ROHM BU9844GUL-W Technical data

A
WL-CSP EEPROM family I2C BUS
BU9844GUL-W
Description
BU9844GUL-W series is a serial EEPROM of I available at 400kHz.
Features
1) Completely conforming to the world standard I and serial data(SDA)
2) Other devices than EEPROM can be connected to the same port, saving microcontroller port.
3) Actions available at 400kHz clock (1.7V~5.5V)
4) 1.75.5V single power source action most suitable for battery use.
5) Page write mode useful for initial value write at factory shipment.
6) Auto erase and auto end function at data rewrite.
7) Low current consumption At write action (5V) : 1.2mA (Typ.) At read action (5V) : 0.2mA (Typ.) At standby action (5V) : 0.1μA (Typ.)
8) Write mistake prevention function Write (write protect) function added. Write mistake prevention function at low voltage.
9) Data rewrite up to 1,000,000times.
10) Data kept for 40 years.
11) Noise filter built in SCL / SDA terminal
12) Shipment data all address FFh.
Page write
Product number Number of pages
2
C BUS interface method. 1.7V single power source action and actions
2
C BUS. All controls available by 2 ports of serial clock (SCL)
No.10001EAT18
BU9844GUL-W
BU9844GUL-W
Type Capacity Bit format Power source voltage Package
BU9844GUL-W
Absolute maximum ratings (Ta=25)
Parameter Symbol Ratings Unit
Impressed voltage Vcc -0.3~+6.5 V
Permissible dissipation Pd 220 *1 mW
Storage temperature range Tstg -65~125
Operating temperature range Topr -40~85
Terminal voltage - -0.3~Vcc+1.0 V
* When using at Ta=25 or higher, 2.2mW (*1) to be reduced per 1
Recommended action conditions
Parameter Symbol Ratings Unit
Power source voltage
Input voltage
16Byte
16Kbit 2048×8 1.7~5.5V VCSP50L1
Vcc 1.7~5.5
V
Vin 0~Vcc
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1/18
2010.09 - Rev.
BU9844GUL-W
A
Memory cell characteristics (Ta=25, Vcc=1.7~5.5V)
Parameter
Min Typ. Max
Limits
Number of data rewrite times *1 1,000,000 - - Times
Technical Note
Unit
Data hold years
*1 Not 100% TESTED
40 - - Years
Electrical characteristics (Unless otherwise specified, Ta=-40~+85, Vcc=1.7~5.5V)
Parameter Symbol
“HIGH” input voltage1 V
“LOW” Input voltage1 V
“HIGH” input voltage2 V
“LOW” input voltage2 V
“LOW” output voltage1 V
“LOW output voltage2 V
Min. Typ. Max.
0.7Vcc - - V 2.5V≦Vcc≦5.5V
IH1
- - 0.3Vcc V 2.5V≦Vcc≦5.5V
IL1
0.9Vcc - - V 1.7V≦Vcc<2.5V
IH2
-
IL2
- - 0.3 V IOL=3.0mA, 2.5V≦Vcc≦5.5V, (SDA)
OL1
- - 0.2 V IOL=1.5mA, 1.7V≦Vcc<2.5V, (SDA)
OL2
Limits
- 0.1Vcc V 1.7V≦Vcc<2.5V
Unit Conditions
Input leak current ILI -1 - 1 μA VIN=0V~Vcc
Output leak current ILO -1 - 1 μA V
I
- - 2.0 mA
CC1
Current consumption at action
I
- - 0.5 mA
CC2
Standby current ISB - - 2.0 μA
This product is not designed for protection against radioactive rays.
=0V~Vcc(SDA)
OUT
Vcc=5.5V, f
=400kHz, tWR=5ms,
SCL
Byte write, Page write
Vcc=5.5V, f
=400kHz
SCL
Random read, Current read, sequential read
Vcc=5.5V, SDA·SCL=Vcc, A2=GND, WP=GND
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2/18
2010.09 - Rev.
BU9844GUL-W
A
ACK
f
A
A
A
A
Action timing characteristics
Technical Note
(Unless otherwise specified, Ta=-40~+85℃, Vcc=1.7~5.5V)
FAST-MODE
Parameter Symbol
2.5VVcc5.5V
STANDARD-MODE
1.7VVcc5.5V
Min. Typ. Max. Min. Typ. Max.
SCL frequency fSCL - - 400 - - 100 kHz
Data clock “HIGH” time tHIGH 0.6 - - 4.0 - - μs
Data clock “LOW” time tLOW 1.2 - - 4.7 - - μs
SDA, SCL rise time *1 tR *1 - - 0.3 - - 1.0 μs
SDA< SCL fall time *1 tF *1 - - 0.3 - - 0.3 μs
Start condition hold time tHD:STA 0.6 - - 4.0 - - μs
Start condition setup time tSU:STA 0.6 - - 4.7 - - μs
Input data hold time tHD:DAT 0 - - 0 - - ns
Input data setup time tSU:DAT 100 - - 250 - - ns
Output data delay time tPD 0.1 - 0.9 0.2 - 3.5 μs
Output data hold time tDH 0.1 - - 0.2 - - μs
Stop condition setup time tSU:STO 0.6 - - 4.7 - - μs
Bus release time before transfer start tBUF 1.2 - - 4.7 - - μs
Internal write cycle time tWR - - 5 - - 5 ms
Noise removal valid period (SDA, SCL terminal) tI - - 0.1 - - 0.1 μs
WP hold time tHD:WP 0 - - 0 - - ns
WP setup time tSU:WP 0.1 - - 0.1 - - μs
WP valid time tHIGH:WP 1.0 - - 1.0 - - μs
*1 Not 100% tested.
Sync data input / output timing
SCL
SDA (Input)
SDA (Output)
SCL
SDA
tHD:STA tHD:DAT tSU:DAT
tBUF tPD tDH
Input read at the rise edge of SCL Data output in sync with the fall of SCL
Fig.-1(a) Sync data input / output timing
tSU:ST
START BIT
Fig.1-(b) Start – stop bit timing
tLOW
tHIGH tR tF
SCL
SDA
WP
DATA(1)
D1 D0ACK
DATA(n)
WR
stop condition
tSU:WP
tHD:
WP
fig.1-(d) WP timing at write execution
SCL
SDA
WP
DATA(1)
D1 D0
CK
tHIGH:WP
tSU :STO tHD:ST
STOP BIT
DATA(n)
CK
tWR
Fig.1-(e) WP timing at write cancel
SCL
SDA
D0 ACK
Write d ata
(n-th address)
Stop conditio n Start condition
tWR
At write execution, in the area from the DO taken clock rise of the first DATA (1),
to tWR, set WP=”LOW”
By setting WP “HIGH” in the area, write can be cancelled. When it is set WP=”HIGH” during tWR, write is forcibly ended, and data o
address under access is not guaranteed, therefore write it once again.
Fig.1-(c) Write cycle timing
Unit
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3/18
2010.09 - Rev.
BU9844GUL-W
A
Block diagram
VCC
GND
9bit
Address
decoder
16Kbit EEPROM array
9bit
Slave – word
address register
A2
High voltage
generating circuti
START STOP
Control circuit
ACK
Power source
voltage detection
Fig.2 Block diagram
Pin assignment and description
C
C1
○○
C2
B
B1 B2
○○
A
A1
○○
A2
Fig.3 BU9844GUL-W(bottom view)
12
Land No. Terminal name Input/ Output Function
A1 VCC
A2 A2 Input
Power Supply Out of Use (Vcc or GND or OPEN)
B1 WP Input Write Protect Input
B2 GND Input
Ground 0V
C1 SCL Input Serial Clock Input
C2 SDA Input /Output
Slave and Word Address,
Serial Data Input, Serial Data Output *1
*1 An open drain output requires a pull-up resistor.
Characteristic data (The following values are Typ. ones.)
6
5
4
3
VIH1,2,3[V]
2
1
0
0123456
SPEC
Ta= 85
Ta= -4 0
Ta= 25
Vcc[V]
6
5
4
Ta= 85
3
VIL1,2,3[V]
Ta= -4 0
2
Ta= 25
1
0
0123456
SPEC
Vcc[V]
Fig.4 H input voltage VIH1,2,3
(A2,SCL,SDA,WP)
Fig.5 L input voltage VIL1,2,3
(A2,SCL,SDA,WP)
Technical Note
8bit
Data
register
INDEX post
1
0.8
0.6
VOL2[V]
0.4
SPEC
0.2
0
0123456
Fig.6 L output voltage VOL2-IOL2
Ta= 85
IOL2[mA]
CC=1.7V)
(V
WP
SCL
SDA
Ta= 25
Ta= -4 0
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© 2010 ROHM Co., Ltd. All rights reserved.
4/18
2010.09 - Rev.
BU9844GUL-W
A
Technical Note
1
0.8
0.6
VOL1[V]
0.4
0.2
0
0123456
SPEC
Ta= 85
IOL1[mA]
Fig.7 L input voltage
VOL1-IOL1 (Vcc=2.5V)
2.5
Ta= 25
Ta= 85
SPEC
1.5
ICC1[mA]
2
fSCL=400kHz DATA=AAh
1
0.5
0
0123456
Vcc[V]
Fig.10 Consumption current
at write action Icc1 (f
10000
1000
Ta= 85
100
fSCL[kHz]
10
1
0123456
SPEC
Vcc[V]
Fig.13 SCL frequency
f
SCL
1
0.8
0.6
0.4
tHD:STA[μs]
0.2
0
0123456
SPEC
Vcc[V]
Fig.16 Start condition hold time
tHD:STA
200
100
0
tSU:DAT(HIGH)[ns]
-100
-200 0123456
Fig.19 Input data setup time
SPEC
Ta= 85
Vcc[V]
tSU:DAT
Ta= 25
Ta= -4 0
Ta= -4 0
SCL=400kHz)
Ta= -4 0 Ta= 25
Ta= 85
Ta= 25
Ta= -4 0
Ta= -4 0
Ta= 25
1.2
SPEC
Vcc[V]
Ta= 85 Ta= 25
Ta= -4 0
1
0.8
0.6
ILI[μA]
0.4
0.2
0
0123456
Fig.8 Input leak current
LI(A2,SCL, WP)
I
0.6
0.5
0.4
0.3
ICC2[mA]
0.2
0.1
0
SPEC
fSCL=400kHz DATA=AAh
Ta= 25
Ta= 85
Ta= -4 0
0123456
Vcc[V]
Fig.11 Consumption current
at write action Icc2 (fSCL=400kHz)
1
0.8
0.6
0.4
tHIGH [μs]
0.2
0
0123456
SPEC
Ta= 85
Ta= 25
Ta= -4 0
Vcc[V]
Fig.14 Data clock “H” time
tHIGH
1
0.8
0.6
0.4
0.2
tHD:DAT(HIGH)[ns ]
0
-0.2 0123456
SPEC
Ta= 85
Ta= 25
Vcc[V]
Fig.17 Start condition setup time
tSU:STA
1
0.8
0.6
0.4
tPD0 [μs]
0.2
0
0123456
Fig.20 Output data delay time
SPEC
Ta= 85
Ta= 25
Ta= -4 0
SPEC
Vcc[V]
tPD0
1.2
1
0.8
0.6
ILO[μA]
0.4
0.2
0
SPEC
Ta= 85
Ta= 25
Ta= -4 0
0123456
Vcc[V]
Fig.9 Output leak current
I
LO (SDA)
2.5
2
1.5
ISB[μA]
1
0.5
0
0123456
Fig.12 Standby current
SPEC
Ta= 85
Ta= 25
Ta= -4 0
Vcc[V]
ISB
1.6
1.2
0.8
tLOW[μs]
0.4
0
0123456
SPEC
Ta= 85
Ta= 25
Vcc[V]
Ta= -4 0
Fig.15 Data clock “L” time
tLOW
50
0
-50
-100
tHD:DAT(HIGH)[ns ]
-150
-200 0123456
SPEC
Ta= 85
Ta= 25
Ta= -4 0
Vcc[V]
Fig.18 Input data hold time
tHD:DAT
1
0.8
0.6
0.4
tPD1 [μs]
0.2
0
0123456
Fig.21 Output data delay time
SPEC
Ta= 85
Ta= 25
Ta= -4 0
SPEC
Vcc[V]
tPD1
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2010.09 - Rev.
BU9844GUL-W
A
Technical Note
1
4
5
0.8
0.6
0.4
tDH0[μs]
0.2
0
SPEC
0123456
Ta= 85
Ta= 25
Ta= -4 0
Vcc[V]
Fig.22 Output data hold time
5
4
3
tBUF[μs]
2
1
0
0123456
tDH1
SPEC
Vcc[V]
Ta= -4 0
Ta= 25
Ta= 85
Fig.25 Bus release time
before transfer start tBUF
0.6
0.5
0.4
SPEC
Ta= -4 0
Ta= 85
Vcc[V]
0.3
Ta= 25
tI(SCL L) [ μs]
0.2
0.1
0
0123456
Fig.28 Noise removal time
Ta= 25
tI (SCL L)
SPEC
Ta= 85
Ta= -4 0
Vcc[V]
0.2
0
-0.2
tSU:WP[μs]
-0.4
-0.6
0123456
Fig.31 WP setup time
tSU:WP
3
2
tDH1[μs]
1
SPEC
0
0123456
Ta= 85
Ta= 25
Ta= -4 0
Vcc[V]
Fig.23 Output data hold time
6
5
4
3
tWR[ms]
2
1
0
0123456
tDH1
SPEC
Ta= 85
Vcc[V]
Ta= -4 0
Ta= 25
Fig.26 Internal write cycle time
0.6
0.5
0.4
0.3
Ta= 25
0.2
tI(SDA H) [μs]
0.1
0
0123456
Fig.29 Noise removal time
1.2
1
0.8
0.6
tHIGH:WP[μs]
0.4
0.2
0
0123456
tWR
Ta= -4 0
Ta= 85
SPEC
Vcc[V]
tI (SDA H)
SPEC
Ta= -4 0
Ta= 25
Ta= 85
Vcc[V]
Fig.32 WP valid time
tHIGH: WP
4
3
2
tSU:STO[μs]
1
0
SPEC
0123456
Vcc[V]
Ta= 85
Ta= 25
Ta= -4 0
Fig.24 Stop condition setup time
Ta= -4 0
tSU:STO
SPEC
Vcc[V]
Ta= 25
Ta= 85
0.6
0.5
0.4
0.3
tI(SCL H) [μs]
0.2
0.1
0
0123456
Fig.27 Noise removal time
0.6
0.5
0.4
0.3
tI(SDA L) [ μs]
0.2
0.1
tI (SCL H)
Ta= -4 0
Ta= 25
SPEC
0
0123456
Fig.30 Noise removal time
Ta= 85
Vcc[V]
tI (SDA L)
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2010.09 - Rev.
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