ROHM BU6520KV, BU6521KV Technical data

AIE Adaptive Image Enhancer Series

Video Encoders
built-in Image Correction

BU6520KV,BU6521KV

●Description

BU6520KV, BU6521KV are video encoders with built-in AIE image correcting function. Also, BU6521KV has the image
correcting function of the fog reduction, too.
Fog Reduction, the brightness correction, the backlight correction and the chroma emphasis can improve the visibility of the
input image of the camera.

* AIE and Fog Reduction function are image processing technology by ROHM’s hardware.

●Features

1) Format of video output is compatible with NTSC/PAL composite video format (CVBS).
Built-in DAC with direct 75Ω drive capability.

2) Built-in Fog Reduction function

3) Input/output data format is compatible with ITU-R BT.656 and YCbCr=4:2:2 with synchronization signal.

4) Compatible with NTSC (27MHz, 28.63636MHz and 19.06993MHz)/
PAL(27MHz, 28.375MHz, 35.46895MHz and 18.9375MHz)

5) Registers can be set up with a 2-line serial interface.

6) Registers can be automatically set up by reading from external EEPROM, when after resetting or changing mode.

*1 As for the Fog Reduction feature, it loads only BU6521KV.
*2 NTSC 19,06993 MHz and PAL 18,9375 MHz support only BU6521KV.

●Applications

Security camera, camera for automotive, drive recorder etc.

●Line up matrix

Part No.

BU6520KV

BU6521KV

Power Sopply

Voltage(V)

1.4 to 1.6
Core)

(V

DD

2.7 to 3.6

(VDDI/O, AVDD)

1.4 to 1.6
Core)

(V

DD

2.7 to 3.6

I/O, AVDD)

(V

DD

Image size

720x480,

SD size

720x480,

SD size

*1

, dynamic range correction, edge-emphasizing filter and gamma filter.

*2

.

Input

Interface

8bit,

YUV=4:2:2,

ITU-R BT.656

8bit,

YUV=4:2:2,

ITU-R BT.656

Control

Interface

2

C,

I

Serial

EEPROM

interface

2

C,

I

Serial

EEPROM

interface

Output

Interface

8bit,

YUV=4:2:2,

ITU-R BT.656

8bit,

YUV=4:2:2,

ITU-R BT.656

Feature

AIE,

Video output

AIE,

Fog reduction,

Video output

I2C BUS is a registered trademark of Philips

Temperature

No.10060ECT03

Operating

Range(℃)

-40 ~ +85 VQFP48C

-40 ~ +85 VQFP48C

Package

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© 2010 ROHM Co., Ltd. All rights reserved.

1/18

2010.02 - Rev.C

BU6520KV,BU6521KV

Technical Note

●Absolute maximum ratings

Parameter Symbol Rating Unit

Supply voltage1 (IO) VDDIO -0.3～+4.2 V

Supply voltage2 (IO) VDDI2C -0.3～+4.2 V

Supply voltage3 (DAC) AVDD -0.3～+4.2 V

Supply voltage4 (CORE) VDD -0.3～+2.1 V

Input voltage range VIN -0.3～IO_LVL+0.3 *1 V

Storage temperature range Tstg -40～+125 ℃

Power dissipation PD 400 *2, 900 *3 mW

*1 IO_LVL is a generic name of VDDIO, VDDI2C, and AVDD.
*2 IC only. In the case exceeding 25ºC, 4.0mW should be reduced at the rating 1ºC.
*3 When packaging a glass epoxy board of 70x70x1.6mm. If exceeding 25ºC, 9.0mW should be reduced at the rating 1ºC.
* Has not been designed to withstand radiation.
* Operation is not guaranteed at absolute maximum ratings.

●Operating conditions

Parameter Symbol Ratings Unit

Supply voltage 1 (IO) VDDIO 2.70 ~ 3.60 (Typ.: 3.30) V

Supply voltage 2 (IO) VDDI2C 2.70 ~ 3.60 (Typ.: 3.30) V

Supply voltage 3 (DAC) AVDD 2.70 ~ 3.60 (Typ.: 3.30) V

Supply voltage 4 (CORE) VDD 1.40 ~ 1.60 (Typ.: 1.50) V

Input voltage range VIN 0.00 ~ IO_LVL *1 V

Operating temperature range Topr -40 ~ +85 ºC

*1 IO_LVL is a generic name of VDDIO, VDDI2C, and AVDD.
* Please supply power source in order of VDD→(VDDIO, VDDI2C, and AVDD).

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© 2010 ROHM Co., Ltd. All rights reserved.

2/18

2010.02 - Rev.C

BU6520KV,BU6521KV

●Block Diagram

[BU6520KV]

Technical Note

CAMDI0

―CAMDI7

CAMHSI
CAMVSI
CAMCKI

[BU6521KV]

8

2-line Serial

Inter fac e

2

C)

(I

SDA SDC

Register

AIE

Tim ing

Genera tor

Serial

Interfac e

(SPI)

SDI SDO SCK SCEB

WPB

Fig.1 BU6520KV Block Diagram

8

Video

Encoder

RESETB TEST AU TO

10bit
DAC

MOD E0
MOD E1

CAMDO0

―CAMDO7

VOU T

IREF

CAMHSO
CAMVSO
CAMCKO

CAMDI0

―CAMDI7

CAMHSI
CAMVSI
CAMCKI

8

Fog reduction

2-line Serial

Inter fac e

2

(I

C)

SDA SDC

Register

AIE

Tim ing

Genera tor

Serial

Interfac e

(SPI)

SDI SDO SCK SCEB

WPB

Fig.2 BU6521KV Block Diagram

Vi de o

Encoder

RESETB TEST AUT O

10bit
DAC

8

MOD E0
MOD E1

CAMDO0

―CAMDO7

VOU T

IREF

CAMHSO

CAMVSO

CAMCKO

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© 2010 ROHM Co., Ltd. All rights reserved.

3/18

2010.02 - Rev.C

BU6520KV,BU6521KV

Technical Note

●Pin functional descriptions・Equivalent circuit

PIN

PIN Name In/Out

No.

Active

Level

Init Function explanation

Power

Source

System

1 SDI In DATA - SPI-bus data input 1 A

2 CAMDI7 In DATA - Data input bit 7 1 C

3 CAMDI6 In DATA - Data input bit 6 1 C

4 CAMDI5 In DATA - Data input bit 5 1 C

5 CAMDI4 In DATA - Data input bit 4 1 C

6 GND - GND - Common GROUND 1,2,4 -

7 VDD - PWR - CORE power source 4 -

8 CAMDI3 In DATA - Data input bit 3 1 C

9 CAMDI2 In DATA - Data input bit 2 1 C

10 CAMDI1 In DATA - Data input bit 1 1 C

11 CAMDI0 In DATA - Data input bit 0 1 C

12 CAMHSI In * - Horizontal timing input 1 C

I/O

type

*1

13 CAMVSI In * - Vertical timing input 1 C

14 CAMCKI In CLK - Clock input 1 E

15 GND - GND - Common GROUND 1,2,4 -

16 VDDIO - PWR - Digital IO power source 1 -

17 CAMDO0 Out DATA Low Data output bit 0 1 F

18 CAMDO1 Out DATA Low Data output bit 1 1 F

19 CAMDO2 Out DATA Low Data output bit 2 1 F

20 CAMDO3 Out DATA Low Data output bit 3 1 F

21 CAMDO4 Out DATA Low Data output bit 4 1 F

22 CAMDO5 Out DATA Low Data output bit 5 1 F

23 CAMDO6 Out DATA Low Data output bit 6 1 F

24 CAMDO7 Out DATA Low Data output bit 7 1 F

※ ” * ” in the Active Level column indicates that it may be changed during set-up of the register.
※ Init column indicates pin status when released from reset.
※ In the power system column, ” 1 ” stands for VDDIO, ” 2 ” stands for VDDI2C, ” 3 ” stands for AVDD, ” 4 ” stands for VDD.

*1 Fig.3 Equivalent Circuit Structures of input / output pins reference

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© 2010 ROHM Co., Ltd. All rights reserved.

4/18

2010.02 - Rev.C

BU6520KV,BU6521KV

Technical Note

PIN

PIN Name In/Out

No.

Active

Level

Init Function explanation

Power
Source
System

25 CAMHSO Out * Low Horizontal timing output 1 F

26 CAMVSO Out * Low Vertical timing output 1 F

27 CAMCKO Out CLK Low Clock output 1 F

28 GND - GND - Common GROUND 1,2,4 -

29 VDD - PWR - CORE power source 4 -

30 AUTO In High PD *2 Auto register setting enable signal 1 D

31 MODE0 In DATA PD *2 Auto register setting mode select bit 0 1 D

32 MODE1 In DATA PD *2 Auto register setting mode select bit 1 1 D

33 VOUT Out Analog - Analog composite output 3 H

34 AVSS - GND - Analog GROUND for DAC 3 -

35 IREF Out Analog - Reference voltage for DAC 3 I

36 AVDD - PWR - Analog power source for DAC 3 -

I/O

type

*1

37 GND - GND - Common GROUND 1,2,4 -

38 VDDI2C - PWR -

Digital IO power source
(For 2-line serial interface input/output)

2 -

39 SDA In/Out DATA In 2-line serial interface data input/output 2 G

40 SDC In/Out CLK In 2-line serial interface clock input 2 G

41 RESETB In Low - System reset signal 1 B

42 TEST In High PD *2 Test mode terminal (Connect to GND) 1 D

43 GND - GND - Common GROUND 1,2,4 -

44 VDDIO - PWR - Digital IO power source 1 -

45 WPB Out Low Low Write protect signal to EEPROM 1 F

46 SCEB Out Low High Chip select signal to EEPROM 1 F

47 SCK Out CLK Low SPI-bus clock 1 F

48 SDO Out DATA Low SPI-bus data output 1 F

※ ” * ” in the Active Level column indicates that it may be changed during set-up of the register.
※ Init column indicates pin status when released from reset.
※ In the power system column, ” 1 ” stands for VDDIO, ” 2 ” stands for VDDI2C, ” 3 ” stands for AVDD, ” 4 ” stands for VDD.

*1 Fig.3 Equivalent Circuit Structures of input / output pins reference
*2 Pull-down status.

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© 2010 ROHM Co., Ltd. All rights reserved.

5/18

2010.02 - Rev.C

BU6520KV,BU6521KV

Technical Note

Type Equivalent circuit configuration Typ Equivalent circuit configuration

A

Input terminal

VDDIO VDDIO

To internal

circuit

GND

GND

VDDIO

B

GND

Input terminal with hysteresis

To internal

circuit

VDDIO

Internal signal

VDDIO

C

GND

Input terminal with suspend

VDDIO

E

GND

Input terminal with hysteresis and suspend

G

VDDI2C

VDDI2C

To internal

circuit

GND

GND

GND

Input/Output terminal

GND

To internal

Internal signal

VDDI2C

Internal signal

Internal signal

Internal signal

To internal

circuit

circuit

VDDIO

D

GND

Input terminal with pull down

F

Output terminal

H

VOUT

VDDIO

GND

GND

AVDD

AVSS

VDDIO

VDDIO

AVDD

Internal signal

To internal

circuit

GND

Internal signal

GND

Internal signal

Internal signal

AVDD

AVDD

I

AVSS

Internal signal

IREF

Fig.3 Equivalent Circuit Structures of input / output pins

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© 2010 ROHM Co., Ltd. All rights reserved.

Internal signal

Internal signal

To internal

circuit

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2010.02 - Rev.C