ROHM BU1851GUW Technical data

GPIO ICs Series

Key Encoder IC

BU1851GUW

No.09098EAT03

●Description
Key Encoder IC can monitor up to 8x8 matrix (64 keys), which means to be adaptable to Qwerty keyboard. We adopt the
architecture that the information of the only key which status is changed, like push or release, is encoded into the 8 bits
data. This can greatly reduce the CPU load which tends to become heavier as the number of keys increase.
(Previously, all key's status is stored in the registers.)
Furthermore, auto sleep function contribute to low power consumption, when no keys are pressed. It is also equipped with
the various functions such as ghost key rejection, N-key Rollover, Built-in power on reset and oscillator.

●Features

1) Monitor up to 64-matrix keys

2) Under 5A Stand-by Current

3) Built-in Power On Reset

4) Ghost key rejection

●Absolute maximum ratings
(Ta=25℃)

Item Symbol Value Unit comment
Supply Voltage*1 VDD -0.3 ~ +4.5 V
Input voltage VI -0.3 ~ VDD +0.3*1 V
Storage temperature range Tstg -55 ~ +125

℃

Package power PD 272*2 mW

This IC is not designed to be X-ray proof.

*1

It is prohibited to exceed the absolute maximum ratings even including +0.3 V.

*2

Package dissipation will be reduced each 2.72mW/ oC when the ambient temperature increases beyond 25 oC.

●Operating Conditions
Limit

Item Symbol

Unit Condition

Min Typ Max
Supply voltage range（VDD） VDD 2.20 3.30 3.60 V
Input voltage range VIN -0.2 - VDD+0.2 V

Operating temperature range Topr -30 25 +85 ℃
External clock Fclk 0.8 1.0 1.2 MHz CLKSEL=VDD

External resistor Rxi 118.8 120 121.2 kΩ To Xi pin, when CLKSEL=VSS

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© 2009 ROHM Co., Ltd. All rights reserved.

2009.09 - Rev.A

BU1851GUW

● Package Specification

Technical Note

U1851

Lot No.

Fig.1 Package Specification（VBGA035W040）

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© 2009 ROHM Co., Ltd. All rights reserved.

2009.09 - Rev.A

BU1851GUW

● Pin Assignment

Technical Note

1 2 3 4 5

TESTM0 XRST XO XI ROW0

A

B

KINT VDD VSS PORENB ROW4

C

KSDA VDD VSS VSS ROW6

D

KSCL COL6 COL4 COL2 COL0

E

TESTM1 COL7 COL5 COL3 COL1FTESTM2

CLKSEL VDD VDD ROW2

Fig.2 Pin Diagram（Top View）

6

TESTM3

ROW1

ROW3

ROW5

ROW7

● Block Diagram

VDD

TESTM[3:0]

KINT

KSCL

KSDA

XRST

PORENB

VSS

3wire

Control

3wire

Timeout

Power

On

Reset

XIXO CLKSEL

Oscillator

Key

Encoder

Key Scan

Reset

Gen

Fig.3 Functional Block Diagram

8bit

8bit

Column

Drive

Row

Monitor

8bit

8bit

COL[7:0]

ROW[7:0]

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© 2009 ROHM Co., Ltd. All rights reserved.

2009.09 - Rev.A

BU1851GUW

● Pin-out Functional Descriptions

PIN name I/O Function Init

VDD - Power supply (Core, I/O) - ­VSS - GND - ­XRST I Reset（Low Active） I A

CLKSEL I

XI I

XO O Test pin*1 L C
KINT O Key Interrupt H C
KSCL I Clock for serial interface I A

KSDA I/O Serial data inout for serial interface I D
ROW0 I

ROW1 I

H: External clock is used

L: Internal CR oscillator is used

External clock input when “CLKSEL” is H.

120k is attached up to VDD when “CLKSEL”

is L.

Technical Note

Cell

Type

I B

I G

ROW2 I
ROW3 I
ROW4 I

Row input from key matrix

(Pull-up)

I

Pull-up

E

ROW5 I
ROW6 I
ROW7 I
COL0 O
COL1 O
COL2 O
COL3 O

Column output to key matrix L C

COL4 O
COL5 O
COL6 O
COL7 O
PORENB I Power on reset enable (Low Active) I B
TESTM0 I
TESTM1 I

Test Pin

*2

I F

TESTM2 I
TESTM3 I

*1

Note: This pin must be open in normal operation.

*2

Note: All these pins must be tied down to GND in normal operation.

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© 2009 ROHM Co., Ltd. All rights reserved.

2009.09 - Rev.A