ROHM BU1850MUV Technical data
GPIO ICs Series
GPIO Expander IC
BU1850MUV
●Description
GPIO expander is useful especially for the application that is in short of IO ports.
It can
1. Control GPIO output states by I
2. Know GPIO input states by I
Furthermore,it has the interrupt function that can release CPU from polling the registers in the GPIO expander.
GPIO expander are also equipped with Built-in power on reset, 3V tolerant input,and NMOS open-drain output.
●Features
1) An 8-Port General purpose input/output interface 150kΩPull-down resistance.
2) NMOS Open-drain output interrupt controller with up to 1us pulse noise filter and bit mask function for
individual GPIO port.
3) 3volt tolerant Input
4) Built-in Power On Reset
5) 3mmx3mm small package
●Absolute maximum ratings
(Ta=25
o
C)
Parameter Symbol Rating Unit comment
Supply Voltage*1
Input voltage
Storage temperature range Tstg -55 ~ +125
Package power PD 272*2 mW
2
C write protocol.
2
C read protocol.
VDD -0.3 ~ +4.5 V VDD≦VDDIO
VDDIO -0.3 ~ +4.5 V
VI -0.3 ~ VDD +0.3
*1
V XRST, ADR
VIT -0.3 ~ 4.5 V XINT, SCL, SDA, GPIO[7:0]
℃
No.09098EAT02
This IC is not designed to be X-ray proof.
*1 It is prohibited to exceed the absolute maximum ratings even including +0.3 V.
*2 Package dissipation will be reduced each 2.72mW/
o
C when the ambient temperature increases beyond 25 oC.
●Operating conditions
Parameter Symbol Min Typ Max Unit Conditions
Core, XINT, XRST,
Supply voltage range (VDD) V
1.65 1.80 3.6 V
VDD
SCL, SDA, ADR,
Power On Reset
Supply voltage range (VDDIO) V
Input voltage range
1.65 1.80 3.6 V GPIO[7:0]
VDDIO
-0.2 - V
V
IN
V
-0.2 - 3.6 V
INT
+0.2 V XRST, ADR
VDD
XINT, SCL, SDA,
GPIO[7:0]
Operating temperature range Topr -30 - +85 ℃
I2C operating frequency F
- - 400 kHz Slave
I2C
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© 2009 ROHM Co., Ltd. All rights reserved.
2009.09 - Rev.A
BU1850MUV
●Package Specification
Technical Note
B U 1
8 5 0
Lot No.
(UNIT: mm)
Fig.1 Package Specification (VQFN016V3030)
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© 2009 ROHM Co., Ltd. All rights reserved.
2009.09 - Rev.A
BU1850MUV
●Pin Assignment
12 GPIO3
11 GPIO2
10 GPIO1
Technical Note
9 GPIO0
●Block Diagram
13 GPIO4
14 GPIO5
15 GPIO6
16 GPIO7
1 XINT
2 XRST
3 SCL
4 ADR
Fig.2 Pin Diagram (Top View)
Functional Block Diagram
8 VSS
7 VDDIO
6 VDD
5 SDA
XINT
VDD
ADR
SCL
SDA
XRST
VSS
Interrupt
Filter
Input
Filter
Power
On
Reset
Reset
Gen
Interrupt
Logic
I2C Bus
Control
INT_MASK
IN/OUT
Control
Shift
8bit
Register
Write Pulse
Read Pulse
Fig.3 Functional Block Diagram
GPIO
[7:0]
8bit
VDDIO
GPIO[7:0]
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© 2009 ROHM Co., Ltd. All rights reserved.
2009.09 - Rev.A
BU1850MUV
●Pin-out Functional Descriptions
PIN
No.
1 XINT O VDD
2 XRST I VDD Reset（Low Active） I E
3 SCL I VDD Clock for I2C I A
4 ADR I VDD Select dev ice address of I2C I E
5 SDA I/O VDD
6 VDD - 7 VDDIO - - Power supply (I/O) - -
8 VSS - - GND - 9 GPIO0 I/O VDDIO
10 GPIO1 I/O VDDIO
PIN name I/O
Power source
system
Function Init
Interrupt signal (1s pulse cut)*1
(NMOS Open-drain)
2
Serial data inout for I
(NMOS Open-drain)
Power supply (Core, I/O, Power On
Reset)
C
Technical Note
Cell
Type
Hi-Z B
Hi-Z C
- -
11 GPIO2 I/O VDDIO
12 GPIO3 I/O VDDIO
13 GPIO4 I/O VDDIO
14 GPIO5 I/O VDDIO
15 GPIO6 I/O VDDIO
16 GPIO7 I/O VDDIO
*1 Specific bit mask control is decided by internal register value.
*2
Pull-up more than VDDIO voltage.
It is possible to select Pull-down ON or OFF with register.
*3
A
B
General purpose input/output.
(NMOS Open-drain
150kΩPull-down
*2
/CMOS Output,
C
I
*3
)
Pull-down
D
D
E
Fig.4 Equivalent IO circuit diagram
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© 2009 ROHM Co., Ltd. All rights reserved.
2009.09 - Rev.A
BU1850MUV
Technical Note
●Functional Description
1. Power Modes
The device enters the state of Power Down when XRST=”Low” or enters the operation state when XRST=High after
powered.
Refer to “Electrical Specification” section 5 for a detailed startup sequence.
1-1 Power supply
A single supply to Core power supply (VDD) and IO power supply (VDDIO) is prohibited.
Supply the power supply to the Cor e power supply and the IO power supply at the same time.
1-2 Power On Reset
A Power On Reset logic is implemented in this device. Therefore, it will operate correctly eve n if the XRST port is
not used. In this case, the XRST port must be connected to high(VDD).
1-3 State of Power Down
The device enters the state of Power Down by XRST =”Low”. An internal circuit is initialized and I
2
C interface is
invalid is input. Power On Reset becomes inactive during this state.
1-4 State of operation
The device enters the operation state by setting XRST to "High". The I
2
C interface starts communication is
the START condition. It becomes standby by the STOP condition. Power On Reset is active in this state.
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© 2009 ROHM Co., Ltd. All rights reserved.
2009.09 - Rev.A
BU1850MUV
Technical Note
2
C Bus Interface
2. I
Each function of GPIO is controlled by an internal register. The I
2
C Slave interface is used to write or read this internal
register. The device supports up to 400kHz Fast-mode data transfer rate.
2-1 Slave address
Two device addresses (Slave address) can be selected by ADR port.
ADR=0
ADR=1
A7 A6 A5 A4 A3 A2 A1 R/W
0 0 0 1 0 0 1
0 0 0 1 1 1 0
2-2 Data transfer
One bit of data is transferred during SCL = “1”. During the bit transfer SCL = “1” cycle, the signal SDA should
keep the value. If SDA changes during SCL = “1”, a START condition or STOP condition occur and it is interpreted
as a control signal.
SDA
SCL
Data is valid
when SDA is
stable
SDA is
variable
1/0
Fig.5 Data transfer
2-3 START-STOP-Repeated START conditions
When SDA and SCL are “1”, the data isn’t transferred on the 2-wire bus. If SCL remains “1” and SDA transfers
from “1” to “0”, it means a “Start condition” is occurred and access is started.
If SCL remains “1” and SDA transfers from “0” to “1”, it means a “Stop condition” is occurred and access is
stopped.
It becomes repeated START condition (Sr) the START condition enters again although the STOP condition is not
done.
SDA
SCL
START Condition Repeated START Condition
S Sr
P
STOP Condition
Fig.6 START-STOP-Repeated START conditions
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© 2009 ROHM Co., Ltd. All rights reserved.
2009.09 - Rev.A
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