●Description
These devices control are simple. It requires only 3.3V source and a few GPIO controls.
Termination resistors (50Ω) are integrated at all TMDS input port. When channel is not selected, TMDS input termination
resistors are turned off and TMDS inputs are high impedance. These devices are also integrated equalizer circuit to adapt
long cable and DDC active buffer function to isolate capacitance.
●Features
1) Supports 2.25 Gbps signaling rate for 480i/p, 720p, and 1080i/p resolution to 12-bit color depth
●Absolute Maximum Rating
Over operating free-air temperature range (unless otherwise noted)
Item Limits
BU16006KVBU16018KVBU16024KVBU16027KV
Unit
Power supply voltage(Vcc) -0.3~+4.5 -0.3~+4.5 -0.3~+4.5 -0.3~+4.5 V
DDC, HPD_SINK input voltage -0.3~+5.6 -0.3~+5.6 -0.3~+5.6 -0.3~+5.6 V
Differential input voltage +2.5~+4.0 +2.5~+4.0 +2.5~+4.0 +2.5~+4.0 V
Control pin input voltage -0.3~+4.0 -0.3~+4.0 -0.3~+4.0 -0.3~+4.0 V
Power dissipation 1000(*1) 1200(*2) 950(*3) 1000(*1) mW
Strage temperture range -55~+125 -55~+125 -55~+125 -55~+125 ℃
(*1-3) 70mm×70mm×1.6mm glass epoxy board mount.(Reverse Cu occupation rate:15mm×15mm)
(*1) When it’s used by than Ta=25℃, it’s reduced by 10.0mW/℃.
(*2) When it’s used by than Ta=25℃, it’s reduced by 12.5mW/℃.
(*3) When it’s used by than Ta=25℃, it’s reduced by 9.5mW/℃.
●Recommended Operating Conditions
Symbol Parameter Min. Typ. Max. Unit
VCC Supply voltage 3 3.3 3.6 V
TA Free-air temperature 0 - 70 ℃
TMDS Differential Pins
VIC Input common mode voltage, see Figure 2. VCC–0.6- VCC+0.01V
V
Resistor for TMDS compliant voltage swing range 4.60 4.64 4.68 k Ω
VSADJ
AVCC TMDS Output termination voltage, see Figure 1. 3 3.3 3.6 V
RT Termination resistance, see Figure 1. 45 50 55 Ω
Signaling rate - - 2.25 Gbps
Control Pins
VIH LVTTL High-level input voltage 2 - VCC V
VIL LVTTL Low-level input voltage GND - 0.8 V
HPD_SINK
VIH High-level input voltage 2.4 - 5.5 V
VIL Low-level input voltage GND - 0.8 V
RX (SDA[n],SCL[n])
VIH High-level input voltage 2.4 - 5.5 V
VIL Low-level input voltage GND - 0.8 V
TX (SCL_SINK, SDA_SINK)
VIH High-level input voltage 1.5 - 5.5 V
VIL Low-level input voltage GND - 0.35 V
DDC I/O Pins (SCL, SCL_SINK, SDA, SDA_SINK) See Figure 4
Technical Note
Limits Unit
Max.
ps
ps
ps
ps
ps
ps
t
pdLHTR(DDC)
Propagation delay time, low to high level
output Tx to Rx
= 4.7kΩ, CL = 100pF,
R
L
- 650 - ns
see Figure 5
t
pdHLTR(DDC)
t
pdLHRT(DDC)
t
pdHLRT(DDC)
tr Tx
DDC
tf Tx
DDC
tr Rx
DDC
tf Rx
DDC
Propagation delay time, high to low level
output Tx to Rx
Propagation delay time, low to high level
output Rx to Tx
Propagation delay time, high to low level
output Rx to Tx
Tx output Rise time
Tx output Fall time - 150 - ns
Rx output Rise time
Rx output Fall time - 50 - ns
R
= 1.67kΩ, CL = 400pF,
L
see Figure 5
R
= 4.7kΩ, CL = 100pF,
L
see Figure 5
R
= 1.67kΩ
L
C
= 400pF
L
- 200 - ns
- 500 - ns
- 350 - ns
- 800 - ns
- 950 - ns
tsx Select to switch output see Figure 4 - 8 - ns
t
Disable time see Figure 4 - 5 - ns
dis
ten Enable time see Figure 4 - 7 - ns
t
Switch time from SCLn to SCL_SINK CL=10pF - 800 - ns
sx(DDC
CIO Input/output capacitance VI=0V - 15 - pF
Hot Plug Detect Pins
t
pdLH(HPD)
t
pdHL(HPD)
t
sx(HPD)
Propagation delay time, low to high level
output from HPD_SINK to HPDn(n=1,2,3)
Propagation delay time, high to low level
output from HPD_SINK to HPDn(n=1,2,3)
Switch time from port select to the latest
valid status of HPD
CL=10pF - 5 - ns
CL=10pF - 5 - ns
=10pF - 8 - ns
C
L
Note: (1). All typical values are at 25℃ and with a 3.3V supply.