ROHM BD9486F Datasheet

t

LED Drivers for LCD Backlights

1ch Boost up type
White LED Driver for large LCD

BD9486F

1.1 General Description

BD9486F is a high efficiency driver for white LEDs and is
designed for large LCDs. BD9486F has a boost DCDC
converter that employs an array of LEDs as the light
source.
BD9486F has some protect functions against fault
conditions, such as over-voltage protection (OVP), over
current limit protection of DCDC (OCP), LED OCP
protection, and Over boost protection (FBMAX).
Therefore it is available for the fail-safe design over a
wide range output voltage.

Features

 DCDC converter with current mode
 VOUT discharge function at shutdown
 LED protection circuit (Over boost protection, LED

OCP protection)

 Over-voltage protection (OVP) for the output voltage

Vout

 Adjustable soft start
 Adjustable oscillation frequency of DCDC
 Wide range of analog dimming 0.2V to 3.0V
 UVLO detection for the input voltage of the power

stage

Applications

 TV, Computer Display, LCD Backlighting

1.3 Typical Application Circuit(s)

Figure 2. Typical Application Circuit

Key Specifications

 Operating power supply voltage range:9.0V to 18.0V
 Oscillator frequency of DCDC: 150kHz (RT=100kΩ)
 Operating Current: 2.6mA(Typ.)
 Operating temperature range: -40°C to +85°C

1.2 Package(s) W(Typ) x D(Typ) x H(Max)

SOP16 10.00mm x 6.20mm x 1.71mm

Figure 1. SOP16

Datashee

Pin pitch 1.27mm

○Product structure：Silicon monolithic integrated circuit ○This product has not designed protection against radioactive rays
.

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Datasheet

●1.4 Absolute Maximum Ratings (Ta=25°C)
Parameter Symbol

Ratings Unit

Power Supply Voltage Vccmax 20 V

STB, OVP, UVLO, PWM, ADIM
Terminal Voltage
SS, RT, ISENSE, FB, CS, CP,
REG50 Terminal Voltage
DIMOUT, GATE Terminal
Voltage

Power Dissipation Pd 625

STB, OVP, UVLO,

PWM, ADIM

SS, RT, ISENSE, FB, CS,

CP, REG50

20 V

7 V

DIMOUT, GATE VCC V

(Note 1)

mW

Operating Temperature Range Topr -40 to +85 °C

Junction Temperature Tjmax 150 °C

Storage Temperature Range Tstg -55 to +150 °C

(Note 1) In the case of mounting 1 layer glass epoxy base-plate of 70mm×70mm×1.6mm, derate by 5.0mW/°C when operating above
Ta=25°C.

●1.5 Operating Ratings

Parameter Symbol Range Unit

Power Supply Voltage VCC 9.0 to 18.0 V

DC/DC Oscillation Frequency fsw 50 to 800 kHz

Effective Range of ADIM Signal VADIM 0.2 to 3.0 V

PWM Input Frequency FPWM 90 to 2000 Hz

●1.6 External Components Recommended Range

Parameter Symbol Range Unit

REG50 Connection Capacitance C

0.5 to 10

REG50

SS Connection Capacitance CSS 0.001 to 2.2

(Note 2)

μF

(Note 2)

μF

RT Connection Resistance RRT 15 to 300 kΩ

GATE Drive Capacitance C

(Note 2) Please set connection capacitance above Min value of Recommended Range according to temperature characteristic
and DC bias characteristic.

to 1000 pF

GATE

●1.7 Pin Configuration ●1.8 Physical Dimension and Marking Diagram

BD9486F

Lot No.

Figure 3. Pin Configuration Figure4. Physical Dimension and Marking Diagram of SOP16

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●1.9 Electrical Characteristics (Unless otherwise specified, Ta=25°C，VCC=12V)

Parameter Symbol

【Total Current Consumption】

Circuit Current Icc － 2.6 5.2 mA

Circuit Current (standby) IST

【UVLO Block】

Operation Voltage（VCC） VUVLO_VCC 6.5 7.5 8.5 V VCC=SWEEP UP
Hysteresis Voltage（VCC）

UVLO Release Voltage VUVLO 2.88 3.00 3.12 V VUVLO=SWEEP UP

UVLO Hysteresis Voltage VUHYS 250 300 350 mV VUVLO=SWEEP DOWN

UVLO Pin Leak Current UVLO_LK -2 0 2 μA VUVLO=4.0V

【DC/DC Block】

ISENSE Threshold Voltage 1 VLED1 0.225 0.233 0.242 V VADIM=0.7V

ISENSE Threshold Voltage 2 VLED2 0.656 0.667 0.677 V VADIM=2.0V

ISENSE Threshold Voltage 3 VLED3 0.988 1.000 1.012 V VADIM=3.0V

ISENSE Clamp Voltage VLED4 0.989 1.015 1.040 V

Oscillation Frequency FCT 142.5 150 157.5 KHz RT=100kΩ

RT Short Protection Range RT_DET -0.3 -

RT Terminal Voltage VRT 1.6 2.0 2.4 V RT=100kΩ

RT Pin ON Resistance at OFF RRT_L - 2.0 4.0 kΩ At latch off

GATE Pin MAX DUTY Output MAX_DUTY 90 95 99 % RT=100kΩ
GATE Pin ON Resistance

(as source)
GATE Pin ON Resistance
(as sink)

SS Pin Source Current ISSSO -3.75 -3.0 -2.25 μA VSS=2.0V

SS Pin ON Resistance at OFF RSS_L - 3.0 5.0 kΩ

Soft Start Ended Voltage VSS_END 3.52 3.70 3.88 V SS=SWEEP UP

FB Source Current IFBSO -115 -100 -85 μA

FB Sink Current IFBSI 85 100 115 μA

OCP Detect Voltage VCS 360 400 440 mV CS=SWEEP UP

OCP Latch Off Detect Voltage VCS 0.85 1.00 1.15 V CS=SWEEP UP

【DC/DC Protection Block】

OVP Detect Voltage VOVP 2.88 3.00 3.12 V VOVP SWEEP UP

OVP Detect Hysteresis VOVP_HYS 150 200 250 mV VOVP SWEEP DOWN

OVP Pin Leak Current OVP_LK -2 0 2 μA VOVP=4.0V, VSTB=3.0V

VUHYS_VCC 150 300 600 mV VCC=SWEEP DOWN

RONSO 2.5 5.0 10.0 Ω

RONSI 2.0 4.0 8.0 Ω

Min. Typ. Max.

－

Limit

40 80 μA VSTB=0V

VRT

×90%

Unit Condition

VSTB=3.0V, PWM=3.0V,
GATE=L,IREG50=0mA

VADIM=3.3V
(at masked analog dimming)

V RT=SWEEP DOWN

VISENSE=0.2V, VADIM=3.0V,
VFB=1.0V
VISENSE=2.0V, VADIM=3.0V,
VFB=1.0V

Datasheet

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●1.9 Electrical Characteristics (Unless otherwise specified, Ta=25°C，VCC=12V)

Parameter Symbol

【LED Protection Block】

LED OCP Detect Voltage VLEDOCP 2.88 3.0 3.12 V VISENSE=SWEEP UP

Over Boost Detection Voltage VFBH 3.84 4.00 4.16 V VFB=SWEEP UP

【Dimming Block】

ADIM Pin Leak Current ILADIM -2 0 2 μA VADIM=2.0V

ISENSE Pin Leak Current IL_ISENSE -2 0 2 μA VISENSE=4.0V
DIMOUT Source ON

Resistance
DIMOUT Sink ON Resistance RONSI 4.0 8.0 16 Ω

【REG50 Block】

REG50 Output Voltage 1 REG50_1 4.95 5.00 5.05 V IO=0mA

REG50 Output Voltage 2 REG50_2 4.925 5.00 5.075 V IO=-5mA

REG50 Available Current | IREG50 | 5 - - mA

REG50_UVLO Detect Voltage REG50_TH 2.0 2.3 2.6 V

REG50 Discharge Current REG50_DIS 3.0 5.0 7.0 μA

【STB Block】

STB Pin HIGH Voltage STBH 2.0 - 18 V

STB Pin LOW Voltage STBL -0.3 - 0.8 V

STB Pull Down Resistance RSTB 600 1000 1400 kΩ VSTB=3.0V

【PWM Block】

PWM Pin HIGH Voltage PWM_H 1.5 - 18 V

PWM Pin LOW Voltage PWM_L -0.3 - 0.8 V

PWM Pin Pull Down Resistance RPWM 600 1000 1400 kΩ VPWM=3.0V

【FAIL Block 】

CP Detect Voltage VCP 2.85 3.0 3.15 V VCP=SWEEP UP

CP Charge Current ICP 2.7 3.0 3.3 μA

RONSO 5.0 10 20 Ω

Min. Typ. Max.

Limit

Unit Condition

VREG50=SWEEP DOWN
VSTB=0V
STB=ON->OFF, REG50=4.0V,
PWM=L

Datasheet

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●2.1 Pin Function

No.

1 REG50 Out

2 STB In IC ON/OFF pin -0.3 to 20

3 OVP In Over voltage protection detection pin -0.3 to 20

4 UVLO In Under voltage lock out detection pin -0.3 to 20

5 SS Out Slow start setting pin -0.3 to 7

6 PWM In External PWM dimming signal input pin -0.3 to 20

7 CP Out Charge timer for abnormal state -0.3 to 7

8 ADIM In ADIM signal input pin -0.3 to 20

9 RT Out DC/DC switching frequency setting pin -0.3 to 7

10 FB Out Error amplifier output pin -0.3 to 7

11 ISENSE In LED current detection input pin -0.3 to 7

12 GND - -

13 DIMOUT Out Dimming signal output for NMOS -0.3 to VCC

14 GATE Out DC/DC switching output pin -0.3 to VCC

15 CS In

16 VCC In Power supply pin -0.3 to 20

Pin

Name

IN/OUT Function

5.0V output voltage pin and shutdown
timer pin

DC/DC output current detect pin,
OCP input pin

Rating [V]

-0.3 to 7

-0.3 to 7

Datasheet

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●2.2 Pin ESD Type

OVP UVLO SS

Datasheet

UVLO

REG50

RT

50k

5V

REG50 CP

ADIM FB DIMOUT / VCC

20k

5V

ADIM

VCC

DIMOUT

100k

VCC

GND

GATE / VCC / CS PWM / STB ISENSE

VCC

PWM

STB

VCC

100k

GATE

GND

100k

5V

1M

100k

CS

5V

1M

Figure 5. Pin ESD Type

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●2.3 Block Diagram

Datasheet

Figure 6. Block Diagram

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●2.4 Typical Performance Curves (Reference data)

Figure 7. Circuit current (active) Figure 8. Fsw vs RT characteristic

Datasheet

Figure 9. FB sink current vs FB voltage characteristic Figure 10. FB source current vs FB voltage characteristic

Figure 11. ISENSE feedback voltage vs ADIM voltage characteristic

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●2.5 Pin Description

○Pin 1: REG50

This is the 5.0V(typ.) output pin. Available current is 5mA (min).
And this terminal is also used as timer for discharging DCDC output capacitor.
Please refer to section“3.2.2 Shutdown Method and REG50 Capacitance Setting”, for detailed explanation.

○Pin 2: STB

This is the ON/OFF setting terminal of the IC. Input reset-signal to this terminal to reset IC from latch-off.

At startup, internal bias starts at high level, and then PWM DCDC boost starts after PWM rise edge inputs.
Note: IC status (IC ON/OFF) transits depending on the voltage inputted to STB terminal. Avoid the use of intermediate
level (from 0.8V to 2.0V).
In order to discharge output voltage while STB=L and REG50UVLO=H, DIMOUT can assert High, depending on PWM
logic. About discharge behavior at end, please refer to section “3.5.3 Timing Chart” or section “3.2.2 Shutdown Method
and REG50 Capacitance Setting”.

○Pin 3: OVP

The OVP terminal is the input for over-voltage protection. If OVP is more than 3.0V(typ), the over-voltage protection
(OVP) will work. At the moment of these detections, it sets GATE=L, DIMOUT=L and starts to count up the abnormal
interval. If OVP detection continued to count four GATE clocks, IC reaches latch off. (Please refer to “3.5.5 Timing Chart”)
The OVP pin is high impedance, because the internal resistance is not connected to a certain bias.
Even if OVP function is not used, pin bias is still required because the open connection of this pin is not a fixed potential.
The setting example is separately described in the section ”3.2.7 OVP Setting”.
As PWM=L interval, IC operates to keep the OVP pin voltage therefore the output voltage. Please refer the section “TBD
the Retaining Function of The Output Voltage”.

○Pin 4: UVLO

Under Voltage Lock Out pin is the input voltage of the power stage. , IC starts the boost operation if UVLO is more than

3.0V(typ) and stops if lower than 2.7V(typ).
The UVLO pin is high impedance, because the internal resistance is not connected to a certain bias.
Even if UVLO function is not used, pin bias is still required because the open connection of this pin is not a fixed
potential.
The setting example is separately described in the section ”3.2.6 UVLO Setting”

○Pin 5: SS

This is the pin which sets the soft start interval of DC/DC converter. It performs the constant current charge of 3.0 μA to
external capacitance Css. The switching duty of GATE output will be limited during 0V to 3.7V of the SS voltage.
So the soft start interval Tss can be expressed as follows

Tss = 1.23*10

The logic of SS pin asserts low is defined as the latch-off state or PWM is not input high level after STB reset release.
When SS capacitance is under 1nF, take note if the in-rush current during startup is too large, or if over boost detection
(FBMAXI) mask timing is too short.
Please refer to soft start behavior in the section “3.5.4 Timing Chart ”.

○Pin 6: PWM

This is the PWM dimming signal input terminal. The high / low level of PWM pins are the following.

○Pin 7: CP

Timer pin for counting the abnormal state of the over boost protection (FBMAX). If the abnormal state is detected, the CP
pin starts charging the external capacitance by 3μA. As the CP voltage reaches 3.0V, IC will be latched off. (GATE=L,
DIMOUT=L).
Please refer to section“3.2.8 Interval Until Latch Off Setting”, for detailed explanation.

○Pin 8: ADIM

This is the input pin for analog dimming signal. The ISENSE feedback point is set as 1/3 of this pin bias. If more than 3.0V
is input, ISENSE feedback voltage is clamped to limit to flow LED large current. In this condition, the input current is
caused. Please refer to <ISENSE> terminal explanation.

6

*Css Css: the external capacitance of the SS pin.

State PWM input voltage

PWM=H PWM=1.5V to 18.0V

PWM=L

PWM=‐0.3V to 0.8V

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Datasheet

○Pin 9: RT

This is the DC/DC switching frequency setting pin. DCDC frequency is decided
by connected resistor.

○The relationship between the frequency and RT resistance value (ideal)

R

RT

15000

SW

　]k[



]kHz[f

The oscillation setting ranges from 50kHz to 800kHz.

The setting example is separately described in the section ”3.2.5 DCDC

Oscillation Frequency Setting”

Figure 12. RT terminal circuit example

The fail logic indicating the abnormal state can be obtained by using the right
circuit example. The gate capacitor is limited to 200pF. We recommend
RE1C001VN for M1.The RT pin output the 2.0V(typ.) in the normal state and
drops to 0V in the latch off state. When REG50 reaches to 0V,there is a point
that FAIL output voltage is unstable, if this is a problem, please add C1 capacitor.
Please refer to section “2.7 Behavior List of the Protect Functions” or “3.5 Timing
Chart”.

○Pin 10: FB

CH1:

STB

CH2:
REG50

CH3:
FAIL

This is the output terminal of error amplifier.
FB pin rises with the same slope as the SS pin during the soft-start period.
After soft -start completion (SS>3.7V), it operates as follows.

When PWM=H, it detects ISENSE terminal voltage and outputs error signal compared to analog dimming signal (ADIM).

It detects over boost (FBMAX) over FB=4.0V(typ). After the SS completion, if FB>4.0V and PWM=H continues 4clk GATE,
the CP charge starts. After that, only the FB>4.0V is monitored, if CP charge continues to the CP=3.0V, IC will be latched
off. (Please refer to section “3.5.6 Timing Chart”.)

The loop compensation setting is described in section "3.4 Loop Compensation".

○Pin 11: ISENSE

This is the input terminal for the current detection. Error amplifier compares the
lower one among 1/3 of the voltage terminal ADIM analog dimming and 1.0V(typ).
And it detects abnormal LED overcurrent at ISENSE=3.0V(typ) over. If GATE
terminal continues during four CLKs (equivalent to 40μs at fosc = 100kHz), it
becomes latch-off. (Please refer to section “3.5.7 Timing Chart”.)

1.015V

1.0V

Gain=1/3

Error amp Vth[V]

67mV

0.2

0

3.0

3.3

ADIM[V]

Figure 13. Relationship of the feedback voltage and ADIM Figure 14. ISENSE terminal circuit example

○Pin 12: GND

This is the GND pin of the IC.

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○Pin 13: DIMOUT

This is the output pin for external dimming NMOS. The table below shows the rough output
logic of each operation state, and the output H level is VCC. Please refer to “3.5 Timing Chart”
for detailed explanations, because DIMOUT logic has an exceptional behavior. Please insert
the resistor R
PWM turns from low to high.

○Pin 14: GATE

This is the output terminal for driving the gate of the boost MOSFET. The high level is VCC. Frequency can be set by the
resistor connected to RT. Refer to <RT> pin description for the frequency setting.

○Pin 15: CS

The CS pin has two functions.

1. DC / DC current mode Feedback terminal
The inductor current is converted to the CS pin voltage by the sense resistor
R

This voltage compared to the voltage set by error amplifier controls the

CS.

output pulse.

2. Inductor current limit (OCP) terminal
The CS terminal also has an over current protection (OCP). If the voltage is
more than 0.4V(typ.), the switching operation will be stopped compulsorily. And

the next boost pulse will be restarted to normal frequency.
In addition, the CS voltage is more than 1.0V(typ.) during four GATE clocks, IC
will be latch off. As above OCP operation, if the current continues to flow
nevertheless GATE=L because of the destruction of the boost MOS, IC will
stops the operation completely.

Both of the above functions are enabled after 300ns (typ) when GATE pin
asserts high, because the Leading Edge Blanking function (LEB) is included
into this IC to prevent the effect of noise.
Please refer to section “3.3.1 OCP Setting / Calculation Method for the Current Rating of DCDC Parts”, for detailed
explanation.

If the capacitance Cs in the right figure is increased to a micro order, please be careful that the limited value of NMOS

drain current Id is more than the simple calculation. Because the current Id flows not only through Rcs but also through

Cs, as the CS pin voltage moves according to Id.

○Pin 16: VCC

This is the power supply pin of the IC. Input range is from 9V to 18V.

The operation starts at more than 7.5V(typ) and shuts down at less than 7.2V(typ)

between the dimming MOS gate to improve the over shoot of LED current, as

DIM

Status DIMOUT output

Normal Same logic to PWM

Abnormal GND Level

Figure 15. DIMOUT terminal circuit example

Figure 16. CS terminal circuit example

Datasheet

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●2.6 Detection Condition List of the Protect Functions (TYP Condition)

Protect Function

FBMAX FB FB > 4.0V H(4clk) SS>3.7V FB < 4.0V CP charge Latch off

LED OCP ISENSE ISENSE > 3.0V - - ISENSE < 3.0V 4clk Latch off

Detection

Pin

Detection

Condition

Detect Condition

PWM

SS

Release

Condition

Timer

Operation

Datasheet

Protection Type

RT GND SHORT RT RT<VRT×90% - -

UVLO UVLO UVLO<2.7V - - UVLO>3.0V NO Restart by release

REG50UVLO REG50 REG50<2.3V - - REG50>2.6V NO Restart by release

VCC UVLO VCC VCC<7.2V - - VCC>7.5V NO Restart by release

OVP OVP OVP>3.0V - - OVP<2.8V 4clk Latch off
OCP CS CS>0.4V - - - NO Pulse by Pulse

OCP LATCH CS CS>1.0V - - CS<1.0V 4clk Latch off

Release

RT=GND

NO Restart by release

To reset the latch type protection, please set STB logic to ‘L’ once. Otherwise the detection of VCCUVLO, REG50UVLO is
required.

The clock number of timer operation corresponds to the boost pulse clock.

●2.7 Behavior List of the Protect Function

Operation of the Protect Function

Protect Function

FBMAX

LED OCP

RT GND SHORT

STB

UVLO

REG50UVLO

VCC UVLO

OVP
OCP

OCP LATCH

DC/DC Gate

Stops after latch L after latch discharge after latch L after latch

Stops immediately H immediately, L after latch discharge after latch L after latch

Stops immediately immediately L Not discharge -

Stops immediately

Stops immediately immediately L discharge immediately H (2.0V)

Stops immediately immediately L discharge immediately H (2.0V)

Stops immediately immediately L discharge immediately H (2.0V)

Stops immediately immediately L discharge after latch L after latch

Stops immediately Normal operation Not discharge H (2.0V)

Stops after latch L after latch discharge after latch L after latch

Output

Dimming Transistor

(DIMOUT) Logic

L after REG50UVLO

detects

SS Pin

discharge immediately

RT pin

(FAILB logic)

L after REG50UVLO

detects

Please refer to section “3.5 Timing Chart” for details.

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