BD3823FV is a low-noise (3.2ҏμVrms), low distortion (0.0015%), 5ch selector, incorporating a resistor-ladder type
volume.
Because of a wide power supply voltage range (7V to 14.5V), BD3823FV can meet a wide input voltage (to 4.5 Vms), and high S/N
can be achieved. In addition, the built-in volume does not add any distortion ratio characteristics, even when the attenution is varied,
and is applicable for high-quality audio systems.
ƔFeatures
1) A resistor-ladder type volume circuit is with a low distortion ratio (0.0015% with volume set to –6dB) and low noise (3.2 ȝVrms with
volume set to -6dB).
2) By grouping sound input terminals with output terminals, the PCB layout is reduced.
3) Small package SSOP - B20 achieves good crosstalk characteristicss (-110 dB).
4) The use of Bi-CMOS process enables low current consumption and energy saving design.
Because of low current consumption, BD3823FV has the advantage in quality over the scaling down of the internal regulators and
heat controls.
ƔApplications
DVD recorders
ƔAbsolute maximum rating (T
Parameter Symbol Limits Unit
Applied Voltage
Input voltage VIN
Power Dissipation Pd 810
Operating Temperature Topr
Storage Temperature Tastg
*1 Reduced by 6.5 mW/qC at 25qC or higher.
Thermal resistance Tja = 154 (°C/W), when Rohm standard board is mounted.
Rohm standard board: Size: 70701.6 (mm
*2 As long as voltage stays within operating voltage range, certain circuit operation is guaranteed in
the operating temperature range.
Allowable power loss conditions are related to temperature, to which care must be taken.
In addition though the standard value of its electrical characteristics cannot be guaranteed under
the conditions other than those specified, basic functions are maintained.
ƔOperating range (Basic operation at Ta=25)
Parameter Symbol Min. Typ. Max. Unit
Power supply voltage
*3 As long as temperature and operating voltage meet specifications
In addition, though the standard value of its electrical characteristics cannot be guaranteed under
the conditions other than those specified, basic functions are maintained.
a=25°C)
VCC 15.0
SCL, SDA 7.0
VCC+0.3GND-0.3
3
)
Material: FR4 glass-epoxy substrate (copper foil area: not more than 3%).
*
3
VCC 7.0 12.0 14.5 V
*
1
mW
-40䌾+85
-55+150
*
2
V
V
°C
°C
Ver.B Oct.2005
!
ƔElectrical characteristics
Unless otherwise specified, Ta=25, VCC=12V, f=1kHz, Vin=1Vrms, Rg=600Ԉ, R
Input terminal = Front 1, Output terminal = Out 1
Limits
Parameter Symbol
Min.Typ.Max.
Circuit Current upon no signal IQ - 2.5 10 mA VIN=0Vrms
L=10kԈ, Gain selector = 0dB, Volume = 0dB,
Unit Conditions
Voltage gain GV -1.50 1.5 КB GV=20log(V
Maximum output voltage VOM 3.0 3.6 - Vrms
Channel balance CB -1.50 1.5 dB
Total harmonic distortion THD - 0.00150.05%
Output noise voltage * VNO - 3.2 16 ȝVrms
GENERAL
Residual output noise voltage * V
- 2 10 ȝVrms
NOR
Cross-talk between channels * CTC - -110-80 dB
VOM at THD(V
BW=400Hz-30KHz
CB = G
GV1:ch1Gain, GV2:ch2 Gain
VIN=2Vrms,Volume=-6dB
BW=400Hz-30KHz
Volume=-6dB
g = 0ȍ, BW=IHF-A
R
Volume = -dB
Rg = 0ȍ, BW=IHF-A
Rg = 0ȍ
BW = IHF-A
OUT/VIN
OUT
V1-GV2
Input impedance RIN 77 110143 kȍ 1pin-10pin terminal
Maximum input voltage VIM 3.1 3.6
1)
- Vrms
VIM at THD(V
BW=400Hz-30KHz
OUT
)=1%
1pin-10pin terminal
Rg = 0ȍ
Cross-talk between selectors * CTS - -110-80 dB
Volume control range VV -32.5-30.5-28.5dB
BW = IHF-A
CTS=20log(V
GV=20log(V
BW = IHF-A
OUT/VIN
OUT/VIN
Volume = -dB
Maximum attenuation * G
VOLUME
Step resolution G
- -106-85 dB
V MIN
V STEP
- 0.5 - dB Volume=0-30.5dB
GV=20log(V
BW = IHF-A
OUT/VIN
)
)=1%
)
)
)
Attenuation set error G
-1.50 1.5 dB Volume=0-30.5dB
V ERR
Gain Selector=6dB
Maximum gain G
Step resolution G
GAIN SELECTOR
Gain set error G
4.5 6 7.5 dB
MAX
=500mVrms
V
IN
G=20log(V
- 2 - dB From 2dB to 4dB
STEP
-1.50 1.5 dB
ERR
OUT/VIN
)
ͰVP-9690A (average value detection, effective value display) filter by Matsushita Communication is used for * measurement.
ͰPhase between input/output is the same.
ͰThis IC is not designed to be radiation-resistant.
1)V
V
=2.5Vrms(TYP) at VCC=9VTHD(V
IM
=4.2Vrms(TYP) at VCC=14VTHD(V
IN
OUT
)=1%
OUT
)=1%
2/8
ƔTiming chart
Electrical specifications and timing of bus lines and I/O stages
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Fig.1 Timing Definition on I
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2
C BUS
2
Table 1 . Characteristics of the SDA and SCL BUS lines for I
C BUS devices
Parameter Symbol
SCL clock frequency
1
Bus free time between a STOP and START condition
2
Hold time (repeated) START condition. After this period, the first clock
3
pulse is generated
LOW period of the SCL clock
4
HIGH period of the SCL clock
5
Set-up time for a repeated START condition
6
Data hold time
7
Data set-up time
8
Rise time of both SDA and SCL signals
9
Fall time of both SDA and SCL signals
10
Set-up time for STOP condition
11
Capacitive load for each bus line
12
The above numerical values all correspond to VIH min and VIL max levels (see Table 2).
*The input signals must internally provide at least 300 ns hold-time for SDA signals (at V
undefined region at the fall-end of SCL.
2
Table 2 . Characteristics of the SDA and SCL I/O stages for I
C BUS devices
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㪤㪙㪚㪍㪈㪈
㪧
High speed mode
I2C BUS
Min. Max.
fSCL 0 400 kHz
tBUF 1.3 - ȝs
tHD;STA0.6 - ȝs
tLOW 1.3 - ȝs
tHIGH 0.6 - ȝs
tSU;STA0.6 - ȝs
tHD;DAT0* - ȝs
tSU; DAT100 - ns
tR 20+Cb 300 ns
tF 20+Cb 300 ns
tSU;STO0.6 - ȝs
Cb - 400 pF
IH min of SCL signals) in order to cross over
Unit
High speed mode
Parameter
Symbol
I2C BUS
Min. Max.
Low-level input voltage : fixed input levels
13
Low-level input voltage : fixed input levels
14
Hysteresis of Schmitt trigger inputs: fixed input levels
15
VIL -0.5 1.0 V
VIH 2.3 - ȝs
Vhys n/a n/a V
16 Pulse width of spikes which must be suppressed by the input filter. tSP 0 50 ns
17 Low-level output voltage (open drain): at 3mA sink current VOL1 0 0.4 V
Output fall time from VIHmin. to VIHmax. with a bus capacitance from 10
18
pF to 400pF: with up to 3mA sink current at VOL1
Input current each I/O pin with an input voltage between 0.4V and 0.9
19
VCCmax.
tOF 20+0.1Cb 250 ns
Ii -10 10 ȝA
20 Capacitance for each I/O pin Ci - 10 pF
n/a = not applicable
3/8
Unit
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