ROHM BD3550HFN Technical data

TECHNICAL NOTE

High-performance Regulator IC Series for PCs

Ultra Low Dropout
Linear Regulators for PC

BD3550HFN, BD3551HFN, BD3552HFN (0.5～2.0A)

● Description
BD3550HFN,BD3551HFN,BD3552HFN ultra low-dropout linear chipset regulator operates from a very low input supply, and
offers ideal performance in low input voltage to low output voltage applications. It incor porates a bui lt-in N-MOSFET power
transistor to minimize the input-to-output voltage differential to the ON resistance (R
lowering the dropout voltage in this way, the regulator realizes high current output (Iomax=2.0A <BD3552HFN>) with
reduced conversion loss, and thereby obviates the switching regulator and its power transistor, choke coil, and rectifier
diode. Thus, BD3550HFN,BD3551HFN,BD3552HFN is designed to ena ble significant package profile d ownsizing and cost
reduction. An external resistor allows the entire range of output voltage configurations bet ween 0.65 and 2.7V, while the
NRCS (soft start) function enables a controlled output voltage ramp-up, which can be programmed to whatever power
supply sequence is required.

● Features

1) Internal high-precision reference voltage circuit(0.65V±1%)

2) Built-in VCC undervoltage lockout circuit

3) NRCS (soft start) function reduces the magnitude of in-rush current

4) Internal Nch MOSFET driver offers low ON resistance (100mΩ <BD3552HFN typ>)

5) Built-in current limit circuit

6) Built-in thermal shutdown (TSD) circuit

7) Variable output (0.65～2.7V)

8) Small package HSON8 : 2.9×3×0.6(mm)

9) Tracking function

● Applications
Notebook computers, Desktop computers, LCD-TV, DVD, Digital appliances

● Line-up

It is available to select power supply voltage and maximum output voltage.

Maximum Output Voltage Package Vcc=5V

0.5A

1.0A BD3551HFN

2.0A BD3552HFN

HSON8

BD3550HFN

ON=100mΩ <BD3552HFN>) level. By

Oct. 2008

●Absolute maximum ratings

◎BD3550HFN,BD3551HFN,BD3552HFN

Parameter Symbol

BD3550HFN BD3551HFN BD3552HFN

Limit

Unit

Input Voltage 1 VCC +6.0 *1 V
Input Voltage 2 VIN +6.0 *1 V
Enable Input Voltage Ven -0.3～+6.0 V
Power Dissipation 1 Pd1 0.63 *2 W
Power Dissipation 2 Pd2 1.35 *3 W

Power Dissipation 3 Pd3 1.75 *4 W
Operating Temperature Range Topr -10～+100 ℃
Storage Temperature Range Tstg -55～+150 ℃
Maximum Junction Temperature Tjmax +150 ℃

*1 Should not exceed Pd.
*2 Reduced by 5.04mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 1-layer)
On less than 0.2% (percentage occupied by copper foil.
*3 Reduced by 10.8mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 1-layer)
On less than 7.0% (percentage occupied by copper foil.
*4 Reduced by 14.0mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 1-layer)

On less than 65.0% (percentage occupied by copper foil.

2/16

◎BD3550HFN,BD3551HFN,BD3552HFN

●Operating Voltage(Ta=25℃)

Parameter Symbol Min. Max. Unit
Input Voltage 1 VCC 4.3 5.5 V
Input Voltage 2 VIN 0.95 VCC-1 *5 V
Output Voltage Setting Range Vo VFB 2.7 V
Enable Input Voltage Ven 0 5.5 V
NRCS Capacity CNRCS 0.001 1 μF

*5 VCC and VIN do not have to be implemented in the order listed.

★This product is not designed for use in radioactive environments.

●Electrical Characteristics (Unless otherwise specified, Ta=25℃, VCC=5V, Ven=3V, VIN=1.8V, R1=3.9KΩ, R2=3.3KΩ)

Parameter Symbol

Bias Current ICC - 0.5 1.0 mA
VCC Shutdown Mode Current IST - 0 10 uA Ven=0V
Output Voltage VOUT - 1.200 - V
Output Voltage Temperature
Coefficient

Tcvo - 0.01 - %/℃

Feedback Voltage 1 VFB1 0.643 0.650 0.657 V
Feedback Voltage 2 VFB2 0.637 0.650 0.663 V Tj=-10 to 100℃

Load Regulation Reg.L - 0.5 10 mV
Line Regulation 1 Reg.l1 - 0.1 0.5 %/V VCC=4.3V to 5.5V

Line Regulation 2 Reg.l2 - 0.1 0.5 %/V VIN=1.2V to 3.3V

Standby Discharge Current Iden 1 - - mA Ven=0V, Vo=1V
[ENABLE]
Enable Pin
Input Voltage High
Enable Pin
Input Voltage Low

Enhi 2 - - V

Enlow 0 - 0.8 V

Enable Input Bias Current Ien - 7 10 μA Ven=3V
[FEEDBACK]
Feedback Pin Bias Current IFB -100 0 100 nA
[NRCS]
NRCS Charge Current Inrcs 14 20 26 μA Vnrcs=0.5V
NRCS Standby Voltage VSTB - 0 50 mV Ven=0V
[UVLO]
VCC Undervoltage Lockout
Threshold Voltage
VCC Undervoltage Lockout
Hysteresis Voltage

VccUVLO 3.5 3.8 4.1 V Vcc:Sweep-up

Vcchys 100 160 220 mV Vcc:Sweep-down

[AMP]
Gate Source Current I
Gate Sink Current I

Maximum output
current

Minimum dropout
voltage

BD3550HFN Io 0.5 - - A
BD3551HFN Io 1.0 - - A
BD3552HFN Io 2.0 - - A
BD3550HFN dVo - 200 300 mV Io=0.5A, VIN=1.2V, Ta=-10 to 100℃
BD3551HFN dvo - 200 300 mV Io=1.0A, VIN=1.2V, Ta=-10 to 100℃
BD3552HFN dVo - 200 300 mV Io=2.0A, VIN=1.2V, Ta=-10 to 100℃

- 1.6 - mA VFB=0, V

GSO

- 4.7 - mA VFB=VCC, V

GSI

Limit

Min. Typ. Max.

Unit Condition

Io=0 to 1A
(BD3550HFN Io=0A to 0.5A)

=2.5V

GATE

=2.5V

GATE

3/16

●Reference Data(BD3550HFN)

μ

v

v

v

v

v

v

v

v

μ

v

v

v

v

v

v

50mV/di

Vo

26mV

Vo

50mV/di

22mV

0.5A/di

Io

0.5A

0.5A/di

Io

0.5A

Io=0A→1A/μsec t(10μsec/div)

Fig.1 Transient Response

(0→0.5A)

Co=100μF, Cfb=1000pF

Io=0A→1A/μsec t(10μsec/div) Io=0A→1A/μsec t(10μsec/div)

Fig.2 Transient Response

(0→0.5A)

Co=47μF, Cfb=1000pF

50mV/di

Vo

14mV

50mV/div

Vo

23mV

Io

0.5A/di

0.5A

Io=1A→0A/μsec t(100μsec/div)

Fig.4 Transient Response

(0.5→0A)

Co=100

F, Cfb=1000pF

0.5A/div

Io

0.5A

Io=1A→0A/μsec t(100μsec/div)

Fig.5 Transient Response

(0.5→0A)

Co=47μF, Cfb=1000pF

50mV/di

0.5A/di

50mV/div

0.5A/div

Vo

40mV

Io

0.5A

Fig.3 Transient Response

(0→0.5A)

Co=22μF, Cfb=1000pF

Vo

33mV

Io

0.5A

Io=1A→0A/μsec t(100μsec/div)

Fig.6 Transient Response

(0.5→0A)

Co=22μF, Cfb=1000pF

●Reference Data(BD3551HFN)

Vo

50mV/di

35mV

Io

1.0A/di

Vo

50mV/div

1.0A

Io=0A→1A/μsec t(10μsec/div)

Fig.7 Transient Response

(0→1.0A)

Co=100μF, Cfb=1000pF

36mV

Fig.7 Transient Response (1.0→

0A)

F, Cfb=1000pF

1.0A/div

Io

1.0A

Co=100

Vo

50mV/div

46mV

Io

1.0A/div

1.0A

Io=0A→1A/μsec t(10μsec/div) Io=0A→1A/μsec t(10μsec/div)

Fig.8 Transient Response

(0→1.0A)

Co=47μF, Cfb=1000pF

Vo

50mV/div

46mV

Io=0A→1A/μsec t(10μsec/div)

Fig.8 Transient Response (0→

1.0A)

1.0A/div

Io

1.0A

Vo

50mV/di

55mV

Io

1.0A/di

1.0A

Fig.9 Transient Response

(0→1.0A)

50mV/di

Co=22μF, Cfb=1000pF

Vo

56mV

Io=0A→1A/μsec t(10μsec/div)

Fig.9 Transient Response (0→

1.0A)

1.0A/di

Io

1.0A

Io=1A→0A/μsec t(100μsec/div)

Fig.10 Transient Response

(1.0→0A)

Co=100μF, Cfb=1000pF

Io=1A→0A/μsec t(100μsec/div)

Fig.11 Transient Response

(1.0→0A)

Co=47μF, Cfb=1000pF

Io=1A→0A/μsec t(100μsec/div)

Fig.12 Transient Response

(1.0→0A)

Co=22μF, Cfb=1000pF

4/16

●Reference Data(BD3552HFN)

v

v

v

v

v

v

v

v

v

μ

v

v

v

v

v

v

v

Vo

50mV/di

2.0A/di

50mV/di

2.0A/di

26mV

Io

Io=0A→1A/μsec t(10μsec/div)

2.0A

Fig.13 Transient Response

(0→2.0A)

Co=100μF, Cfb=1000pF

Vo

54mV

Io

2.0A

Io=1A→0A/μsec t(100μsec/div)

Fig.16 Transient Response

(2.0→0A)

Co=100

F, Cfb=1000pF

●Reference Data(BD3551HFN)

Ven

2V/di

VNRCS

2V/di

Vo

1V/di

Fig.19 Waveform at output

t(200μsec/div)

start

VCC

Ven

VIN

Vo

VIN→VCC→Ven

Fig.22 Input sequence

Vo

50mV/di

89mV

Io

2.0A/di

Io=0A→1A/μsec t(10μsec/div)

2.0A

Fig.14 Transient Response

(0→2.0A)

Vo

50mV/di

2.0A/di

Co=47μF, Cfb=1000pF

83mV

Io

2.0A

Io=1A→0A/μsec t(100μsec/div)

Fig.17 Transient Response

(2.0→0A)

Co=47μF, Cfb=1000pF

Ven

2V/di

VNRCS

2V/div

Vo

1V/di

t(2msec/div)

Fig.20 Waveform at output OFF

VCC

Ven

VIN

Vo

Ven→VCC→VIN

Fig.23 Input sequence

50mV/di

2.0A/di

50mV/di

2.0A/div

VCC

Vo

117mV

Io

Io=0A→1A/μsec t(10μsec/div)

2.0A

Fig.15 Transient Response

(0→2.0A)

Co=22μF, Cfb=1000pF

Vo

117mV

Io

2.0A

Io=1A→0A/μsec t(100μsec/div)

Fig.18 Transient Response

(2.0→0A)

Co=22μF, Cfb=1000pF

VCC

Ven

VIN

Vo

Fig.21 Input sequence

Ven

VIN

Vo

VCC→Ven→VIN

Fig.24 Input sequence

VCC→VIN→Ven

5/16

●Reference Data(BD3551HFN)

1.25

VCC

Ven

VIN

Vo

Fig.25 Input sequence

0.80

0.75

0.70

0.65

0.60

0.55

ICC(mA)

0.50

0.45

0.40

0.35

0.30

-10 10 30 50 70 90
Ta(℃)

VCC

Ven

VIN

Vo

VIN→Ven→VCC Ven→VIN→VCC

Fig.26 Input sequence

1.2

1.0

0.8

0.6

ICC(uA)

0.4

0.2

100

0.0

-60 -30 0 30 60 90 120 150
Ta(℃)

1.23

1.21

Vo(V)

1.19

1.17

1.15

-101030507090
Ta(℃)

Fig.27 Ta-Vo (Io=0mA)

2.0

1.9

1.8

1.7

1.6

1.5

IIN(mA)

1.4

1.3

1.2

1.1

1.0

-101030507090

Ta(℃)

100

100

Fig.28 Ta-ICC

30

25

20

15

IIN(uA)

10

5

0

-60 -30 0 30 60 90 120 150
Ta(℃)

Fig.31 Ta-IINSTB

10

9
8
7
6
5

Ien(uA)

4
3
2
1
0

-101030507090
Ta(℃)

100

Fig.29 Ta-ISTB

25
24
23
22
21
20
19

INRCS(uA)

18
17
16
15

-101030507090
Ta(℃)

Fig.32 Ta-INRCS

150

140

130

)

Ω

120

RON(m

110

100

90

-10 10 30 50 70 90
Ta(℃)

Fig.30 Ta-IIN

20
15
10

5
0

IFB(nA)

-5

-10

-15

100 100

-20

-10 10 30 50 70 90
Ta(℃)

Fig.33 Ta-IFB

150

140

130

)

Ω

120

RON(m

110

100

90

100

2468

Vcc(V)

Fig.34 Ta-Ien

Fig.35 Ta-RON

(VCC=5V/Vo=1.2V)

6/16

Fig.36 VCC-RON

●Block Diagram

432

4

●Pin Layout

PIN No. PIN name PIN Function

1 VCC Power supply pin
2 EN Enable input pin
3 GATE Gate pin
4 VIN Input voltage pin
5 VO Output voltage pin
6 FB Reference voltage feedback pin
7 NRCS In-rush current protection (NRCS) capacitor connection pin
8 GND Ground pin

reverse FIN Connected to heatsink and GND

●Pin Function Table
◎HSON8

7

±

±

1PIN MARK

0.6Max.

±

B D 3

5 5 X

VCC

VCC

Reference

Block

Thermal

Shutdown

TSD

Lot No.

VCC

NRCS

UVLO

CL
UVLO
TSD

VCC

CLEN

Current

Limit

EN

GNDNRCS

VIN

VO

FB

GATE

VIN

Vo

.

.

+0.1

0.13

−0.05

.

2

±

(Unit : mm)

7/16

●Operation of Each Block

・AMP

This is an error amp that compares the reference voltage (0.65V) with Vo to drive the output Nch FET (Ron=100m
Ω:BD3552HFN). Frequency optimization helps to realize rapid transient response, and to support the use of ceramic
capacitors on the output. AMP input voltage ranges from GND to 2.7V, while the AMP output ranges from GND to VCC.
When EN is OFF, or when UVLO is active, output goes LOW and the output of the NchFET switches OFF.

・EN

The EN block controls the regulator’s ON/OFF state via the EN logic input pin. In the OFF position, circuit voltage is
maintained at 0μA, thus minimizing current consumption at standby. The FET is switched ON to enable discharge of the
NRCS pin Vo, thereby draining the excess charge and preventing the IC on the load side from malfunctioning. Since no
electrical connection is required (e.g., between the VCC pin and the ESD prevention Diode), module operation is
independent of the input sequence.

・UVLO

To prevent malfunctions that can occur during a momentary decrease in VCC, the UVLO circuit switches the output OFF,
and (like the EN block) discharges NRCS and Vo. Once the UVLO threshold voltage (TYP3.80V) is reached, the power-on
reset is triggered and output continues.

・CURRENT LIMIT

When output is ON, the current limit function monitors the internal IC output current against the parameter value (2.0A or
more:BD3552HFN). When current exceeds this level, the current limit module lowers the output current to protect the loa d
IC. When the overcurrent state is eliminated, output voltage is restored to the parameter value.

・NRCS (Non Rush Current on Start-up)

The soft start function enabled by connecting an external capacitor between the NRCS pin and ground. Output ramp-up
can be set for any period up to the time the NRCS pin reaches VFB (0.65V). Durin g startup, the NRCS pin serves as a 20
μA (TYP) constant current source to charge the external capacitor. Output start time is calculated via formula (1) below.

Tracking sequence is available by connecting the output voltage of external power supply instead of external capacitor. And
then, ratio-metric sequence is also available by changing the resistor division rati o of e xternal p ower supply output voltage.
(See the next page)

・TSD (Thermal Shut down)

The shutdown (TSD) circuit automatically switches output OFF when the chip temperature gets too high, thus serving to
protect the IC against “thermal runaway” and heat damage. Because the TSD circuit is provided to shut down the IC in the
presence of extreme heat, in order to avoid potential problems with the TSD, it is crucial that the Tj (max) parameter not be
exceeded in the thermal design.

・VIN

The VIN line acts as the major current supply line, and is connected to the output NchFET drain. Since no electrical

connection (such as between the VCC pin and the ESD protection Diode) is necessary, VIN operates independent of the
input sequence. However, since an output NchFET body Diode exists between VIN and Vo, a VIN-Vo electric (Diode)
connection is present. Note, therefore, that when output is switched ON or OFF, reverse current may flow to VIN from Vo.

0.65V

t = C ・・・(1)

20μA

8/16

●Timing Chart

EN ON/OFF

VIN

VCC

EN

NRCS

Vo

VCC ON/OFF

VIN

VCC

EN

NRCS

Vo

Tracking sequence

Ratio-metric sequence

1.8V Output

1.2V Output

(R

=3.9kΩ, R2=3.3kΩ)

1

Tracking sequence

1.8V

1.2V

0.65V(typ)

UVLO

0.65V(typ)

Startup

Startup

DC/DC

Vo

1.8V

R2

R

1

Hysteresis

t

t

NRCS

V0

FB

1.2V

3.3kΩ

3.9kΩ

9/16

●Evaluation Board

BD3550HFN,BD3551HFN,BD3552HFN Evaluation Board Schematic

■■

VCC

GND

C11

SW1

GND

VIN

R8

C12

GND

GND

R4

VCC

GND

EN

VIN_S

C7 C4

GATE

GND

C3

GND

GND

VCC

C1

C2

1

2

3

4

U1
BD355XHFN
(HSON8)

GND

8

GND

7

6

R1

R2

5

GND

GND

GND

GND

C13

C5

GND_S

GND

GND

FB

C6

GND

2

C10

GND

3

5

Vo_S

C8

TP2

4

NRCS

GND

JPF2

R3

C9

VCC

U3

GND

U2

GND

R5

7 5 6 8

2 1

3

4

GND

Vo

R6

TP1

R7

JPF1

C14

R9

BD3550HFN,BD3551HFN,BD3552HFN Evaluation Board Standard Component List

■■

Component Rating Manufacturer Product Name Component Rating Manufacturer Product Name

U1 - ROHM BD355XHFN C2 22uF KYOCERA CM32X5R226M10A
C1 1uF MURATA GRM188B11A105KD C13 1000pF MURATA GRM188B11H102KD
C10 0.01uF MURATA GRM188B11H103KD R1 3.9kΩ ROHM MCR03EZPF3301
R8 0Ω - Jumper R2 3.3kΩ ROHM MCR03EZPF3901
C5 22uF KYOCERA CM32X5R226M10A

BD3550HFN,BD3551HFN,BD3552HFN Evaluation Board Layout

■■

(2nd layer and 3rd layer is GND Line.)

TOP Layer

Bottom Layer Silkscreen

10/16

●Recommended Circuit Example

1

8

VCC

EN

R4

C1

2

3

7

6

4

VIN

C2

R2

5

R1

GND

C4

FB

C5

VOUT1(1.2V)

C3

Component

Recommended
Value

Programming Notes and Precautions

R1/R2 3.9k/3.3k IC output voltage can be set with a configuration formula using the values for the internal

reference output voltage (V
values that will avoid the impact of the VREF

)and the output voltage resistors (R1, R2). Select resistance

FB

current (±100nA). T he recommended total

resistance value is 10KΩ.

C3 22μF To assure output voltage stability, please be certain the Vo1, Vo2, and Vo3 pins and the

GND pins are connected. Output capacitors play a role in loop gain phas e compensation
and in mitigating output fluctuation during rapid changes in load level. Insufficient
capacitance may cause oscillation, while high equivalent series reisistance (ESR) will
exacerbate output voltage fluctuation under rapid load change conditions. W hile a 22μF
ceramic capacitor is recomended, actual stability is highly dependent on temperature and
load conditions. Also, note that connecting different types of capacitors in series may result
in insufficient total phase compensation, thus causing oscillation. In light of this information,
please confirm operation across a variety of temperature and load conditions.

C1 1μF Input capacitors reduce the output impedance of the voltage supply source connected to

the (VCC) input pins. If the impedance of this power supply were to increase, input voltage
(VCC) could become unstable, leading to oscillation or lowered ripple rejection function.
While a low-ESR 1 μ F capacitor with minimal susceptibility to temperature is
recommended, stability is highly dependent on the input power supply characteristics and
the substrate wiring pattern. In light of this information, please confirm operation across a
variety of temperature and load conditions.

C2 22μF Input capacitors reduce the output impedance of the voltage supply source connected to

the (VIN) input pins. If the impedance of this power supply were to increase, input voltage
(VIN) could become unstable, leading to oscillation or lowered ripple rejection function.
While a low-ESR 22 μ F capacitor with minimal susceptibility to temperature is
recommended, stability is highly dependent on the input power supply characteristics and
the substrate wiring pattern. In light of this information, please confirm operation across a
variety of temperature and load conditions.

C4 0.01μF The Non Rush Current on Startup (NRCS) function is built into the IC to prevent rush

current from going through the load (VIN to VO) and impacting output capacitors at power
supply start-up. Constant current comes from the NRCS pin when EN is HIGH or the
UVLO function is deactivated. The temporary reference voltage is proportionate to time,
due to the current charge of the NRCS pin capacitor, and output voltage start-up is
proportionate to this reference voltage. Capacitors with low susceptibility to temperature
are recommended, in order to assure a stable soft-start time.

C5

R4

- This compone nt is employed when the C3 capacitor causes, or may cause, oscillation. It
provides more precise internal phase correction.

Several kΩ
～several 10kΩ

It is recommended that a resistance (several kΩ to several 10kΩ) be put in R4, in case
negative voltage is applied in EN pin.

11/16

●Heat Loss

Thermal design should allow operation within the following conditio ns. Note that the temperatures listed are the allowed
temperature limits, and thermal design should allow sufficient margin from the limits.

1. Ambient temperature T a can be no higher than 100℃.

2. Chip junction temperature (Tj) can be no higher than 150℃.

Chip junction temperature can be determined as follows:

① Calculation based on ambient temperature (Ta)

Tj=Ta+θj-a×W

＜Reference values＞

1-layer substrate (copper foil density 0.2%)
1-layer substrate (copper foil density 7%)

92.4℃/W
2-layer substrate (copper foil density 65%)

71.4℃/W
Substrate size: 70×70×1.6mm

θj-a:HSON8 198.4℃/W

3

(substrate with thermal via)

It is recommended to layout the VIA for heat radiation in the GND pattern of reverse (of IC) when there is the GND pattern in
the inner layer (in using multiplayer substrat e). This package is so small (size: 2.9mm×3.0mm) that it is not available to
layout the VIA in the bottom of IC. Spreading the pattern and being increased the number of VIA like the figure below).
enable to get the superior heat radiation characteristic. (This figure is the image. It is recommended that the VIA size and
the number is designed suitable for the actual situation.).

Most of the heat loss that occurs in BD3550HFN,BD3551HFN,BD3552HFN is generated from the output Nch FET. Power
loss is determined by the total V

IN-Vo voltage and output current. Be sure to confirm the system input and output voltage

and the output current conditions in relation to the heat dissipation characteristics of the VIN and Vo in the design. Bearing in
mind that heat dissipation may vary substantially depending on the substrate employed (due to the power package
incorporated in BD3550HFN,BD3551HFN,BD3552HFN) make certain to factor conditions such as substrate size into the
thermal design.

Power consumption (W) = Input voltage (VIN)- Output voltage (Vo) (Vo≒VREF) ×Io(Ave)

Example) Where VIN=1.8V, VO=1.2V, Io(Ave) = 1A,

Power consumption (W) = 1.8(V)-1.2(V) ×1.0(A)

= 0.6(W)

12/16

●Input-Output Equivalent Circuit Diagram

VCC

VCC

NRCS

1kΩ

1kΩ

10kΩ

VCC

VO1

VO2

50kΩ

●Reference landing pattern

Lead pitch

0.65 2.50 0.40 0.35

central pad length

2.90 1.90

*It is recommended to design suitable for the actual application.

1kΩ

1kΩ

EN

10kΩ

b2

L2

D3

1kΩ

VIN

10kΩ

VCC

VFB

100kΩ

100kΩ

20pF

MIE

E3

1kΩ

1kΩ

1kΩ

1kΩ

e

(Unit:mm)

Lead pitch

e

MIE

landing length

≧l2

landing pitch

b2

central pad pitch

D3 E3

350kΩ

13/16

●Operation Notes

1. Absolute maximum ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc ., can
break down the devices, thus making impossible to identify break ing mode, such as a s hort circuit or an open circuit. If any
over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protectio n devices, such as
fuses.

2. Connecting the power supply connector backward
Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply
lines. An external direction diode can be added.

3. Power supply lines
Please add a protection diode when a large inductance com pon ent is conn ected to the output te rminal, a nd rev erse-polarity
power is possible at startup or in output OFF condition.

4. GND voltage
The potential of GND pin must be minimum potential in all operating conditions.

5. Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.

6. Inter-pin shorts and mounting errors
Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any
connection error or if pins are shorted together.

7. Actions in strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to
malfunction.

8. ASO
When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO.

9. Thermal shutdown circuit
The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed
only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or guarantee its operation. Do not
continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is
assumed.

TSD on temperature [°C]

BD3550HFN,BD3551HFN,BD3552HFN 175 15

10. Testing on application boards

When testing the IC on an application board, connecting a capacitor to a pin with low impedanc e subjects the IC to stress.
Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or
removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure.
Use similar precaution when transporting or storing the IC.

(Example)

OUTPUT PIN

Hysteresis temperature [°C]

(typ.)

(typ.)

14/16

P

iti

P

iti

11. Regarding input pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode
or transistor. For example, the relation between each potential is as follows:

When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.

When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes operate,
such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used.

Pin A

Parasitic element

N

+

P

P

P

GND

Resistor Transistor (NPN)

B

C

E

N

P

P substrate

GND

+

N N

P substrate

Pin A

aras

element

Pin B

N

+

c

P

Parasitic element

Pin B

B C

+

P

N

GND

Other adjacent elements

E

GND

aras

element

12. Ground Wiring Pattern.
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing
a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations
caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring
pattern of any external components, either.

●Heat Dissipation Characteristics

◎HSON8

[W]

2.0

(3) 1.75W

1.5
(2) 1.35W

1.0

(1) 0.63W

Power Dissipation [Pd]

0.5

0

0 25 75 100 125 150 50

Ambient Temperature [Ta ]

(1) Substrate (copper foil density: 0.2%…1-layer)

θj-a=198.4℃/W

(2) Substrate (copper foil density: 7%…1-layer)

θj-a=92.4℃/W

(3) Substrate (copper foil density: 65%…1-layer)

θj-a=71.4℃/W

[℃]

c

15/16

●Type Designations (Ordering Information)

p

B D 3 5 5 X

Product Name

・BD355X

Package Type

・HFN : HSON8

HSON8

<Dimension>

0.475

0.2

±

3.00

2.90±0.2

0.2

±

2.80

0.6Max.

0.65

5678

4321

0.32±0.10

(0.2) (1.8) (0.2)

(0.05)(2.2)

8765

(0.30)

(0.15)

(0.45)

1234

0.13

(Unit:mm)

+0.1

−0.05

F N

TR Emboss tape reel opposite draw-out side: 1 pin

<Tape and Reel information>

Tape
Quantity
Direction

of feed

Embossed carrier tape

cs

3000
TR

(The direction is the 1pin of product is at the upper light when you hold
reel on the left hand and you pull out the tape on the right hand)

XX
X
X X

X

X

Reel

XX

X

X

X X

X

※When you order , please order in times the amount of package quantity.

1Pin

X

X X

-

T R H

XX

X

X

X X

X
X X

X

X

X X

X
X X

X

X

Direction of feed

16/16

Catalog No.08T416A '08.10 ROHM ©

Appendix

No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM
CO.,LTD.

The content specified herein is subject to change for improvement without notice.

The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you
wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM
upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account when
designing circuits for mass production.

Great care was taken in ensuring the accuracy of the information specified in this document. However, should
you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no respon­sibility for such damage.

The technical information specified herein is intended only to show the typical functions of and examples of
application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or
exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility
whatsoever for any dispute arising from the use of such technical information.

The Products specified in this document are intended to be used with general-use electronic equipment or
devices (such as audio visual equipment, office-automation equipment, communication devices, electronic
appliances and amusement devices).

The Products are not designed to be radiation tolerant.

While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or
malfunction for a variety of reasons.

Please be sure to implement in your equipment using the Products safety measures to guard against the
possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as
derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your
use of any Product outside of the prescribed scope or not in accordance with the instruction manual.

The Products are not designed or manufactured to be used with any equipment, device or system
which requires an extremely high level of reliability the failure or malfunction of which may result in a direct
threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment,
aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no
responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended
to be used for any such special purpose, please contact a ROHM sales representative before purchasing.

If you intend to export or ship overseas any Product or technology specified herein that may be controlled under
the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.

Notes

Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact your nearest sales office.

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Appendix1-Rev3.0