ROHM BD3538F Technical data

High Performance Regulators for PCs

Termination Regulators for DDR-SDRAMs

BD3538F,BD3538HFN

No.10030EAT33

Description

BD3538F/HFN is a termination regulator compatible with JEDEC DDR-SDRAM, which functions as a linear power supply incorporating an N-channel MOSFET and provides a sink/source current capability up to 1A respectively. A built-in high-speed OP-AMP specially designed offers an excellent transient response. Requires 3.3 volts or 5.0 volts as a bias power supply to drive the N-channel MOSFET. Has an independent reference voltage input pin (VDDQ) and an independent feedback pin (VTTS) to maintain the accuracy in voltage required by JEDEC, and offers an excellent output voltage accuracy and load regulation. Also has a reference power supply output pin (VREF) for DDR-SDRAM or a memory controller. When EN pin turns to “Low”, VTT output becomes “Hi-Z” while VREF output is kept unchanged, compatible with “Self Refresh” state of DDR-SDRAM.

Features

1) Incorporates a push-pull power supply for termination (VTT)

2) Incorporates a reference voltage circuit (VREF)

3) Incorporates an enabler

4) Incorporates an undervoltage lockout (UVLO)

5) Employs SOP8 package

6) Employs HSON8 package

7) Incorporates a thermal shutdown protector (TSD)

8) Operates with input voltage from 2.7 to 5.5 volts

9) Compatible with Dual Channel (DDR-II)

Use

Power supply for DDR I / II / III - SDRAM

●Absolute Maximum Ratings

Parameter Symbol

BD3538F BD3538HFN

Input Voltage VCC 7

Enable Input Voltage VEN 7

Termination Input Voltage VTT_IN 7

VDDQ Reference Voltage VDDQ 7

Ratings

*1*2

Unit

Output Current ITT 1 1 A

Power Dissipation1 Pd1 560 *3 630

Power Dissipation2 Pd2 690 *4 1350

Power Dissipation3 Pd3 - 1750 *7 mW Operating Temperature Range Tstg -40～+105 -40～+105 ℃ Storage Temperature Range Tjmax -55～+150 -55～+150 ℃ Maximum Junction Temperature Tjmax +150 +150 ℃

*1 Should not exceed Pd. *2 Instantaneous surge voltage, back electromotive force and voltage under less than 10% duty cycle. *3 Reduced by 4.48mW for each increase in Ta of 1℃ over 25℃(With no heat sink). *4 Reduced by 5.52mW for each increase in Ta of 1℃ over 25℃(When mounted on a board 70mm×70mm×1.6mm Glass-epoxyPCB). *5 Reduced by 5.04mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 1-layer) On less than 0.2% (percentage occupied by copper foil. *6 Reduced by 10.8mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 1-layer) On less than 7.0% (percentage occupied by copper foil. *7 Reduced by 14.0mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 1-layer) On less than 65.0% (percentage occupied by copper foil.

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Technical Note

●Operating Conditions (Ta=25℃)

Parameter Symbol

Min Max

Ratings

Unit

Input Voltage VCC 2.7 5.5 V

Termination Input Voltage VTT_IN 1.0 5.5 V

VDDQ Reference Voltage VDDQ 1.0 2.75 V

Enable Input Voltage VEN -0.3 5.5 V

★ No radiation-resistant design is adopted for the present product.

●Electrical Characteristics (unless otherwise noted, Ta=25℃ VCC=3.3V VEN=3V VDDQ=1.8V VTT_IN=1.8V)

Parameter Symbol

Standby Current IST

Bias Current ICC

Limits

Min Typ Max

- 0.5 1.0

- 2 4

Unit

VEN=0V

VEN=3V

Condition

[Enable]

High Level Enable Input Voltage VENHIGH

Low Level Enable Input Voltage VENLOW

Enable Pin Input Current IEN

2.3 - 5.5 V

-0.3 - 0.8 V

- 7 10

µA

VEN=3V

[Termination]

Termination Output Voltage 1 VTT1

VREF-30m VREF VREF+30m

ITT=-1.0A to 1.0A

Ta =0 ℃ to 105℃ VCC=5V, VDDQ=2.5V

Termination Output Voltage 2 VTT2

VREF-30m VREF VREF+30m

VTT_IN=2.5V

ITT=-1.0A to 1.0A Ta =0 ℃ to 105℃

Source Current ITT+

Sink Current ITTLoad Regulation ⊿VTT

Line Regulation Reg.l

Upper Side ON Resistance 1 HRON1

Lower Side ON Resistance 1 LRON1

Upper Side ON Resistance 2 HRON2

Lower Side ON Resistance 2 LRON2

1.0 - - A

- - -1.0 A

- - 50

- 20 40

- 0.45 0.9 

- 0.4 0.8



ITT=-1.0A to 1.0A

VCC=5V, VDDQ=2.5V VTT_IN=2.5V

[Reference Voltage Input]

Input Impedance ZVDDQ

Output Voltage 1 VREF1

Output Voltage 2 VREF2

70 100 130

1/2×VDDQ

-18m

1/2×VDDQ

-40m

1/2×VDDQ

+18m

1/2×VDDQ

+40m

k

IREF=-5mA to 5mA

Ta =0 ℃ to 105℃ IREF=-10mA to 10mA

Ta =0 ℃ to 105℃ VCC=5V, VDDQ=2.5V

Output Voltage 3 VREF3

1/2×VDDQ

-25m

1/2×VDDQ

+25m

VTT_IN=2.5V

IREF=-5mA to 5mA Ta =0 ℃ to 105℃ VCC=5V, VDDQ=2.5V

Output Voltage 4 VREF4

1/2×VDDQ

-40m

1/2×VDDQ

+40m

VTT_IN=2.5V

ITT=-10mA to 10mA Ta =0 ℃ to 105℃

[UVLO]

Threshold Voltage VUVLO Hysteresis Voltage ⊿VUVLO

*6 Design Guarantee

2.40 2.55 2.70 V VCC : sweep up

100 160 220

VCC : sweep down

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Technical Note

●Reference Data

VTT(20mV/Div)

ITT(1A/Div)

Fig.1 DDR1 (-1A→1A) Fig.3 DDR2 (-1A→1A)

10µsec/Div

Fig.2 DDR1 (1A→-1A)

VTT(20mV/Div)

ITT(1A/Div)

10µsec/Div

Fig.4 DDR2 (1A→-1A)

1.252

1.251

1.250

VREF(V)

1.249

1.248

-10 -5 0 5 10 IREF(mA)

Fig.5 IREF-VREF (DDR1)

0.902

0.901

0.900

VREF(V)

0.899

0.898

0.897

-10 -5 0 5 10

IREF(mA)

Fig.6 IREF-VREF (DDR2)

1.260

1.255

1.250

VTT(V)

1.245

1.240

-2 -1 0 1 2

Fig.7 ITT-VTT (DDR1)

ITT(A)

0.920

0.915

0.910

0.905

0.900

0.895

VTT(V)

0.890

0.885

0.880

-2 -1 0 1 2 ITT(A)

Fig.8 ITT-VTT (DDR2) Fig.9 Input Sequence 1

VCC

VDDQ VTT IN

VTT

VCC

VTT_IN

VDDQ VTT IN

VREF

VTT

Fig.10 Input Sequence 2 Fig.11 Input Sequence 3 Fig.12 Start up Wave Form

VTT(20mV/Div)

ITT(1A/Div)

10µsec/Div

VTT

1234

ITT_IN (1A/div)

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●Block Diagram

VCC

VDDQ

VCC

VDDQ

VCC VCC VCC

Reference

Block

UVLO

SOFT

TSD EN UVLO

Thermal

Protection

Enable

TSD

GND

●PIN Configration ●PIN Function

VCC

TSD EN UVLO

VTT_IN

7 5 6

VTT_IN

VTT

VTTS

VREF

Technical Note

VTT

½×

VDDQ

PIN No. PIN Name PIN Function

GND

VTTS

4 5

VREF

VTT

VTT_IN

VCC

VDDQ

Bottom FIN

1 GND GND Pin

2 EN Enable Input Pin

3 VTTS Detector Pin for Termination Voltage

4 VREF Reference Voltage Output Pin

5 VDDQ Reference Voltage Input Pin

6 VCC VCC Pin

7 VTT_IN Termination Input Pin

8 VTT Termination Output Pin

Substraight (Conntct to GND)

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●Description of operations

・VCC

In BD3538F/HFN, an independent power input pin is provided for an internal circuit operation of the IC. This is used to drive the amplifier circuit of the IC, and its maximum current rating is 4 mA. The power supply voltage is 3.3 to 5.5 volts. It is recommended to connect a bypass capacitor of 1 µF or so to VCC.

・VDDQ

Reference input pin for the output voltage, that may be used to satisfy the JEDEC requirement for DDR-SDRAM (VTT = 1/2VDDQ) by dividing the voltage inside the IC with two 50 k voltage-divider resistors For BD3538F/HFN, care must be taken to an input noise to VDDQ pin because this IC also cuts such noise input into half and provides it with the voltage output divided in half. Such noise may be reduced with an RC filter consisting of such resistance and capacitance (220  and 2.2 µF, for instance) that may not give significant effect to voltage dividing inside the IC.

・VTT_IN

VTT_IN is a power supply input pin for VTT output. Voltage in the range between 1.0 and 5.5 volts may be supplied to this VTT_IN terminal, but care must be taken to the current limitation due to on-resistance of the IC and the change in allowable loss due to input/output voltage difference. Generally, the following voltages are supplied:

・ DDR I VTT_IN=2.5V ・ DDRII VTT_IN=1.8V ・ DDRIII VTT_IN=1.5V

Higher impedance of the voltage input at VTT_IN may result in oscillation or degradation in ripple rejection, which must be noted. To VTT_IN terminal, it is recommended to use a 10 µF capacitor characterized with less change in capacitance. But it may depend on the characteristics of the power supply input and the impedance of the pc board wiring, which must be carefully checked before use.

・VREF

In BD3538F/HFN, a reference voltage output pin independent from VTT output is given to provide a reference input for a memory controller and a DRAM. Even if EN pin turns to “Low” level, VREF output is kept unchanged, compatible with “Self Refresh” state of DRAM. The maximum current capability of VREF is 20 mA, and a suitable capacitor is needed to stabilize the output voltage. It is recommended to use a combination of a 1.0 to 2.2 µF ceramic capacitor characterized with less change in capacitance and a 0.5 to 2.2  phase compensator resistor, or a 10µF ceramic or tantalum capacitor instead. For an application where VREF current is low, a capacitor of lower capacitance may be used. If VREF current is 1 mA or less, it is possible to secure a phase margin with a ceramic capacitor of 1 µF more or less.

・VTTS

An independent pin provided to improve load regulation of VTT output. In case that longer wiring is needed to the load at VTT output, connecting VTTS from the load side may improve the load regulation.

・VTT

A DDR memory termination output pin. BD3538F/HFN has a sink/source current capability of ±1.0A respectively. The output voltage tracks the voltage divided in half at VDDQ pin. VTT output is turned to OFF when VCC UVLO or thermal shutdown protector is activated with EN pin level turned to “Low”. Do not fail to connect a capacitor to VTT output pin for a loop gain phase compensation and a reduction in output voltage variation in the event of sudden change in load. Insufficient capacitance may cause an oscillation. High ESR (Equivalent Series Resistance) of the capacitor may result in increase in output voltage variation in the event of sudden change in load. It is recommended to use a 220 µF functional polymer capacitor (OS-CON, POS-CAP, NEO-CAP), though it depends on ambient temperature and other conditions. A low ESR ceramic capacitor may reduce a loop gain phase margin and may cause an oscillation, which may be improved by connecting a resistor in series with the capacitor.

・EN

With an input of 2.3 volts or higher, the level at EN pin turns to “Hig volts or less, the level at EN pin turns to “Low” and VTT status turns to Hi-Z. But if VCC and VDDQ are established, VREF output is maintained.

h” to provide VTT output. If the input is lowered to 0.8

Technical Note

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BD3538F,BD3538HFN

●Evaluation Board

■ BD3538F/HFN Evaluation Board Circuit

SW1

VCC

VDDQ

VCC

VTT_IN

■ BD3538F/HFN Evaluation Board Application Components

Part No Value Company Parts Name

U1 - ROHM BD3538F/HFN R4 220Ω ROHM MCR032200

J1 0Ω - -

C2 10µF MURATA GRM21 Series

C3 1µF MURATA GRM18 Series

C5 10µF MURATA GRM21 Series

C7 220µF SANYO 2R5TPE220MF

C9 2.2µF MURATA GRM18 Series

BD3538F/HFN

Technical Note

GND

VTTS

VREF

GND

VTT

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iti

Technical Note

●Notes for use

1. Absolute maximum ratings For the present product, thoroughgoing quality control is carried out, but in the event that applied voltage, working temperature range, and other absolute maximum rating are exceeded, the present product may be destroyed. Because it is unable to identify the short mode, open mode, etc., if any special mode is assumed, which exceeds the absolute maximum rating, physical safety measures are requested to be taken, such as fuses, etc.

2. GND potential Bring the GND terminal potential to the minimum potential in any operating condition.

3. Thermal design Consider allowable loss (Pd) under actual working condition and carry out thermal design with sufficient margin provided.

4. Terminal-to-terminal short-circuit and erroneous mounting When the present IC is mounted to a printed circuit board, take utmost care to direction of IC and displacement. In the event that the IC is mounted erroneously, IC may be destroyed. In the event of short-circuit caused by foreign matter that enters in a clearance between outputs or output and power-GND, the IC may be destroyed.

5. Operation in strong electromagnetic field The use of the present IC in the strong electromagnetic field may result in maloperation, to which care must be taken.

6. Built-in thermal shutdown protection circuit The present IC incorporates a thermal shutdown protection circuit (TSD circuit). The working temperature is 175°C (standard value) and has a -15°C (standard value) hysteresis width. When the IC chip temperature rises and the TSD circuit operates, the output terminal is brought to the OFF state. The built-in thermal shutdown protection circuit (TSD circuit) is first and foremost intended for interrupt IC from thermal runaway, and is not intended to protect and warrant the IC. Consequently, never attempt to continuously use the IC after this circuit is activated or to use the circuit with the activation of the circuit premised.

7. Capacitor across output and GND In the event a large capacitor is connected across output and GND, when Vcc and VIN are short-circuited with 0V or GND for some kind of reasons, current charged in the capacitor flows into the output and may destroy the IC. Use a capacitor smaller than 1000 µF between output and GND.

8. Inspection by set substrate In the event a capacitor is connected to a pin with low impedance at the time of inspection with a set substrate, there is a fear of applying stress to the IC. Therefore, be sure to discharge electricity for every process. As electrostatic measures, provide grounding in the assembly process, and take utmost care in transportation and storage. Furthermore, when the set substrate is connected to a jig in the inspection process, be sure to turn OFF power supply to connect the jig and be sure to turn OFF power supply to remove the jig.

9. Inputs to IC terminals This device is a monolithic IC with P

isolation between P-substrate and each element as illustrated below. This P-layer

and the N-layer of each element form a PN junction which works as:

・a diode if the electric potentials at the terminals satisfy the following relationship; GND>Terminal A>Terminal B, or ・a parasitic transistor if the electric potentials at the terminals satisfy the following relationship; Terminal B>GND Terminal A.

The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits, and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such manner that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in activation of parasitic elements.

Parasitic element

Pin A

P+ P

GND

Resistor Transistor (NPN)

N N

P substrate

Pin A

aras

element

Pin B

P+

Parasitic element

GND

P+

P substrate

GND

Pin B

B C

Other adjacent elements

arasitic element

GND

10. GND wiring pattern When both a small-signal GND and high current GND are present, single-point grounding (at the set standard point) is recommended, in order to separate the small-signal and high current patterns, and to be sure the voltage change stemming from the wiring resistance and high current does not cause any voltage change in the small-signal GND. In the same way, care must be taken to avoid wiring pattern fluctuations in any connected external component GND.

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11. Output capacitor (C1) Do not fail to connect a output capacitor to VREF output terminal for stabilization of output voltage. The capacitor connected to VREF output terminal works as a loop gain phase compensator. Insufficient capacitance may cause an oscillation. It is recommended to use a low temperature coefficient 1-10 µF ceramic capacitor, though it depends on ambient temperature and load conditions. It is therefore requested to carefully check under the actual temperature and load conditions to be applied.

12. Output capacitor (C4) Do not fail to connect a capacitor to VTT output pin for stabilization of output voltage. This output capacitor works as a loop gain phase compensator and an output voltage variation reducer in the event of sudden change in load. Insufficient capacitance may cause an oscillation. And if the equivalent series resistance (ESR) of this capacitor is high, the variation in output voltage increases in the event of sudden change in load. It is recommended to use a 47-220 µF functional polymer capacitor, though it depends on ambient temperature and load conditions. Using a low ESR ceramic capacitor may reduce a loop gain phase margin and cause an oscillation, which may be improved by connecting a resistor in series with the capacitor. It is therefore requested to carefully check under the actual temperature and load conditions to be applied.

13. Input capacitors (C2 and C3) These input capacitors are used to reduce the output impedance of power supply to be connected to the input terminals (VCC and VTT_IN). Increase in the power supply output impedance may result in oscillation or degradation in ripple rejecting characteristics. It is recommended to use a low temperature coefficient 1µF (for VCC) and 10µF (for VTT_IN) capacitor, but it depends on the characteristics of the power supply input, and the capacitance and impedance of the pc board wiring pattern. It is therefore requested to carefully check under the actual temperature and load conditions to be applied.

14. Input terminals (VCC, VDDQ, VTT_IN and EN) VCC, VDDQ, VTT_IN and EN terminals of this IC are made up independent one another. To VCC terminal, the UVLO function is provided for malfunction protection. Irrespective of the input order of the inputs terminals, VTT output is activated to provide the output voltage when UVLO and EN voltages reach the threshold voltage while VREF output is activated when UVLO voltage reaches the threshold. If VDDQ and VTT_IN terminals have equal potential and common impedance, any change in current at VTT_IN terminal may result in variation of VTT_IN voltage, which affects VDDQ terminal and may cause variation in the output voltage. It is therefore required to perform wiring in such manner that VDDQ and VTT_IN terminals may not have common impedance. If impossible, take appropriate corrective measures including suitable CR filter to be inserted between VDDQ and VTT_IN terminals.

15. VTTS terminal A terminal used to improve load regulation of VTT output. Connection with VTT terminal must be done not to have common impedance with high current line, which may offer better load regulation of VTT output.

16. Operating range Within the operating range, the operation and function of the circuits are generally guaranteed at an ambient temperature within the range specified. The values specified for electrical characteristics may not be guaranteed, but drastic change may not occur to such characteristics within the operating range.

17. Allowable loss Pd For the allowable loss, the thermal derating characteristics are shown in the Exhibit, which should be used as a guide. Any uses that exceed the allowable loss may result in degradation in the functions inherent to IC including a decrease in current capability due to chip temperature increase. Use within the allowable loss.

18. Built-in thermal shutdown protection circuit Thermal shutdown protection circuit is built-in to prevent thermal breakdown. Turns VTT output to OFF when the thermal shutdown protection circuit activates. This thermal shutdown protection circuit is originally intended to protect the IC itself. It is therefore requested to conduct a thermal design not to exceed the temperature under which the thermal shutdown protection circuit can work.

19. The use in the strong electromagnetic field may sometimes cause malfunction, to which care must be taken. In the event that load containing a large inductance component is co back-EMF at the start-up and when output is turned OFF is assumed, it is requested to insert a protection diode.

20. In the event that load containing a large inductance component is connected to the output terminal, and generation of back-EMF at the start-up and when output is turned OFF is assumed, it is requested to insert a protection diode.

21. We are certain that examples of applied circuit diagrams are recommendable, but you are requested to thoroughly confirm the characteristics before using the IC.In addition, when the IC is used with the external circuit changed, decide the IC with sufficient margin provided while consideration is being given not only to static characteristics but also variations of external parts and our IC including transient characteristics.

nnected to the output terminal, and generation of

(Example)

OUTPUT PIN

Technical Note

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Technical Note

●Heat Loss

Thermal design must be conducted with the operation under the conditions listed below (which are the guaranteed temperature range requiring consideration on appropriate margins etc.):

1. Ambient temperature Ta: 100°C or lower

2. Chip junction temperature Tj: 150°C or lower

The chip junction temperature Tj can be considered as follows. See Page 2/10 for θja. For the package has FIN at the bottoms of IC, package power depends on the connected copper foil area. Be sure to keep the board surface area or release the heat with setting enough through holes to inside pattern. Most of heat loss in BD3538F/HFN occurs at the output N-channel FET. The power lost is determined by multiplying the voltage between VIN and Vo by the output current. As this IC employs the power PKG, the thermal derating characteristics significantly depends on the pc board conditions. When designing, care must be taken to the size of a pc board to be used.

Power dissipation (W) = {Input voltage (V

) – Output voltage (VTT=1/2VDDQ)}×Io (Ave)

TT_IN

If VTT_IN = 1.8 volts, VDDQ=1.8 volts, and Io (Ave)=0.5 A, for instance, the power dissipation is determined as follows:

Power dissipation (W) = {1.8 (V) – 0.9 (V)} × 0.5 (A) = 0.4 (W)

●Power Dissipation

◎SOP8 ◎HSON8

800

(1) 690mW

700

600

(2) 560mW

500

400

300

200

100

Power Dissipation ：Pd （mW)

0 25 50 75 100 125 150

Ambient Temperature：Ta(℃)

(1) 70mm×70mm×1.6mm Glass-epoxy PCB θj-c=181℃/W (2) With no heat sink θj-a=222℃/W

100℃

2.0

(1) 1.75W

1.5

(2) 1.35W

1.0

(3) 0.63W

0.5

Power Dissipation ：Pd （W)

0.0

0 25 50 75 100 125 150

Ambient Temperature：Ta(℃)

(1) 1 layer (copper foil density : 65％） θja=71.4℃/W (2) 1 layer (copper foil density : 7％) θja=92.4℃/W (3) 1 layer (copper foil density : 0.2％) θja=198.4℃/W

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●Ordering part number

B D 3 5 3 8 H F N - T R

Technical Note

Part No. Part No.

SOP8

(MAX 5.35 include BURR)

4.4±0.2

6.2±0.3

0.595

1.5±0.1

0.11

HSON8

2.90±0.2

0.475

876 5

3.00±0.2

0.6MAX.

0.65

2.80±0.2

4312

1PIN MARK

0.32±0.10

5.0±0.2

1.27

(0.2)

(1.8)

(0.2)

438251

0.42±0.1

(2.2)

54632718

0.1 S

(0.05)

(0.30)

0.17

(0.15)

−4°

(0.45)

+0.1

0.05

0.13

0.3MIN

0.9±0.15

(Unit : mm)

+0.1 –0.05

Package

F : SOP8 HFN : HSON8

Embossed carrier tapeTape

Quantity

Direction of feed

Quantity

Direction of feed

2500pcs E2

The direction is the 1pin of product is at the upper left when you hold

()

reel on the left hand and you pull out the tape on the right hand

Reel

Embossed carrier tapeTape 3000pcs

The direction is the 1pin of product is at the upper right when you hold

()

reel on the left hand and you pull out the tape on the right hand

Packaging and forming specification E2: Embossed tape and reel

(SOP8)

TR: Embossed tape and reel

(HSON8)

1pin

Order quantity needs to be multiple of the minimum quantity.

∗

1pin

Direction of feed

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(Unit : mm)

10/10

Reel

Direction of feed

Order quantity needs to be multiple of the minimum quantity.

∗

2010.05 - Rev.

Notes

No copying or reproduction of this document, in par t or in whole, is permitted without the consent of ROHM Co.,Ltd.

The content specied herein is subject to change for improvement without notice.

The content specied herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specications, which can be obtained from ROHM upon request.

Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production.

Great care was taken in ensuring the accuracy of the information specied in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage.

The technical information specied herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information.

Notice

The Products specied in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, ofce-automation equipment, communication devices, electronic appliances and amusement devices).

The Products specied in this document are not designed to be radiation tolerant.

While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons.

Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, re or any other damage caused in the event of the failure of any Product, such as derating, redundancy, re control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual.

The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injur y (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing.

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R1010

ROHM BD3538F Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual