ROHM BD3538F Technical data

A

High Performance Regulators for PCs

Termination Regulators
for DDR-SDRAMs

BD3538F,BD3538HFN

No.10030EAT33

Description

BD3538F/HFN is a termination regulator compatible with JEDEC DDR-SDRAM, which functions as a linear power supply
incorporating an N-channel MOSFET and provides a sink/source current capability up to 1A respectively. A built-in
high-speed OP-AMP specially designed offers an excellent transient response. Requires 3.3 volts or 5.0 volts as a bias
power supply to drive the N-channel MOSFET. Has an independent reference voltage input pin (VDDQ) and an
independent feedback pin (VTTS) to maintain the accuracy in voltage required by JEDEC, and offers an excellent output
voltage accuracy and load regulation. Also has a reference power supply output pin (VREF) for DDR-SDRAM or a memory
controller. When EN pin turns to “Low”, VTT output becomes “Hi-Z” while VREF output is kept unchanged, compatible with
“Self Refresh” state of DDR-SDRAM.

Features

1) Incorporates a push-pull power supply for termination (VTT)

2) Incorporates a reference voltage circuit (VREF)

3) Incorporates an enabler

4) Incorporates an undervoltage lockout (UVLO)

5) Employs SOP8 package

6) Employs HSON8 package

7) Incorporates a thermal shutdown protector (TSD)

8) Operates with input voltage from 2.7 to 5.5 volts

9) Compatible with Dual Channel (DDR-II)

Use

Power supply for DDR I / II / III - SDRAM

●Absolute Maximum Ratings

Parameter Symbol

BD3538F BD3538HFN

Input Voltage VCC 7

Enable Input Voltage VEN 7

Termination Input Voltage VTT_IN 7

VDDQ Reference Voltage VDDQ 7

Ratings

*1*2

7

*1*2

7

*1*2

7

*1*2

7

*1*2

V

*1*2

V

*1*2

V

*1*2

V

Unit

Output Current ITT 1 1 A

Power Dissipation1 Pd1 560 *3 630

Power Dissipation2 Pd2 690 *4 1350

*5

mW

*6

mW

Power Dissipation3 Pd3 - 1750 *7 mW
Operating Temperature Range Tstg -40～+105 -40～+105 ℃
Storage Temperature Range Tjmax -55～+150 -55～+150 ℃
Maximum Junction Temperature Tjmax +150 +150 ℃

*1 Should not exceed Pd.
*2 Instantaneous surge voltage, back electromotive force and voltage under less than 10% duty cycle.
*3 Reduced by 4.48mW for each increase in Ta of 1℃ over 25℃(With no heat sink).
*4 Reduced by 5.52mW for each increase in Ta of 1℃ over 25℃(When mounted on a board 70mm×70mm×1.6mm Glass-epoxyPCB).
*5 Reduced by 5.04mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 1-layer)
On less than 0.2% (percentage occupied by copper foil.
*6 Reduced by 10.8mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 1-layer)
On less than 7.0% (percentage occupied by copper foil.
*7 Reduced by 14.0mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 1-layer)
On less than 65.0% (percentage occupied by copper foil.

www.rohm.com

© 2010 ROHM Co., Ltd. All rights reserved.

1/10

2010.05 - Rev.

BD3538F,BD3538HFN

A

Technical Note

●Operating Conditions (Ta=25℃)

Parameter Symbol

Min Max

Ratings

Unit

Input Voltage VCC 2.7 5.5 V

Termination Input Voltage VTT_IN 1.0 5.5 V

VDDQ Reference Voltage VDDQ 1.0 2.75 V

Enable Input Voltage VEN -0.3 5.5 V

★ No radiation-resistant design is adopted for the present product.

●Electrical Characteristics (unless otherwise noted, Ta=25℃ VCC=3.3V VEN=3V VDDQ=1.8V VTT_IN=1.8V)

Parameter Symbol

Standby Current IST

Bias Current ICC

Limits

Min Typ Max

- 0.5 1.0

- 2 4

Unit

mA

mA

VEN=0V

VEN=3V

Condition

[Enable]

High Level Enable Input Voltage VENHIGH

Low Level Enable Input Voltage VENLOW

Enable Pin Input Current IEN

2.3 - 5.5 V

-0.3 - 0.8 V

- 7 10

µA

VEN=3V

[Termination]

Termination Output Voltage 1 VTT1

VREF-30m VREF VREF+30m

ITT=-1.0A to 1.0A

V

Ta =0 ℃ to 105℃
VCC=5V, VDDQ=2.5V

Termination Output Voltage 2 VTT2

VREF-30m VREF VREF+30m

VTT_IN=2.5V

V

ITT=-1.0A to 1.0A
Ta =0 ℃ to 105℃

Source Current ITT+

Sink Current ITT­Load Regulation ⊿VTT

Line Regulation Reg.l

Upper Side ON Resistance 1 HRON1

Lower Side ON Resistance 1 LRON1

Upper Side ON Resistance 2 HRON2

Lower Side ON Resistance 2 LRON2

1.0 - - A

- - -1.0 A

- - 50

- 20 40

mV

mV

- 0.45 0.9 

- 0.45 0.9 

- 0.4 0.8

- 0.4 0.8





ITT=-1.0A to 1.0A

VCC=5V, VDDQ=2.5V
VTT_IN=2.5V

VCC=5V, VDDQ=2.5V
VTT_IN=2.5V

[Reference Voltage Input]

Input Impedance ZVDDQ

Output Voltage 1 VREF1

Output Voltage 2 VREF2

70 100 130

1/2×VDDQ

-18m

1/2×VDDQ

-40m

1/2×VDDQ

1/2×VDDQ

1/2×VDDQ

+18m

1/2×VDDQ

+40m

k

IREF=-5mA to 5mA

V

Ta =0 ℃ to 105℃
IREF=-10mA to 10mA

V

Ta =0 ℃ to 105℃
VCC=5V, VDDQ=2.5V

Output Voltage 3 VREF3

1/2×VDDQ

-25m

1/2×VDDQ

1/2×VDDQ

+25m

VTT_IN=2.5V

V

IREF=-5mA to 5mA
Ta =0 ℃ to 105℃
VCC=5V, VDDQ=2.5V

Output Voltage 4 VREF4

1/2×VDDQ

-40m

1/2×VDDQ

1/2×VDDQ

+40m

VTT_IN=2.5V

V

ITT=-10mA to 10mA
Ta =0 ℃ to 105℃

[UVLO]

Threshold Voltage VUVLO
Hysteresis Voltage ⊿VUVLO

*6 Design Guarantee

2.40 2.55 2.70 V VCC : sweep up

100 160 220

VCC : sweep down

mV

*6

*6

*6

*6

*6

*6

www.rohm.com

© 2010 ROHM Co., Ltd. All rights reserved.

2/10

2010.05 - Rev.

BD3538F,BD3538HFN

A

Technical Note

●Reference Data

VTT(20mV/Div)

VTT(20mV/Div)

ITT(1A/Div)

ITT(1A/Div)

Fig.1 DDR1 (-1A→1A) Fig.3 DDR2 (-1A→1A)

10µsec/Div

10µsec/Div

Fig.2 DDR1 (1A→-1A)

VTT(20mV/Div)

ITT(1A/Div)

10µsec/Div

Fig.4 DDR2 (1A→-1A)

1.252

1.251

1.250

VREF(V)

1.249

1.248

-10 -5 0 5 10
IREF(mA)

Fig.5 IREF-VREF (DDR1)

0.902

0.901

0.900

VREF(V)

0.899

0.898

0.897

-10 -5 0 5 10

IREF(mA)

Fig.6 IREF-VREF (DDR2)

1.260

1.255

1.250

VTT(V)

1.245

1.240

-2 -1 0 1 2

Fig.7 ITT-VTT (DDR1)

ITT(A)

0.920

0.915

0.910

0.905

0.900

0.895

VTT(V)

0.890

0.885

0.880

-2 -1 0 1 2
ITT(A)

Fig.8 ITT-VTT (DDR2) Fig.9 Input Sequence 1

VCC

EN

VDDQ
VTT IN

VTT

VCC

EN

VCC

EN

VTT_IN

VDDQ
VTT IN

VDDQ
VTT IN

VREF

VTT

VTT

Fig.10 Input Sequence 2 Fig.11 Input Sequence 3 Fig.12 Start up Wave Form

VTT(20mV/Div)

ITT(1A/Div)

10µsec/Div

VTT

1234

ITT_IN
(1A/div)

www.rohm.com

© 2010 ROHM Co., Ltd. All rights reserved.

3/10

2010.05 - Rev.

BD3538F,BD3538HFN

A

●Block Diagram

VCC

VDDQ

VCC

VDDQ

VCC VCC VCC

Reference

Block

UVLO

UVLO

SOFT

TSD
EN
UVLO

2

Thermal

Protection

EN

Enable

EN

TSD

1

GND

●PIN Configration ●PIN Function

VCC

TSD
EN
UVLO

TSD
EN
UVLO

VTT_IN

7 5 6

VTT_IN

VTT

8

3

VTTS

4

VREF

Technical Note

VTT

½×

VDDQ

PIN No. PIN Name PIN Function

GND

1

EN

2

VTTS

3

4 5

VREF

VTT

8

7

VTT_IN

VCC

6

VDDQ

Bottom FIN

1 GND GND Pin

2 EN Enable Input Pin

3 VTTS Detector Pin for Termination Voltage

4 VREF Reference Voltage Output Pin

5 VDDQ Reference Voltage Input Pin

6 VCC VCC Pin

7 VTT_IN Termination Input Pin

8 VTT Termination Output Pin

Substraight
(Conntct to GND)

www.rohm.com

© 2010 ROHM Co., Ltd. All rights reserved.

4/10

2010.05 - Rev.