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BD3533FVM
Technical data
17 pgs690.17 Kb0

ROHM BD3533FVM Technical data

TECHNICAL NOTE
High-performance Regulator IC Series for PCs
Termination Regulators for DDR-SDRAMs
BD3533F/FVM/EKN(1A),BD3531F(1.5A),BD3532F/EFV/KN(3A)
Description
Features
1) Incorporates a push-pull power supply for termination (VTT)
2) Incorporates a reference voltage circuit (VREF)
3) Incorporates an enabler
4) Incorporates an undervoltage lockout (UVLO)
5). Employs SOP8 package
6) Employs MSOP8 package
7) Employs HQFN20V package
8) Employs HTSSOP-B20 package
9) Employs VQFN28V package
10) Incorporates a thermal shutdown protector (TSD)
11) Operates with input voltage from 2.7 to 5.5 volts
12) Compatible with Dual Channel (DDR-II)
Use
Power supply for DDR I/II - SDRAM
●Line up Parameter BD3533F/FVM/EKN BD3531F BD3532F/EFV/KN
Output Current ±1.0A ±1.5A ±3Ａ Vcc Range 2.7V～5.5V 4.5V～5.5V 4.3～5.5V Soft Start Function ○ × ○ Temperature -20～100℃ -10～100℃ -40～100℃ Package SOP8/MSOP8/HQFN20V SOP8 SOP8/HTSSOP-B20/VQFN28
Oct. 2008
●ABSOLUTE MAXIMUM RATINGS
◎BD3533F/FVM/EKN
Parameter Symbol
Input Voltage VCC 7
Enable Input Voltage VEN 7
Termination Input Voltage VTT_IN 7
VDDQ Reference Voltage VDDQ 7
Output Current ITT 3 1 3 A
Power Dissipation1 Pd1 560 *3 437.5
Power Dissipation2 Pd2 690 *4
Power Dissipation3 Pd3
Power Dissipation4 Pd4 Operating Temperature Range Topr -20～+100 -20～+100 -20～+100 ℃ Storage Temperature Range Tstg -55～+150 -55～+150 -55～+150 ℃ Maximum Junction Temperature Tjmax +150 +150 +150 ℃
*1 Should not exceed Pd.
*2 Instantaneous surge voltage, back electromotive force and voltage under less than 10% duty cycle. *3 Reduced by 4.48mW for each increase in Ta of 1℃ over 25℃(With no heat sink). *4 Reduced by 5.52mW for each increase in Ta of 1℃ over 25℃(When mounted on a board 70mm×70mm×1.6mm Glass-epoxyPCB). *5 Reduced by 3.5mW for each increase in Ta of 1℃ over 25℃(With no heat sink). *6 Ta≧25℃(no heat sink)4mW/℃ increase. *7 Ta≧25℃(when mounted on 70mm x 70mm x 1.6mm Glass-epoxy PCB which does not have copper on the back side). *8 Ta≧25℃(when mounted on 70mm x 70mm x 1.6mm Glass-epoxy PCB which has 1 layer ( 60mm x 60mm ) of copper on the back side)14mW/℃ increase. *9 Ta≧25℃(When mounted on board 70mm x 70mm x 1.6mm Glass-epoxy PCB which has 2 layers ( 60mm x 60mm ) of copper on the back side )16mW/℃
increase.
◎BD3531F
Parameter Symbol Limit Unit
Input Voltage VCC 7 *1 V
EN Input Voltage VEN 7 *1 V
Termination Input Voltage VTT_IN 7 *1 V
VDDQ Reference Voltage VDDQ 7 *1 V
Output Current ITT 3 A
Power Dissipation1 Pd1 560 *2 mW
Power Dissipation2 Pd2 690 *3 mW
Operating Temperature Range Topr
Storage Temperature Range Tstg Maximum Junction Temperature Tjmax +150 ℃
*1 Should not exceed Pd. *2 Reduced by 4.48mW for each increase in Ta of 1℃ over 25℃(With no heat sink). *3 Reduced by 5.52mW for each increase in Ta of 1℃ over 25℃(When mounted on a board 70mm×70mm×1.6mm Glass-epoxyPCB).
◎BD3532F/EFV/KN
Parameter Symbol
Input Voltage VCC 7 *1 7 *1 7 *1 V
Enable Input Voltage VEN 7 *1 7 *1 7 *1 V
Termination Input Voltage VTT_IN 7 *1 7 *1 7 *1 V
VDDQ Reference Voltage VDDQ 7 *1 7 *1 7 *1 V
Output Current ITT 3 3 3 A
Power Dissipation1 Pd1 560 *2 - 460 *5 mW
Power Dissipation2 Pd2 690 *3 Operating Temperature Range Topr -40～+100 -40～+100 -40～+100 ℃ Storage Temperature Range Tstg -55～+150 -55～+150 -55～+150 ℃ Maximum Junction Temperature Tjmax +150 +150 +150 ℃
*1 Should not exceed Pd. *2 Reduced by 4.48mW for each increase in Ta of 1℃ over 25℃(With no heat sink). *3 Reduced by 5.52mW for each increase in Ta of 1℃ over 25℃(When mounted on a board 70mm×70mm×1.6mm Glass-epoxyPCB). *4 Reduced by 8.0mW for each increase in Ta of 1℃ over 25℃(When mounted on a board 70mm×70mm×1.6mm Glass-epoxyPCB). *5 Reduced by 3.68mW for each increase in Ta of 1℃ over 25℃(With no heat sink). *6 Reduced by 5.80mW for each increase in Ta of 1℃ over 25℃(When mounted on a board 70mm×70mm×1.6mm Glass-epoxyPCB).
BD3533F BD3533FVM
*1*2
7
*1*2
7
*1*2
7
*1*2
7
*1*2
7
*1*2
7
*1*2
7
*1*2
7
*5
500
-
- -
- -
-10～
-55～
BD3532F BD3532EFV
℃ ℃
1000 *
BD3532KN Unit
4
2/16
BD3533EKN Unit
*1*2
V
*1*2
V
*1*2
V
*1*2
V
*6
mW
750 *7 mW
1750 *8 mW
2000 *9 mW
6
725 *
mW
●RECOMMENDED OPERATING CONDITIONS
◎BD3533F/FVM/EKN(Ta=25℃)
Parameter Symbol MIN MAX Unit
Input Voltage VCC 2.7 5.5 V
Termination Input Voltage VTT_IN 1.0 5.5 V
VDDQ Reference Voltage VDDQ 1.0 2.75 V
Enable Input Voltage VEN -0.3 5.5 V
◎BD3531F(Ta=25℃)
Parameter Symbol MIN MAX Unit
Input Voltage VCC 4.5 5.5 V
Termination Input Voltage VTT_IN 1.0 5.5 V
EN Input Voltage VEN -0.3 5.5 V
◎BD3532F/EFV/KN(Ta=25℃)
Parameter Symbol MIN MAX Unit
Input Voltage VCC 4.3 5.5 V
Termination Input Voltage VTT_IN 1.0 5.5 V
EN Input Voltage VEN -0.3 5.5 V
★ No radiation-resistant design is adopted for the present product.
●ELECTRICAL CHARACTERISTICS
◎BD3533F/FVM/EKN
ELECTRICAL CHARACTERISTICS(unless otherwise noted, Ta=25℃ VCC=3.3V VEN=3V VDDQ=1.8V VTT_IN=1.8V)
Parameter Symbol
Standard Value
MIN TYP MAX
Unit Condition
Standby Current IST - 0.8 1.6 mA VEN=0V
Bias Current ICC - 2 4 mA VEN=3V
[Enable]
High Level Enable Input Voltage VENHIGH 2.3 - 5.5 V
Low Level Enable Input Voltage VENLOW -0.3 - 0.8 V
Enable Pin Input Current IEN - 7 10 uA VEN=3V
[Termination]
Termination Output Voltage 1 VTT1
VREF
-30m
VREF
VREF +30m
ITT=-1.0A to 1.0A
V
Ta =0 ℃ to 100℃
VCC=5V, VDDQ=2.5V
Termination Output Voltage 2 VTT2
VREF
-30m
VREF
VREF +30m
VTT_IN=2.5V
V
ITT=-1.0A to 1.0A Ta =0 ℃ to 100℃
Source Current ITT+ 1.0 - - A
Sink Current ITT- - - -1.0 A Load Regulation ⊿VTT - - 50 mV ITT=-1.0A to 1.0A
Line Regulation Reg.l - 20 40 mV Upper Side ON Resistance 1 HRON1 - 0.45 0.9 Ω Lower Side ON Resistance 1 LRON1 - 0.45 0.9 Ω
Upper Side ON Resistance 2 HRON2 - 0.4 0.8 Ω
Lower Side ON Resistance 2 LRON2 - 0.4 0.8 Ω
VCC=5V, VDDQ=2.5V VTT_IN=2.5V
VCC=5V, VDDQ=2.5V VTT_IN=2.5V
*7 Design Guarantee
*7
*7
3/16
●ELECTRICAL CHARACTERISTICS
◎BD3533F/FVM/EKN
ELECTRICAL CHARACTERISTICS(unless otherwise noted, Ta=25℃ VCC=3.3V VEN=3V VDDQ=1.8V VTT_IN=1.8V)
Parameter Symbol
MIN TYP MAX
Standard Value
Unit Condition
[Input of Reference Voltage] Input Impedance ZVDDQ 70 100 130 kΩ
Output Voltage1 VREF1
Output Voltage2 VREF2
Output Voltage3 VREF3
1/2×VDDQ
-18m
1/2×VDDQ
-40m
1/2×VDDQ
-25m
1/2×VDDQ
1/2×VDDQ
1/2×VDDQ
1/2×VDDQ
+18m
1/2×VDDQ
+40m
1/2×VDDQ
+25m
IREF=-5mA to 5mA
V
Ta =0 ℃ to 100℃
IREF=-10mA to 10mA
V
Ta =0 ℃ to 100℃*7
VCC=5V, VDDQ=VTT_IN=2.5V
IREF=-5mA to 5mA
V
Ta =0 ℃ to 100℃
*7
*7
VCC=5V, VDDQ=VTT_IN=2.5V
IREF=-10mA to 10mA
V
Ta =0 ℃ to 100℃
*7
Output Voltage4 VREF4
1/2×VDDQ
-40m
1/2×VDDQ
1/2×VDDQ
+40m
[Reference voltage]
Source Current IREF+ 20 - - mA
Sink Current IREF- - - -20 mA
[UVLO]
UVLO OFF Voltage VUVLO 2.40 2.55 2.70 V VCC : sweep up
Hysteresis Voltage ⊿VUVLO 100 160 220 mV VCC : sweep down
*7 Design Guarantee
◎BD3531F
ELECTRICAL CHARACTERISTICS(unless otherwise noted, Ta=25℃ VCC=5V VEN=3V VDDQ=2.5V VTT_IN=2.5V)
Parameter Symbol
Standard Value
MIN TYP MAX
Unit Condition
Standby Current IST - 0.8 1.6 mA VEN=0V
Bias Current ICC - 2 4 mA
[Enable]
Hi Level Enable Input Voltage VENHI 2 - 5.5 V
Low Level Enable Input Voltage VENLOW -0.3 - 0.8 V
Enable Pin Input Current IEN - 7 10 uA VEN=3V
[Termination]
Termination Output Voltage VTT
VREF
-30mV
VREF
VREF
+30mV
Io=-1.5A to 1.5A
V
Ta =0 ℃ to 100℃ *
8
Source Current ITT+ 1.5 - - A
Sink Current ITT- - - -1.5 A Load Regulation ⊿VTT - - 40 mV Io=-1.5A to 1.5A
Line Regulation Reg.l - 20 40 mV VCC=4.5V to 5.5V Upper Side ON Resistance HRON - 0.4 0.8 Ω Lower Side ON Resistance LRON - 0.4 0.8 Ω
[Input of Reference Voltage] Input Impedance ZVDDQ - 100 - kΩ
[Reference voltage]
Output Voltage1 VREF1 1/2×VDDQ-30m 1/2×VDDQ 1/2×VDDQ+30m V IREF=0mA
Output Voltage2 VREF2
1/2×VDDQ
-40m
1/2×VDDQ
1/2×VDDQ
+40m
IREF=-10mA to 10mA
V
Ta =0 ℃ to 100℃ *8
Source Current IREF+ 10 20 - mA
Sink Current IREF- - -20 -10 mA
[UVLO]
UVLO OFF Voltage VUVLO 4.2 4.35 4.5 V VCC : Sweep up Hysteresis Voltage ⊿VUVLO 100 160 220 mV VCC : Sweep down
*8 Design Guarantee
4/16
◎BD3532F/EFV/KN
ELECTRICAL CHARACTERISTICS(unless otherwise noted, Ta=25℃ VCC=5V VEN=3V VDDQ=2.5V VTT_IN=2.5V)
Parameter Symbol
MIN TYP MAX
Standard Value
Unit Condition
Standby Current IST - 0.8 1.6 mA VEN=0V
Bias Current ICC - 2 4 mA
[Enable]
Hi Level Enable Input Voltage
Low Level Enable Input Voltage
VENHI 2.3 - 5.5 V
VENLOW -0.3 - 0.8 V
VCC=4.3V to 5.5V Ta =0 ℃ to 100℃ *
VCC=4.3V to 5.5V Ta =0 ℃ to 100℃ *
9
9
Enable Pin Input Current IEN - 7 10 uA VEN=3V
[Termination]
Termination Output Voltage VTT
VREF
-30mV
VREF
VREF
+30mV
Io=-3A to 3A
V
Ta =0 ℃ to 100℃ *9
Source Current ITT+ 3 - - A
Sink Current ITT- - - -3 A Load Regulation ⊿VTT - - 40 mV Io=-3A to 3A
Line Regulation Reg.l - 20 40 mV VCC=4.3V to 5.5V Upper Side ON Resistance HRON - 0.2 0.4 Ω Lower Side ON Resistance LRON - 0.2 0.4 Ω
[Input of Reference Voltage] Input Impedance ZVDDQ 70 100 130 kΩ
Output Voltage1 VREF1
Output Voltage2 VREF2
Output Voltage1’ VREF1’
Output Voltage2’ VREF2’
1/2×VDDQ
-30mV
1/2×VDDQ
-40mV
1/2×VDDQ
-30mV
1/2×VDDQ
-40mV
1/2×VDDQ
1/2×VDDQ
1/2×VDDQ
1/2×VDDQ
1/2×VDDQ
+30mV
1/2×VDDQ
+40mV
1/2×VDDQ
+30mV
1/2×VDDQ
+40mV
V IREF=0mA
IREF=-10mA to 10mA
V
Ta =0 ℃ to 100℃ *9
VDDQ=VTT_IN1=VTT_IN2=1.8V
V
IREF=0mA
VDDQ=VTT_IN1=VTT_IN2=1.8V
V
IREF=-10mA to 10mA Ta =0 ℃ to 100℃ *
9
Source Current1 IREF1+ 20 - - mA
Sink Current1 IREF1- - - -20 mA
Source Current2 IREF2+ 20 - - mA VDDQ=VTT_IN1=VTT_IN2=1.8V
Sink Current2 IREF2- - - -20 mA VDDQ=VTT_IN1=VTT_IN2=1.8V
[UVLO]
UVLO OFF Voltage VUVLO 4.0 4.15 4.3 V VCC : sweep up Hysteresis Voltage ⊿VUVLO 100 160 220 mV VCC : sweep down
*9 Design Guarantee
5/16
●Reference Data
(
VTT(10mV/Div)
VTT(10mV/Div)
VTT(20mV/Div)
ITT(1A/Div)
10μsec/Div 10μsec/Div 10μsec/Div
ITT(1A/Div)
ITT(1A/Div)
Fig.1 DDRⅠ(-1A→1A) BD3531 Fig.3 DDRⅠ(-1A→1A) BD3533
Fig.2 DDRⅠ(-1A→1A) BD3532
VTT
10mV/Div)
VTT(10mV/Div)
VTT(20mV/Div)
ITT(1A/Div)
ITT(1A/Div)
ITT(1A/Div)
10μsec/Div 10μsec/Div 10μsec/Div
Fig.4 DDRⅠ(1A→-1A) BD3531 Fig.5 DDRⅠ(1A→-1A) BD3532 Fig.6 DDRⅠ(1A→-1A) BD3533
VTT(10mV/Div)
VTT(10mV/Div)
VTT(20mV/Div)
Fig.7 DDRⅡ(-1A→1A) BD3531 Fig.8 DDRⅡ(-1A→1A) BD3532 Fig.9 DDRⅡ(-1A→1A) BD3533
ITT(1A/Div)
10μsec/Div 10μsec/Div 10μsec/Div
ITT(1A/Div)
ITT(1A/Div)
VTT(10mV/Div)
VTT(10mV/Div)
VTT(20mV/Div)
ITT(1A/Div)
10μsec/Div 10μsec/Div 10μsec/Div
ITT(1A/Div)
ITT(1A/Div)
Fig.10 DDRⅡ(1A→-1A) BD3531 Fig.11 DDRⅡ(1A→-1A) BD3532 Fig.12 DDRⅡ(1A→-1A) BD3533
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