ROHM BD35281HFN Technical data

A

High Performance Regulators for PCs

Nch FET Ultra LDO
for Desktop PCs

BD35281HFN

●Description

The BD35281HFN ultra low-dropout linear regulator operates from a very low input supply, and offers ideal performance in
low input voltage to low output voltage applications. It incorporates a built-in N-MOSFET power transistor to minimize the
input-to-output voltage differential to the ON resistance (R
the regulator realizes high current output (Iomax=1.5A) with reduced conversion loss, and thereby obviates the switching
regulator and its power transistor, choke coil, and rectifier diode. Thus, the BD35281HFN designed to enable significant
package profile downsizing and cost reduction. In BD35281HFN, The NRCS (soft start) function enables a controlled output
voltage ramp-up, which can be programmed to whatever power supply sequence is required.

●Features

1) Internal high-precision reference voltage circuit (0.65V±1%)

2) Internal high-precision output voltage circuit

3) Built-in V

4) NRCS (soft start) function reduces the magnitude of in-rush current

5) Internal Nch MOSFET driver offers low ON resistance (100mΩ typ)

6) Built-in short circuit protection (SCP)

7) Built-in current limit circuit (1.5A min)

8) Built-in thermal shutdown (TSD) circuit

9) Small package HSON8 : 2.9mm×3.0mm×0.6mm

10) Tracking function

●Applications

Notebook computers, Desktop computers, LCD-TV, DVD, Digital appliances

●Absolute maximum ratings (Ta=25℃)

undervoltage lockout circuit (VCC=3.80V)

CC

ON max=150mΩ) level. By lowering the dropout voltage in this way,

No.11030EAT38

Parameter Symbol Ratings Unit

Input Voltage 1 VCC +6.0 *1 V

Input Voltage 2 VIN +6.0 *1 V

Maximum Output Current IO 2*1 A

Enable Input Voltage VEN -0.3～+6.0 V

Power Dissipation 1 Pd1 0.63 *2 W

Power Dissipation 2 Pd2 1.35 *3 W

Power Dissipation 3 Pd3 1.75*4 W

Operating Temperature Range Topr -10～+100 ℃

Storage Temperature Range Tstg -55～+125 ℃

Maximum Junction Temperature Tjmax +150 ℃

*1 Should not exceed Pd.
*2 Reduced by 5.04mW/℃ for each increase in Ta≧25℃
(when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 1-layer, copper foil area : less than 0.2%)
*3 Reduced by 10.8mW/℃ for each increase in Ta≧25℃
(when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 1-layer, copper foil area : less than 7.0%)
*4 Reduced by 14.0mW/℃ for each increase in Ta≧25℃
(when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 1-layer, copper foil area : less than 65.0%)

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BD35281HFN

●Operating Voltage (Ta=25℃)

Parameter Symbol

Ratings

Min. Max.

Unit

Input Voltage 1 VCC 4.3 5.5 V

Input Voltage 2 VIN 1.5 VCC-1 *5 V

Output Voltage Setting Range IO 1.2 (fixed) V

Enable Input Voltage VEN -0.3 5.5 V

NRCS Capacity CNRCS 0.001 1 µF

*5 VCC and VIN do not have to be implemented in the order listed.

★This product is not designed for use in radioactive environments.

●Electrical Characteristics (Unless otherwise specified, Ta=25℃, VCC=5V, VEN=3V, VIN=1.7V)

Parameter Symbol

Min. Typ. Max.

Limits

Unit Condition

Bias Current ICC - 0.7 1.2 mA

VCC Shutdown Mode Current IST - 0 10 µA VEN=0V

Output Voltage IO 1.5 - - A

Technical Note

Feedback Voltage 1 VOS1 1.188 1.200 1.212 V

Feedback Voltage 2 VOS2 1.176 1.200 1.224 V Tj=-10 to 100℃

Line Regulation 1 Reg.l1 - 0.1 0.5 %/V VCC=4.3V to 5.5V

Line Regulation 2 Reg.l2 - 0.1 0.5 %/V VIN=1.5V to 3.3V

Load Regulation Reg.L - 0.5 10 mV IO=0 to 1.5A

=1.5A,VIN=1.2V,

I

Output ON Resistance RON - 100 150 mΩ

Standby Discharge Current I

1 - - mA VEN=0V, VO=1V

DEN

O

Tj=-10 to 100℃

[ENABLE]

Enable Pin Input Voltage High EN

Enable Pin Input Voltage Low EN

2 - - V

HIGH

0 - 0.8 V

LOW

Enable Input Bias Current IEN - 7 10 µA VEN=3V

[NRCS]

NRCS Charge Current I

NRCS Standby Voltage V

12 20 28 µA

NRCS

- 0 50 mV VEN=0V

STB

[UVLO]

VCC Undervoltage Lockout
Threshold Voltage

VCC Undervoltage Lockout
Hysteresis Voltage

VIN Undervoltage Lockout
Threshold Voltage

VCCUVLO 3.5 3.8 4.1 V VCC:Sweep-up

V

HYS 100 160 220 mV VCC:Sweep-down

CC

UVLO 0.72 0.84 0.96 V VIN:Sweep-up

V

IN

[SCP]

SCP Start up Voltage V

SCP Threshold Voltage T

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VO×0.3 VO×0.4 VO×0.5 V

OSCP

45 90 200 µsec

SCP

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BD35281HFN

v

v

v

v

v

v

v

v

v

v

v

v

●Reference Data

Vo

66mV

50mV/di

Io

1A/di

2A

Fig.1 Transient Response

(0A→1.5A)

Co=100µF

cfb=1000pF

Vo

50mV/di

51mV

Io

1A/di

2A

Fig.4 Transient Response

(1.5A→0A)

Co=100µF

cfb=1000pF

Ven

VNRCS

Vo

Fig.7 Waveform at output start

V

CC

Ven

V

IN

Vo

Fig.10 Input sequence

T(10µsec/div)

T(100µsec/div)

T(200µsec/div)

VIN→VCC→Ven

Vo

2A/di

91mV

Io

2A

50mV/di

Fig.2 Transient Response

(0A→1.5A)

Co=47µF

cfb=1000pF

Vo

80mV

50mV/di

Io

2A

1A/di

Fig.5 Transient Response

(1.5A→0A)

Co=47µF

cfb=1000pF

Ven

VNRCS

Vo

Fig.8 Waveform at output OFF

Ven

V

IN

Vo

V

CC

Fig.11 Input sequence

T(10µsec/div)

T(100µsec/div)

T(200µsec/div)

Ven →VCC→V

Technical Note

Vo

50mV/di

108mV

Io

1A/di

Fig.3 Transient Response

Vo

1A/di

98mV

2A

Io

50mV/di

Fig.6 Transient Response

V

CC

Ven

V

IN

Vo

V

CC

Ven

V

IN

Vo

IN

Fig.12 Input sequence

2A

T(10µsec/div)

(0A→1.5A)

Co=22µF

cfb=1000pF

T(100µsec/div)

(1.5A→0A)

Co=22µF

cfb=1000pF

VCC→VIN→Ven

Fig.9 Input sequence

VCC→Ven →VIN

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3/15

2011.01 - Rev.

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BD35281HFN

●Reference Data

V

CC

Ven

V

IN

Vo

Fig.13 Input sequence

0.9

0.8

0.7

Icc [mA]

0.6

0.5

0.4

-50 -25 0 25 50 75 100 125 150
Tj [℃]

Fig.16 Tj-ICC

30

25

20

15

IINSTB [µ A]

10

5

0

-50 -25 0 25 50 75 100 125 150
Tj [℃]

Fig.19 Tj-IINSTB

150

130

110

90

RON [mO]

70

50

-50 -25 0 25 50 75 100 125 150

Tj [℃]

Fig.22 Tj-R

(Vcc=5V/Vo=1.2V)

V

→Ven →V

ON

V

CC

Ven

V

IN

Vo

Ven →VIN→V

Fig.14 Input sequence

2.0

1.8

1.6

IIN [m A]

1.4

1.2

1.0

-50 -25 0 25 50 75 100 125 150
Tj [℃]

Fig.17 Tj-IIN

20

19

18

17

16

15

14

INRCS [µA]

13

12

11

10

-50 -25 0 25 50 75 100 125 150

Tj [℃]

Fig.20 Tj-NRCS

135

RON [mO]

125

115

105

95

85

75

Vo=2 .5V

Vo=1 .8V

Vo=1 .5V

Vo=1 .2V

Vo=1 .0V

34 56 78

Vcc [V]

Fig.23 Vcc- R

ON

Technical Note

1.25

1.23

1.21

Vo [V]

1.19

1.17

CC

1.15

-50 -25 0 25 50 75 100 125 150
Tj [℃]

Fig.15 Tj-Vo (Io=0mA)

3.0

2.5

2.0

1.5

ISTB [µA]

1.0

0.5

0.0

-50 -25 0 25 50 75 100 125 150

Tj [℃]

Fig.18 Tj-ICCSTB

10

9

8

7

6

5

IEN [µ A]

4

3

2

1

0

-50 -25 0 25 50 75 100 125 150

Tj [℃]

Fig.21 Tj-IEN

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2011.01 - Rev.

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BD35281HFN

●Block Diagram

VCC

V

CC

1

EN

2

Reference

Block

C1

V

CC

UVLO2

UVLO1

EN

UVLO1

VIN

UVLOLATCH

CL

VREF1

NRCS

VCC

NRCS0.3.

VREF1×0.4

FB

TSD

SCP/TSD

LATCH

EN
UVLO1

LATCH

CL
UVLO1
UVLO2
TSD
SCP

NRCS

C

3

NRCS

EN/UVLO

NRCS

●Pin Layout ●Pin Function

EN

V

CC

Current

Limit

VREF2

8

GND

R2

R1

R2

R1

Technical Note

VIN

4

V

O

5

6

V

OS

7

FB

VIN

C2

C

FB

V

C3

O

Vcc

EN

NRCS

VIN

PIN No.

6

1

8

GND

PIN name PIN Function

1 VCC Power Supply Pin

2 EN Enable Input Pin

2

FIN

7

FB

4 VIN Input Voltage Pin

3 NRCS

In-rush Current Protection (NRCS)
Capacitor Connection Pin

5 VO Output Voltage Pin

3

6

Vos

6 VOS Output Voltage Control Pin

4

5

Vo

7 FB Reference Voltage Feedback Pin

8 GND Ground Pin

- FIN Connected to heatsink and GND

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2011.01 - Rev.

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BD35281HFN

Technical Note

●Operation of Each Block
・AMP

This is an error amp that compares the reference voltage (0.65V) with V

to drive the output Nch FET (Ron=150mΩ).

O

Frequency optimization helps to realize rapid transient response, and to support the use of ceramic capacitors on the
output capacitors. AMP input voltage ranges from GND to 2.7V, while the AMP output ranges from GND to V
is OFF, or when UVLO is active, output goes LOW and the output of the NchFET switches OFF.

・EN

The EN block controls the regulator’s ON/OFF state via the EN logic input pin. In the OFF position, circuit voltage is
maintained at 0µA, thus minimizing current consumption at standby. The FET is switched ON to enable discharge of the
NRCS pin V
electrical connection is required (e.g. between the V

, thereby draining the excess charge and preventing the IC on the load side from malfunctioning. Since no

O

pin and the ESD prevention diode), module operation is

CC

independent of the input sequence.

UVLO

・V

CC

To prevent malfunctions that can occur during a momentary decrease in V
and (like the EN block) discharges NRCS and V

. Once the UVLO threshold voltage (TYP3.80V) is reached, the power-on

O

, the UVLO circuit switches the output OFF,

CC

reset is triggered and output continues.

・VINUVLO

When V
remains ON even if V
Unlike EN and V

voltage exceeds the threshold voltage, VDUVLO becomes active. Once active, the status of output voltage

D

voltage drops. (When VIN voltage drops, SCP engages and output switches OFF.)

D

, it is effective at output startup. VDUVLO can be restored either by reconnecting the EN pin or VCC pin.

CC

・CURRENT LIMIT

When output is ON, the current limit function monitors the internal IC output current against the parameter value. When
current exceeds this level, the current limit module lowers the output current to protect the load IC. When the overcurrent
state is eliminated, output voltage is restored to the parameter value. However, when output voltage falls to or below the
SCP startup voltage, the SCP function becomes active and the output switches OFF.

・NRCS (Non Rush Current on Start-up)

The soft start function enabled by connecting an external capacitor between the NRCS pin and ground. Output ramp-up
can be set for any period up to the time the NRCS pin reaches V

(0.65V). During startup, the NRCS pin serves as a

FB

20µA (TYP) constant current source to charge the external capacitor. Output start time is calculated via the formula below.

FBNRCS

VC



NRCS

.)typ(T



NRCS

I

・TSD (Thermal Shut down)

The shutdown (TSD) circuit automatically is latched OFF when the chip temperature exceeds the threshold temperature
after the programmed time period elapses, thus serving to protect the IC against “thermal runaway” and heat damage.
Because the TSD circuit is intended to shut down the IC only in the presence of extreme heat, it is crucial that the Tj (max)
parameter not be exceeded in the thermal design ,in order to avoid potential problems with the TSD.

・V

IN

The V
connection (such as between the V
input sequence. However, since an output NchFET body diode exists between V

line acts as the major current supply line, and is connected to the output NchFET drain. Since no electrical

IN

pin and the ESD protection diode) is necessary, VIN operates independent of the

CC

and VO, a VIN-VO electric (diode)

IN

connection is present. Note, therefore, that when output is switched ON or OFF, reverse current may flow to V

・SCP

When output voltage (Vo) drops, the IC assumes that VO pin is shorted to GND and switches the output voltage OFF. After
the GND short has been detected and the programmed delay time has elapsed, output is latched OFF. It is also effective
during output startup. SCP can be cleared either by reconnecting the EN pin or VCC pin.

. When EN

CC

from VO.

IN

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2011.01 - Rev.

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BD35281HFN

●Timin g Chart
EN ON/OFF

VIN

V

CC

EN

NRCS

Vo

ON/OFF

V

CC

VIN

V

CC

EN

NRCS

Vo

0.65V(typ)

UVLO

0.65V(typ)

Technical Note

Star tup

t

Hysteresis

Star tup

t

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2011.01 - Rev.

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BD35281HFN

●Timin g Chart

ON

V

IN

VIN

VCC

EN

NRCS

Vo

SCP OFF

VIN

VCC

EN

NRCS

Vo

VINUVLO

SCP startup voltage

Technical Note

SCP delay time

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2011.01 - Rev.

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BD35281HFN

●Evaluation Board

BD35281HFN Evaluation Board Schematic

■■

V

CC

GND

SW1

R8

C12

GND

V

CC

EN

C11

GND

V

IN

C4

R4

C7

NRCS

VIN_S

C3

GND

GND

GND

■BD35281HFN Evaluation Board List

■

Component Rating Manufacturer Product Name

U1 - ROHM BD35281HFN

C1 1µF MURATA GRM188B11A105KD

C3 10µF KYOCERA CM32X5R226M10A

C5 22µF KYOCERA CM32X5R226M10A

C11 0.01µF MURATA GRM188B11H103KD

C13 1000pF MURATA GRM188B11H102KD

R4 0Ω - Jumper
R8 0Ω - Jumper

■BD35281HFN Evaluation Board Layout

■

(2nd layer and 3rd layer are GND line.)

Silk Screen

GND

GND

VCC

C1

C2

1

U1

2

BD35281HFN

3

4

GND

TOP Layer

8

GND

7

6

5

GND GND

C13

GND

GND_S

GND

Vos

C5

GND

2

C14

GND

3

R9

5

C6

TP2

4

FB

Vo_S

GND

JPF2

C8

R3

C9

GND

VCC

U3

Bottom Layer

Technical Note

Vo

R5

7 5 6 8

U2

3 2 1

GND

R6

4

R7

GND

TP1

JPF1

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9/15

2011.01 - Rev.

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BD35281HFN

●Recommended Circuit Example

V

cc

EN

VIN

Component

Recommended

Val ue

C3 22µF

Technical Note

GND

V

cc

1 8

C1

EN

2

R4

C4

C2

NRCS

3

VIN

4

6

FB

7

V

o

6

V

o

5

Programming Notes and Precautions

To assure output voltage stability, please be certain the output capacitors are connected
between Vo pin and GND. Output capacitors play a role in loop gain phase
compensation and in mitigating output fluctuation during rapid changes in load level.
Insufficient capacitance may cause oscillation, while high equivalent series reisistance
(ESR) will exacerbate output voltage fluctuation under rapid load change conditions.
While a 22µF ceramic capacitor is recomended, actual stability is highly dependent on
temperature and load conditions. Also, note that connecting different types of capacitors
in series may result in insufficient total phase compensation, thus causing oscillation. In
light of this information, please confirm operation across a variety of temperature and
load conditions.

GND

FB

C5

V

o

C3

Input capacitors reduce the output impedance of the voltage supply source connected to
the (V
(V

C1 1µF

While a low-ESR 1µF capacitor with minimal susceptibility to temperature is
recommended, stability is highly dependent on the input power supply characteristics
and the substrate wiring pattern. In light of this information, please confirm operation
across a variety of temperature and load conditions.

Input capacitors reduce the output impedance of the voltage supply source connected to
the (VIN) input pins. If the impedance of this power supply were to increase, input voltage
(V

C2 10µF

While a low-ESR 10µF capacitor with minimal susceptibility to temperature is
recommended, stability is highly dependent on the input power supply characteristics
and the substrate wiring pattern. In light of this information, please confirm operation
across a variety of temperature and load conditions.

The Non Rush Current on Startup (NRCS) function is built into the IC to prevent rush
current from going through the load (VIN to VO) and impacting output capacitors at power
supply start-up. Constant current comes from the NRCS pin when EN is HIGH or the

C4 0.01µF

UVLO function is deactivated. The temporary reference voltage is proportionate to time,
due to the current charge of the NRCS pin capacitor, and output voltage start-up is
proportionate to this reference voltage. Capacitors with low susceptibility to temperature
are recommended, in order to assure a stable soft-start time.

C5

1000pF

This component is employed when the C3 capacitor causes, or may cause, oscillation.
It provides more precise internal phase correction.

) input pins. If the impedance of this power supply were to increase, input voltage

CC

) could become unstable, leading to oscillation or lowered ripple rejection function.

CC

) could become unstable, leading to oscillation or lowered ripple rejection function.

IN

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10/15

2011.01 - Rev.

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BD35281HFN



●Heat Loss
Thermal design should allow operation within the following conditions. Note that the temperatures listed are the allowed
temperature limits, and thermal design should allow sufficient margin from the limits.

1. Ambient temperature Ta can be no higher than 100℃.

2. Chip junction temperature (Tj) can be no higher than 150℃.

Chip junction temperature can be determined as follows:

① Calculation based on ambient temperature (Ta)

Tj=Ta+θj-a×W

＜Reference values＞

θj-a:HSON8 198.4℃/W

92.4℃/W

71.4℃/W

Substrate size: 70×70×1.6mm

It is recommended to layout the VIA for heat radiation in the GND pattern of reverse (of IC) when there is the GND pattern in
the inner layer (in using multiplayer substrate). This package is so small (size: 2.9mm×3.0mm) that it is not available to
layout the VIA in the bottom of IC. Spreading the pattern and being increased the number of VIA like the figure below enable
to get the superior heat radiation characteristic. (This figure is the image. It is recommended that the VIA size and the
number is designed suitable for the actual situation.).

Most of the heat loss that occurs in the BD35281HFN is generated from the output Nch FET. Power loss is determined by the

IN-Vo voltage and output current. Be sure to confirm the system input and output voltage and the output current

total V
conditions in relation to the heat dissipation characteristics of the V
dissipation may vary substantially depending on the substrate employed (due to the power package incorporated in the
BD3523XHFN) make certain to factor conditions such as substrate size into the thermal design.

Example)

Where V

=1.7V, Vo=1.2V, Io(Ave) = 2A,

IN



1.0(W)=

1-layer substrate (copper foil area : below 0.2%)
1-layer substrate (copper foil area : 7%)
2-layer substrate (copper foil area : 65%)

2.0(A) (V) 1.2 -(V) 1.7 = (W) nconsumptio Power 

3

(substrate with thermal via)

IN and Vo in the design. Bearing in mind that heat



Io(Ave) )(V voltage Output -)(V voltage Input = (W) nconsumptio Power OIN 

Technical Note

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11/15

2011.01 - Rev.

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BD35281HFN

●Input-Output Equivalent Circuit Diagram

V

CC

VCC

NRCS

1kΩ

1kΩ

1kΩ

1kΩ

1kΩ

210kΩ

1kΩ

90kΩ

VCC

Vo

50kΩ

10kΩ

●Heat Dissipation Characteristics

◎HSON8

[W]

2.0
(3) 1.75W

1.5

(2) 1.35W

1.0

Power Dissipation [Pd]

(1) 0.63W

0.5

0

0 25 75 100 125 150 50

Ambient Temperature [Ta]

1kΩ

FB

VIN

1kΩ

VCC

V

OS

1kΩ

1kΩ

(1) 1 layer substrate (substrate surface copper foil area: below 0.2%)
θj-a=198.4℃/W
(2) 2 layer substrate (substrate surface copper foil area:7%)
θj-a=92.4℃/W
(3) 2 layer substrate (substrate surface copper foil area:65%)
θj-a=71.4℃/W

[℃]

EN

Technical Note

400kΩ

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2011.01 - Rev.

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BD35281HFN

●Notes for use

1. Absolute maximum ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can
break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any
over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as
fuses.

2. Connecting the power supply connector backward
Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply
lines. An external direction diode can be added.

3. Power supply lines
Design PCB layout pattern to provide low impedance GND and supply lines. To obtain a low noise ground and supply line,
separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power supply terminals
to ICs, connect a capacitor between the power supply and the GND terminal. When applying electrolytic capacitors in the
circuit, not that capacitance characteristic values are reduced at low temperatures.

4. GND voltage
The potential of GND pin must be minimum potential in all operating conditions.

5.Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.

6. Inter-pin shorts and mounting errors
Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any
connection error or if pins are shorted together.

7. Actions in strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to
malfunction.

8. ASO
When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO.

9. Thermal shutdown circuit
The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is
designed only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or guarantee its operation.
Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit
is assumed.

(Example)

OUTPUT PIN

TSD on temperature [°C] (typ.)

Technical Note

BD35281HFN 175

10. Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or
removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic
measure. Use similar precaution when transporting or storing the IC.

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2011.01 - Rev.

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BD35281HFN

Technical Note

11. Regarding input pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode
or transistor. For example, the relation between each potential is as follows:

When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.

When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes
operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used.

Pin A

Parasitic
element

N

+

P

GND

Resistor Transistor (NPN)

P

P

P substrate

Pin B

Pin A

N

+

N N

Parasitic
element

Parasitic element

+

P

B

C

E

N

GND

+

P

P

P substrate

N

GND

Pin B

B C

E

GND

Other adjacent elements

Example of IC structure

12. Ground Wiring Pattern.
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns,
placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage
variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the
GND wiring pattern of any external components, either.

Parasitic
element

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2011.01 - Rev.

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BD35281HFN

●Ordering part number

B D 3 5 2 8 1 H F N - T R

Technical Note

Part No. Part No.

HSON8

2.9± 0.1

(MAX 3.1 include. BURR)

0.475

8765

2.8± 0.1

3.0± 0.2

1PIN MARK

0.6MAX

+0.03

–0.02

0.02

0.65

<Tape and Reel information>

(0.05)

(2.2)

(0.2)

4312

0.32±0.1

S

(1.8)

0.1 S

5678

(0.45)

4321

(0.2)

0.08

(0.3)

(0.15)

+0.1

0.13

–0.05

M

(Unit : mm)

Package
HFN: HSON8

Quantity

Direction
of feed

Packaging and forming specification
TR: Embossed tape and reel

Embossed carrier tapeTape
3000pcs

TR

The direction is the 1pin of product is at the upper right when you hold

()

reel on the left hand and you pull out the tape on the right hand

1pin

Direction of feed

Reel

Order quantity needs to be multiple of the minimum quantity.

∗

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2011.01 - Rev.

Notes

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which can be obtained from ROHM upon request.

Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.

Great care was taken in ensuring the accuracy of the information specied in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.

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The Products specied in this document are not designed to be radiation tolerant.

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Notice

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R1120

A