ROHM BD2802GU Technical data

A

System LED Drivers for Mobile phones

6LEDs
Illumination

BD2802GU

●Description

The BD2802GU is a RGB LED driver specifically engineered for decoration purposes.This RGB driver incorporates lighting
patterns and illuminates without imposing any load on CPU.This RGB driver is best-suited for illumination using RGB LEDs
and decoration using monochrome LEDs.In addition, this RGB driver has been successfully miniaturized through the use of
a VCSP85H2 (2.8 mm 0.5 mm pitch) chip size package.

●Features

1) RGB LED driver (dual drivers)

- A slope control function is incorporated (allowing dual drivers to be controlled independently).

- Slope control can be implemented using the DC current.

- Two modes “continuous illumination mode” and “illumination single cycle mode” are supported.

- Independent external ON/OFF synchronizing terminals (of dual drivers) are provided.

- Multiple drivers can be used concurrently by using the I

2) Thermal shutdown

3) I2C BUS fast mode support (maximum rate: 400 kHz)

- A device address can be changed via an external pin.

* This driver has not been designed for anti-radiation.
* This document may be altered without prior notice.
* This document does not provide for delivery.

●Absolute Maximum Ratings(Ta=25℃)

2

C address change function and supporting reference clock I/O.

No.11041EAT12

Parameter Symbol Limits Unit

Maximum Applied voltage VMAX 7 V

Power Dissipation Pd 1250

Operating Temperature Range Topr -40 ～ +85 ℃

Storage Temperature Range Tstg -55 ～ +150 ℃

(Note1)Power dissipation deleting is 10.0mW/ oC, when it’s used in over 25 oC.
(It’s deleting is on the board that is ROHM’s standard)

●Recommended Operating Conditions(VBAT≧VIO, Ta=-40～85℃)

Parameter Symbol Limits Unit

VBAT input voltage VBAT 2.7 ～ 5.5 V

VIO pin voltage VIO 1.65 ～ 3.3 V

(Note1)

mW

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●Electrical Characteristics(Unless otherwise specified, Ta=25℃, VBAT=3.6V, VIO=1.8V)

Parameter Symbol

【Circuit Current】

VBAT Circuit current 1 IBAT1 - 0.1 3.0 A RESETB=0V, VIO =0V

VBAT Circuit current 2 IBAT2 - 0.5 3.0 A RESETB=0V, VIO=1.8V

VBAT Circuit current 3 IBAT3 - 0.8 1.2 mA

【LED Driver】

LED current Step ILEDSTP 128 step RGB1 group, RGB2 group

Min. Typ. Max.

Limits

Unit Condition

LED 6Ch ON, ILED=10mA setting
Exclusive of LED current,
RGBISET =120k

Technical Note

LED Maximum setup
curren

LED current accurate ILED 18 20 22 mA

LED current Matching ILEDMT - 5 10 %

LED OFF Leak current ILKL - - 1.0 A

【OSC】

OSC oscillation frequency fosc 0.8 1.0 1.2 MHz

【SDA, SCL】(I2C interface )

L level input voltage VILI -0.3 - 0.25×VIO V

H level input voltage VIHI 0.75×VIO - VBAT+0.3 V

Hysteresis of Schmitt
trigger input

L level output voltage VOLI 0 - 0.3 V SDA pin, IOL=3 mA
Input current linI -10 - 10 A Input voltage = 0.1×VIO～0.9×VIO

【RESETB】(CMOS input pin)

L level input voltage VILR -0.3 - 0.25×VIO V

H level input voltage VIHR 0.75×VIO - VBAT+0.3 V
Input current IinR -10 - 10 A Input voltage = 0.1×VIO～0.9×VIO

【ADDSEL】(CMOS input pin)

L level input voltage VILADD -0.3 - 0.25×VBAT V

H level input voltage VIHADD 0.7 ×VBAT - VBAT+0.3 V
Input current IinADD -10 - 10 A Input voltage = 0.1×VBAT～0.9×VBAT

【RGB1CNT, RGB2CNT】(CMOS input pin with Pull-down resistance)

L level input voltage VILCNT -0.3 - 0.25×VIO V

H level input voltage VIHCNT 0.75×VIO - VBAT+0.3 V

Input current IinCNT - 3.6 10 A Input voltage = 1.8V

【CLKIO(Output)】(CMOS output pin)

L level output voltage VOLCLK - - 0.2 V IOL=1mA

H level output voltage VOHCLK VIO-0.2 - - V IOH=1mA

Output frequency fclk 200 250 300 kHz

【CLKIO (Input)】(CMOS input pin)

L level input voltage VILCLK -0.3 - 0.25×VIO V

H level input voltage VIHCLK 0.75×VIO - VIO+0.3 V

Input current IinCLK - 3.6 10 A Input voltage = 1.8V

IMAX - - 30.48 mA

VhysI 0.05×VIO - - V

RGB1 group, RGB2 group
RGBISET=100k

RGB1 group, RGB2 group,
Terminal voltage =1V
ILED=20mA setting, RGBISET
=120k
RGB1 group, between RGB2 group,
Terminal voltage =1V
ILED=20mA setting

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A

A

●Block Diagram / Application Circuit example

VBAT

VBAT2

VBAT1

1µF/10V

1µF/10V

RESETB

VIO

SCL

SD

I/O

Level

Shift

RGB1CNT

RGB2CNT

ADDSEL

RGBISET

IREF

T3

T1

T2

Fig.3 Block Diagram / Application Circuit example

●Pin Arrangement ［Bottom View］

E

T4

G2LED

B2LED R2LED B1LED R1LED VBAT1

D

C

B

VBAT2

GND1

RGBISE

index

RGB2CNT

T1

1 2 3 4 5

VREF

I2C interface

Digital Control

TSD

T4

RGBGND

RGB1CNT

CLKIO SCL SDA

VIO RESETB

Slope

Control

(RGB1)

Slope

Control

(RGB2)

CLKIO

GND1

GND2

G1LED T3

DDSEL GND2

T2

R1LED

G1LED

B1LED

R2LED

G2LED

B2LED

RGBGND

CLKIO

VBAT

Technical Note

RGB1

RGB2

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●Outside size figure

VCSP85H2 CSP small Package
Size : 2.8mm×2.8mm (Tolerance : ± 0.1mm each side) height 1.0mm max
Ball pitch : 0.5 mm

Technical Note

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Technical Note

●Pin Functions

No Pin No. Pin Name I/O

Input Level

For Power For GND

ESD Diode Functions

1 D5 VBAT1 - - GND Battery is connected A

2 C1 VBAT2 - - GND Battery is connected A

3 A1 T1 - VBAT GND Test Pin (short to GND) S

4 A5 T2 - VBAT GND Test Pin (short to GND) S

5 E5 T3 - VBAT GND Test Pin (short to GND) S

6 E1 T4 - VBAT - Test Pin (short to GND) B

7 A3 VIO - VBAT GND I/O voltage source is connected C

8 A4 RESETB I VBAT GND Reset input (L: RESET, H: RESET cancel) H

9 B5 SDA I/O VBAT GND I2C data input I

10 B4 SCL I VBAT GND I2C clock input H

11 B1 GND1 - VBAT - Ground B

12 C5 GND2 - VBAT - Ground B

13 E3 RGBGND - VBAT - Ground B

14 C2 RGBISET I VBAT GND RGB LED reference current O

15 D4 R1LED I - GND Red LED1 connected E

16 E4 G1LED I - GND Green LED1 connected E

17 D3 B1LED I - GND Blue LED1 connected E

18 D2 R2LED I - GND Red LED2 connected E

19 E2 G2LED I - GND Green LED2 connected E

20 D1 B2LED I - GND Blue LED2 connected E

21 C3 RGB1CNT I VBAT GND

22 A2 RGB2CNT I VBAT GND

RGB1 LED external ON/OFF Synchronism
(L：OFF, H：ON)*

RGB2 LED external ON/OFF Synchronism
(L：OFF, H：ON)*

J

J

23 C4 ADDSEL I VBAT GND I2C device address change terminal R

24 B3 CLKIO I/O VBAT GND Standard clock input-and-output terminal V

* A setup of a register is separately necessary to validate it.

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●Equivalent circuit diagram

A VBATB E

F G

VBAT

C

H

VBAT

VIOVBAT

Technical Note

I

VIO VBAT

J

Q

VBAT VBAT

VIO VBAT

R

VIO VBAT V

VIO

VBATVBAT L

VBATVBAT

N

S

X

VBAT VBAT

VBAT

VBATVBAT

O

VBAT

VBAT U

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Technical Note

●I2C BUS format

The writing operation is based on the I2C slave standard.

・Slave address

A7 A6 A5 A4 A3 A2 A1 R/W

ADDSEL=L 0 0 1 1 0 1 0 0

ADDSEL=H 0 0 1 1 0 1 1 0

Slave address can be changed with the external terminal ADDSEL.

・Bit Transfer

SCL transfers 1-bit data during H. SCL cannot change signal of SDA during H at the time of bit transfer. If SDA changes
while SCL is H, START conditions or STOP conditions will occur and it will be interpreted as a control signal.

SDA

SCL

SDA a state of stability

Data are effective

SDA

：

It can change

・START and STOP condition

When SDA and SCL are H, data is not transferred on the I

2

C- bus. This condition indicates, if SDA changes from H to L
while SCL has been H, it will become START (S) conditions, and an access start, if SDA changes from L to H while SCL
has been H, it will become STOP (P) conditions and an access end.

SDA

SCL

S P

START condition

STOP condition

・Acknowledge

It transfers data 8 bits each after the occurrence of START condition. A transmitter opens SDA after transfer 8bits data, and
a receiver returns the acknowledge signal by setting SDA to L.

DATA OUTPUT
BY TRANSMITTER

DATA OUTPUT
BY RECEIVER

SCL

START condition

S

12 89

not acknowledge

acknowledge

clock pulse for
acknowledgement

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AAA

A

A7 A6 A5 A4 A3 A2A1A

A

A

S

Technical Note

・Writing protocol

A register address is transferred by the next 1 byte that transferred the slave address and the write-in command. The 3rd
byte writes data in the internal register written in by the 2nd byte, and after 4th byte or, the increment of register address is
carried out automatically. However, when a register address turns into the last address, it is set to 00h by the next
transmission. After the transmission end, the increment of the address is carried out.

*1 *1

X X X X X X X

S

R/W=0(write)

from master to slave

from slave to master

register addressslave address

D7D6 D5 D4 D3 D2 D1 D0 D7D6 D5 D4 D3 D2 D1 D0

00

DATA

register address

increment

=acknowledge(SDA LOW)

=not acknowledge(SDA HIGH)
S=START condition
P=STOP condition
*1: Write Timing

DATA

register address

increment

P

●Timing diagram

SDA

BUF

t

SU;DAT

t

t HIGH

CL

LOW

t

HD;STA

t

HD;DAT

S Sr P

t

●Electrical Characteristics(Unless otherwise specified, Ta=25

2

【I

C BUS format】

Parameter Symbol

Min. Typ. Max. Min. Typ. Max.

t

HD;STA

SU;STA

t

t SU;STO

S

o

C, VBAT=3.6V, VIO=1.8V)

Standard-mode Fast-mode

Unit

SCL clock frequency fSCL 0 - 100 0 - 400 kHz

LOW period of the SCL clock tLOW 4.7 - - 1.3 - - s

HIGH period of the SCL clock tHIGH 4.0 - - 0.6 - - s

Hold time (repeated) START condition

After this period, the first clock is generated

Set-up time for a repeated START
condition

tHD;STA 4.0 - - 0.6 - - s

SU;STA 4.7 - - 0.6 - - s

t

Data hold time tHD;DAT 0 - 3.45 0 - 0.9 s

Data set-up time tSU;DAT 250 - - 100 - - ns

Set-up time for STOP condition tSU;STO 4.0 - - 0.6 - - s

Bus free time between a STOP
and START condition

BUF 4.7 - - 1.3 - - s

t

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●Register map

Address W/R

Technical Note

Resister data

D7 D6 D5 D4 D3 D2 D1 D0

Function

00h W

01h W

02h W

03h W

04h W

05h W

06h W

07h W

08h W

09h W

0Ah W

0Bh W

0Ch W

0Dh W

0Eh W

- - CLKMD CLKEN - - - SFTRST

- RGB2MEL RGB2OS RGB2EN - RGB1MEL RGB1OS RGB1EN RBG-LED control

SFRGB1(1) SFRGB1(0) SRRGB1(1) SRRGB1(0) - TRGB1(2) TRGB1(1) TRGB1(0) RGB1-hour setup

- IR11(6) IR11(5) IR11(4) IR11(3) IR11(2) IR11(1) IR11(0) R1 current 1 setup

- IR12(6) IR12(5) IR12(4) IR12(3) IR12(2) IR12(1) IR12(0) R1 current 2 setup

- - - - PR1(3) PR1(2) PR1(1) PR1(0) R1 Wave patturn setup

- IG11(6) IG11(5) IG11(4) IG11(3) IG11(2) IG11(1) IG11(0) G1 current 1 setup

- IG12(6) IG12(5) IG12(4) IG12(3) IG12(2) IG12(1) IG12(0) G1 current 2 setup

- - - - PG1(3) PG1(2) PG1(1) PG1(0) G1 Wave patturn setup

- IB11(6) IB11(5) IB11(4) IB11(3) IB11(2) IB11(1) IB11(0) B1 current 1 setup

- IB12(6) IB12(5) IB12(4) IB12(3) IB12(2) IB12(1) IB12(0) B1 current 2 setup

- - - - PB1(3) PB1(2) PB1(1) PB1(0) B1 Wave patturn setup

SFRGB2(1) SFRGB2(0) SRRGB2(1) SRRGB2(0) - TRGB2(2) TRGB2(1) TRGB2(0) RGB2-hour setup

- IR21(6) IR21(5) IR21(4) IR21(3) IR21(2) IR21(1) IR21(0) R2 current 1 setup

- IR22(6) IR22(5) IR22(4) IR22(3) IR22(2) IR22(1) IR22(0) R2 current 2 setup

Soft Reset clock setup

0Fh W

10h W

11h W

12h W

13h W

14h W

15h W

- - - - PR2(3) PR2(2) PR2(1) PR2(0) R2 Wave patturn

- IG21(6) IG21(5) IG21(4) IG21(3) IG21(2) IG21(1) IG21(0) G2 current 1 setup

- IG22(6) IG22(5) IG22(4) IG22(3) IG22(2) IG22(1) IG22(0) G2 current 2 setup

- - - - PG2(3) PG2(2) PG2(1) PG2(0) G2 Wave patturn setup

- IB21(6) IB21(5) IB21(4) IB21(3) IB21(2) IB21(1) IB21(0) B2 current 1 setup

- IB22(6) IB22(5) IB22(4) IB22(3) IB22(2) IB22(1) IB22(0) B2 current 2 setup

- - - - PB2(3) PB2(2) PB2(1) PB2(0) B2 Wave patturn setup

Input "0” for "-".
Vacancy address may be use for test.
Prohibit to accessing the address that isn’t mentioned and the register for test.

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