ROHM BD26502GUL Technical data

System LED Drivers for Mobile Phones

7x17(Max.) Dot Matrix
LED Display Driver

BD26502GUL

●Description

BD26502GUL is “Matrix LED Driver” that is the most suitable for the cellular phone.
It can control 7x17(119 dot) LED Matrix by internal 7-channel PMOS SWs and 17-channel LED drivers.
It can control the luminance and firefly lighting of the LED matrix by the setting of the internal register.
It supports SPI and I2C interface.
VCSP50L4 (4.1mm
It adopts the very thin CSP package that is the most suitable for the slim phone.

●Features

1) LED Matrix driver (7x17)
・It has 7-channel PMOS SWs and 17-channel current drivers with 1/7 timing driven sequentially.
・Put ON/OFF(for every dot).
・The current drivers can drive 0-20.00mA current with 16 step(for every dot).
・64 steps of the luminance control by PWM (common setting for all dots)
・Continuous (TDMA off ) lighting function for LED14-LED17
・Easy register setting by A/B 2-side map for each dot.

2) Automatic Slope function
・Cycle time, Slope time can be set for each dot.

3) 8-direction automatic scroll function.

4) Interface
・SPI and I
・For I

5) Thermal shutdown

6) Small and thin CSP package
・62pin VCSP50L4(4.1mm

*This chip is not designed to protect itself against radioactive rays.
*This material may be changed on its way to designing.
*This material is not the official specification.

●Absolute Maximum Ratings (Ta=25

Maximum voltage (note2) VMAX 7 V

Maximum voltage (note1) VIOMAX 4.5 V

Power Dissipation (note3) Pd 1550 mW
Operating Temperature Range Topr -40 ~ +85 ℃
Storage Temperature Range Tstg -55 ~ +150 ℃

note1) VIO,RESETB,CE,SDA,SCL,IFMODE,SYNC,CLKIN,CLKOUT,TEST1,TEST2,TEST3,TESTO, DO terminal
note2) Except the above
note3) Power dissipation deleting is 12.4mW/
The power dissipation of the IC has to be less than the one of the package.

●Operating Conditions (VBAT≥VIO, VINSW≥VBAT, Ta=-40~85 oC)

VBAT input voltage VBAT 2.7 ~ 5.5 V

VINSW input voltage VINSW 2.7 ~ 5.5 V

VIO pin voltage VIO 1.65 ~ 3.3 V

□

0.55mm height max), small and thin type chip size package.

2

C BUS FS mode(max 400kHz)Compatibility

2

C mode, I2C Device address is selectable (74h or 75h)

2

0.55mm height max)

o

C)

Parameter Symbol Ratings Unit

o

C , when it’s used in over 25 oC. (ROHM’s standard board has been mounted.)

Parameter Symbol Limits Unit

No.10041EAT01

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2010.02 - Rev.A

BD26502GUL

●Electrical Characteristics (Unless otherwise specified, Ta=25°C, VBAT=3.6V, VINSW=3.6V, VIO=1.8V)

Parameter Symbol

[ Circuit Current ]

VBAT Circuit current 1 IBAT1 - 0 3.0 A RESETB=0V, VIO=0V

VBAT Circuit current 2 IBAT2 - 0.8 5.0 A RESETB=0V, VIO=1.8V

VBAT Circuit current 3 IBAT3 - 2.0 3.5 mA

[ UVLO ]

UVLO Threshold VUVLO - 2.1 2.5 V VBAT falling

UVLO Hysteresis VHYUVLO 50 - - mV

[ LED Driver ] (LED1-17)

Maximum output current ILEDMax - 20.00 - mA LED1-17 ,ISET＝100kΩ

Output current ILED -7.0% 10.67 +7.0% mA I=10.67mA setting, VLED=1V

LED current Matching ILEDMT - - 5 %

Driver pin voltage range VLED 0.2 - VBAT- 1.4 V

Min. Typ. Max.

Limit

Unit Condition

When LED1-17 are active
with default settings.

ILEDMT=
(ILEDMax-ILEDMin)/(ILEDMax+ILEDMin)
I=10.67mA setting, VLED=1V

Technical Note

LED OFF Leak current ILKLED - - 1.0 A

[ PMOS switch ]

Leak current at OFF ILEAKP - - 1.0 A

Resistor at ON RonP - 1.0 -  Isw=170mA, VINSW=4.5V

[ OSC ]

OSC frequency fosc 0.96 1.2 1.44 MHz

[ CE, SYNC, CLKIN, IFMODE ]

L level input voltage VIL1 -0.3 - 0.25 x VIO V

H level input voltage VIH1 0.75 x VIO - VIO +0.3 V

L level input current IIL1 - 0 1 A

H level input current IIH1 - 0 1 A

[ SDA, SCL ]

L level input voltage VIL2 -0.3 - 0.25 x VIO V

H level input voltage VIH2 0.75 x VIO - VIO +0.3 V

Input hysteresis Vhys 0.05 x VIO - - V

L level output voltage
(for SDA pin)

Input current Iin1 -3 - 3 A Input voltage = from (0.1 x VIO) to (0.9 x VIO)

VOL2 0 - 0.3 V At 3mA sink current

[ RESETB ]

L level input voltage VIL3 -0.3 - 0.25 x VIO V

H level input voltage VIH3 0.75 x VIO - VIO +0.3 V

Input current Iin2 - 0 1 A Input voltage = from (0.1 x VIO) to (0.9 x VIO)

[ CLKOUT ]

L level output voltage VOL1 - - 0.4 V IOL=2mA

H level output voltage VOH1 0.75 x VIO - - V IOH=-2mA

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2/39

2010.02 - Rev.A

BD26502GUL

●Power Dissipation (on the ROHM’s Standard Board)

1.8

1550mW

1.6

1.4

W)

1.2

（

1.0

0.8

0.6

Power Dissipation Pd

0.4

0.2

Technical Note

0.0
0 25 50 75 100 125 150

Ta(℃)

Fig.1

Information of the ROHM’s standard board
Material: glass-epoxy
Size : 50mm×58mm×1.75mm(

8th layer)

Wiring pattern figure Refer to after page.

,

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3/39

2010.02 - Rev.A

BD26502GUL

A

●Block Diagram / Application Circuit Example 1

VBAT

VBAT1

VBAT2

VBAT3

10µF

VREF

OSC

100kΩ

ISET

IREF

VIO

1µF

I2C or SPI
selectable

RESETB

CE

SD

SCL

IFMODE

SYNC

CLKIN

CLKOUT

I/O

Level

Shift

GND1

GND2

GND3

GND4

GND5

GND6

GND7

GND8

GND9

GND10

GND11

TEST1

TEST2

TEST3

TEST4

Fig.2 Block Diagram / Application Circuit example 1

Enable

SPI / I2C
interface

Digital Control

TEST5

TESTO

1.33mA step

DO

Logic

TDMA

20.00mA/ch

LEDGND1

PWM

LEDGND2

T06

T05

T04

T03

T02

T01

T00

TDMA

TDMA

TDMA

TDMA

TDMA

TDMA

TDMA

TDMA

TDMA

TDMA

TDMA

TDMA

TDMA

TDMA

TDMA

TDMA

TDMA

LEDGND3

Technical Note

VINSW

VINSW1

VINSW2

VINSW3

SW7

SW6

SW5

SW4

SW3

SW2

SW1

LED17

LED16

LED15

LED14

LED13

LED12

LED11

LED10

LED9

LED8

LED7

LED6

LED5

LED4

LED3

LED2

LED1

LEDGND4

10F

7×17

Dot Matrix Unit

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2010.02 - Rev.A

BD26502GUL

A

●Block Diagram / Application Circuit Example 2

VBAT

VBAT1

VBAT2

VBAT3

10µF

VREF

OSC

100kΩ

ISET

IREF

VIO

1µF

I2C or SPI
selectable

RESETB

CE

SD

SCL

IFMODE

SYNC

CLKIN

CLKOUT

I/O

Level

Shift

GND1

GND2

GND3

GND4

GND5

GND6

GND7

GND8

GND9

GND10

GND11

TEST1

TEST2

TEST3

TEST4

Fig.3 Block Diagram / Application Circuit example 2

Enable

SPI / I2C
interface

Digital Control

TEST5

TESTO

1.33mA step

DO

Logic

TDMA

20.00mA/ch

LEDGND1

PWM

LEDGND2

T06

T05

T04

T03

T02

T01

T00

TDMA

TDMA

TDMA

TDMA

TDMA

TDMA

TDMA

TDMA

TDMA

TDMA

TDMA

TDMA

TDMA

TDMA

TDMA

TDMA

TDMA

LEDGND3

Technical Note

VINSW

VINSW1

VINSW2

VINSW3

SW7

SW6

SW5

SW4

SW3

SW2

SW1

LED17

LED16

LED15

LED14

LED13

LED12

LED11

LED10

LED9

LED8

LED7

LED6

LED5

LED4

LED3

LED2

LED1

LEDGND4

10F

7×13

Dot Matrix Unit

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2010.02 - Rev.A

BD26502GUL

●Pin Arrangement ［Bottom View］

TEST4 LED11 LED12 GND1 LED15 LED16 LED17 TESTO

H

LED9 LED10 LED13 LED14 GND2 CLKOUT CE SDA

G

LED8 ISET LEDGND3 LEDGND4 TEST1 IFMODE SCL VIO

F

LEDGND2 LED7 VBAT1 VBAT2 RESETB CLKIN SYNC DO

E

LED5 LED6 LED4 SW3 SW2 SW1 VINSW1

D

Technical Note

LED3 LEDGND1

C

LED2 LED1 GND4 GND5 GND6 SW6 SW7 VINSW3

B

TEST3 VBAT3 GND7 GND8 GND9 GND10 GND11 TEST5

A

1 2 3 4 5 6 7 8

Total 62 Balls

GND3 TEST2 SW5 SW4 VINSW2

index

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2010.02 - Rev.A

BD26502GUL

●Package

62pin VCSP50L4 CSP small package
SIZE : 4.10mm
Height : 0.55mm max
A ball pitch : 0.5 mm

□

Technical Note

*INDEX POST has No Solder Ball

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7/39

2010.02 - Rev.A

BD26502GUL

●Pin Functions

Ball

No

1 A1 TEST3 I 94k GND VIO GND Test input pin 3 E

2 A2 VBAT3 - - VBAT - GND Battery is connected A

3 A3 GND7 - - GND VBAT - Ground B

4 A4 GND8 - - GND VBAT - Ground B

5 A5 GND9 - - GND VBAT - Ground B

6 A6 GND10 - - GND VBAT - Ground B

7 A7 GND11 - - GND VBAT - Ground B

8 A8 TEST5 I - GND VINSW GND Test input pin 5 I

9 B1 LED2 O - GND - GND LED2 driver output K

10 B2 LED1 O - GND - GND LED1 driver output K

11 B3 GND4 - - GND VBAT - Ground B

12 B4 GND5 - - GND VBAT - Ground B

13 B5 GND6 - - GND VBAT - Ground B

14 B6 SW6 O - VINSW VINSW GND P-MOS SW6 output C

15 B7 SW7 O - VINSW VINSW GND P-MOS SW7 output C

16 B8 VINSW3 - - VINSW - GND Power supply for SW1-7 A

17 C1 LED3 O - GND - GND LED3 driver output K

18 C2 LEDGND1 - - GND VBAT - Ground B

19 C4 GND3 - - GND VBAT - Ground B

20 C5 TEST2 I 94k GND VIO GND Test input pin 2 E

21 C6 SW5 O - VINSW VINSW GND P-MOS SW５ output C

22 C7 SW4 O - VINSW VINSW GND P-MOS SW4 output C

23 C8 VINSW2 - - VINSW - GND Power supply for SW1-7 A

24 D1 LED5 O - GND - GND LED5 driver output K

25 D2 LED6 O - GND - GND LED6 driver output K

26 D3 LED4 O - GND - GND LED4 driver output K

27 D5 SW3 O - VINSW VINSW GND P-MOS SW3 output C

28 D6 SW2 O - VINSW VINSW GND P-MOS SW2 output C

29 D7 SW1 O - VINSW VINSW GND P-MOS SW1output C

30 D8 VINSW1 - - VINSW - GND Power supply for SW1-7 A

31 E1 LEDGND2 - - GND VBAT - Ground B

32 E2 LED7 O - GND - GND LED7 driver output K

33 E3 VBAT1 - - VBAT - GND Battery is connected A

34 E4 VBAT2 - - VBAT - GND Battery is connected A

35 E5 RESETB I - GND VIO GND Reset input pin (L: reset, H: reset cancel) D

36 E6 CLKIN I - GND VIO GND External CLK input pin D

37 E7 SYNC I - GND VIO GND External synchronous input pin D

38 E8 DO O - OPEN VIO GND Test output pin2 G

39 F1 LED8 O - GND - GND LED8 driver output K

40 F2 I SET I - OPEN VBAT GND LED Constant Current Driver Current setting pin J

41 F3 LEDGND3 - - GND VBAT - Ground B

42 F4 LEDGND4 - - GND VBAT - Ground B

43 F5 TEST1 I 94k GND VIO GND Test input pin 1 E

44 F6 IFMODE I - GND VIO GND I2C/SPI select pin (L: I2C, H: SPI) D

45 F7 SCL I - GND VIO GND SPI, I2C CLK input pin D

Pin Name I/O

No.

down

Pull

Unused

Terminal

setting

ESD Diode

For

Power

For

Ground

Functions

Technical Note

Equivalent

Circuit

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2010.02 - Rev.A

BD26502GUL

Ball

No

46 F8

47 G1

48 G2

49 G3

50 G4

51 G5

52 G6

53 G7 CE I - GND VIO GND

54 G8

55 H1

56 H2

57 H3

58 H4

59 H5

60 H6

61 H7

62 H8

* Please connect the unused LED pins to the ground.
* It is prohibition to set the registers for unused LED.

Total 62 pins

●Equivalent Circuit

A

Pin Name I/O

No.

VIO - - VIO - GND

LED9 O - GND - GND

LED10 O - GND - GND

LED13 O - GND - GND

LED14 O - GND - GND

GND2 - - GND VBAT -

CLKOUT O - OPEN VIO GND

SDA I/O - GND VIO GND

TEST4 I - GND VBAT GND

LED11 O - GND - GND

LED12 O - GND - GND

GND1 - - GND VBAT -

LED15 O - GND - GND

LED16 O - GND - GND

LED17 O - GND - GND

TESTO O - OPEN VIO GND

down

B

Pull

Unused

Terminal

setting

VBAT

ESD Diode

For

Power

For

Ground

Technical Note

Functions

I/O Power supply is connected

LED9 driver output

LED10 driver output

LED13 driver output

LED14 driver output

Ground

Reference CLK output pin
SPI enable pin(H:Enable), or

2

I

C slave address selection (L: 74h, H: 75h) D

SPI DATA input / I2C DATA input-output pin

Test input pin 4

LED11 driver output

LED12 driver output

Ground

LED15 driver output

LED16 driver output

LED17 driver output

Test output pin1

VINSWCVINSW

D

VIO VIO

Equivalent

Circuit

A

K

K

K

K

B

G

F

H

K

K

B

K

K

K

G

E

I

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VIO VIO

VINSW

F

J

VBAT

VIOVIO

VIOG

VIO

H

VBAT

K

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2010.02 - Rev.A

BD26502GUL

●Serial Interface

1. SPI format

・When IFMODE is set to “H”, it can interface with SPI format.
・The serial interface is four terminals (serial clock terminal (SCL), serial data input terminal (SDA), and chip

selection input terminal (CE)).

(1)Write operation

・Data is taken into an internal shift register with rising edge of CLK. (Max of the frequency is 13MHz.)
・The receive data becomes enable in the “H” section of CE. (Active “H”.)
・The transmit data is forwarded (with MSB-First) in the order of write command “0”(1bit), the control register address

(7bit) and data (8bit).

CE

SCL

Technical Note

SDA

W A6 A5 A4 A3 A2 A1 A0 D4 D3 D2 D1 D0 D7 D6 D5

Fig.4 Writing format

(2)Timing diagram

CE

SCL

SDA

tcss tscyc

twhc

tss tsh

twlc

tcgh

tcsw

Fig.5 Timing diagram (SPI format)

(3) Electrical Characteristics (Unless otherwise specified, Ta=25°C, VBAT=3.6V, VINSW=3.6V, VIO=1.8V)

Parameter Symbol

Min Typ Max

Limit

Unit Condition

SCL cycle time tscyc 76 - - ns

H period of SCL cycle Twhc 35 - - ns

L period of SCL cycle twlc 35 - - ns

SDA setup time tss 38 - - ns

SDA hold time tsh 38 - - ns

Read and Write interval tcsw 38 - - ns

CE setup time tcss 55 - - ns

CE hold time tcgh 55 - - ns

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10/39

2010.02 - Rev.A

BD26502GUL

2. I2C BUS format

When IFMODE is set to “L”, it can interface with I2C BUS format.

(1) Slave address

CE A7 A6 A5 A4 A3 A2 A1 R/W

L 1 1 1 0 1 0 0

H 1 1 1 0 1 0 1

(2) Bit Transfer

SCL transfers 1-bit data during H. During H of SCL, SDA cannot be changed at the time of bit transfer. If SDA changes
while SCL is H, START conditions or STOP conditions will occur and it will be interpreted as a control signal.

(3) START and STOP condition

When SDA and SCL are H, data is not transferred on the I
while SCL has been H, it will become START (S) conditions, and an access start, if SDA changes from L to H while SCL
has been H, it will become STOP (P) conditions and an access end.

SDA

SCL

SDA

SDA a state of stability

Data are effective

Fig.6 Bit transfer (I

Technical Note

0

SDA

：

It can change

2

C format)

2

C- bus. This condition indicates, if SDA changes from H to L

(4) Acknowledge

SCL

S P

START condition

Fig.7 START/STOP condition (I

2

STOP condition

C format)

It transfers data 8 bits each after the occurrence of START condition. A transmitter opens SDA after transfer 8bits data,
and a receiver returns the acknowledge signal by setting SDA to L.

DATA OUTPUT
BY TRANSMITTER

DATA OUTPUT
BY RECEIVER

SCL

START condition

S

12 89

Fig.8 Acknowledge (I

2

C format)

not acknowledge

acknowledge

clock pulse for
acknowledgement

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11/3 9

2010.02 - Rev.A

BD26502GUL

A A

A

A

A7 A6 A5A4A3A2A1A

A

A

S

(5) Writing protocol

A register address is transferred by the next 1 byte that transferred the slave address and the write-in command. The
3rd byte writes data in the internal register written in by the 2nd byte, and after 4th byte or, the increment of register
address is carried out automatically. However, when a register address turns into the last address (77h), it is set to 00h
by the next transmission. After the transmission end, the increment of the address is carried out.

Technical Note

*1 *1

X X X X X X X

S

R/W=0(write)

from master to slave

from slave to master

register addressslave address

(6) Timing diagram

SDA

SU;DAT

t

t HIGH

CL

LOW

t

HD;STA

t

HD;DAT

S Sr P

t

Fig.9 Timing diagram (I2C format)

(7) Electrical Characteristics(Unless otherwise specified, Ta=25

Parameter Symbol

2

【I

C BUS format】

D7D6D5D4D3D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

00

DATA

register address

increment

=acknowledge(SDA LOW)

=not acknowledge(SDA HIGH)
S=START condition
P=STOP condition
*1: Write Timing

t

HD;STA

SU;STA

t

o

C, VBAT=3.6V, VINSW=3.6V, VIO=1.8V)

t SU;STO

DATA

BUF

t

S

Standard-mode Fast-mode

Min. Typ. Max. Min. Typ. Max.

P

register address

increment

Unit

SCL clock frequency fSCL 0 - 100 0 - 400 kHz

LOW period of the SCL clock tLOW 4.7 - - 1.3 - - s

HIGH period of the SCL clock tHIGH 4.0 - - 0.6 - - s

Hold time (repeated) START condition
After this period, the first clock is generated

HD;STA 4.0 - - 0.6 - - s

t

Set-up time for a repeated START condition tSU;STA 4.7 - - 0.6 - - s

Data hold time tHD;DAT 0 - 3.45 0 - 0.9 s

Data set-up time tSU;DAT 250 - - 100 - - ns

Set-up time for STOP condition tSU;STO 4.0 - - 0.6 - - s

Bus free time between a STOP
and START condition

t

BUF 4.7 - - 1.3 - - s

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2010.02 - Rev.A