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R&S®TS-PFG
Function Generator
User Manual
(;ÂVD<)
1152382012
Version 12
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This manual describes the following R&S®TS‑PFG models:
●
R&S®TS‑PFG (1157.9610.02)
© 2021 Rohde & Schwarz GmbH & Co. KG
Mühldorfstr. 15, 81671 München, Germany
Phone: +49 89 41 29 - 0
Email: info@rohde-schwarz.com
Internet: www.rohde-schwarz.com
Subject to change – data without tolerance limits is not binding.
R&S® is a registered trademark of Rohde & Schwarz GmbH & Co. KG.
Trade names are trademarks of the owners.
1152.3820.12 | Version 12 | R&S®TS-PFG
The following abbreviations are used throughout this manual: R&S®TS‑PFG is abbreviated as R&S TS‑PFG.
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1
Risk of injury and instrument damage
The instrument must be used in an appropriate manner to prevent
personal injury or instrument damage.
● Do not open the instrument casing.
● Read and observe the "Basic Safety Instructions" delivered as
printed brochure with the instrument.
● Read and observe the safety instructions in the following sections.
Note that the data sheet may specify additional operating conditions.
● Keep the "Basic Safety Instructions" and the product documentation
in a safe place and pass them on to the subsequent users.
Riesgo de lesiones y daños en el instrumento
El instrumento se debe usar de manera adecuada para prevenir
descargas eléctricas, incendios, lesiones o daños materiales.
● No abrir la carcasa del instrumento.
● Lea y cumpla las "Instrucciones de seguridad elementales"
suministradas con el instrumento como folleto impreso.
● Lea y cumpla las instrucciones de seguridad incluidas en las
siguientes secciones. Se debe tener en cuenta que las
especificaciones técnicas pueden contener condiciones adicionales
para su uso.
● Guarde bien las instrucciones de seguridad elementales, así como
la documentación del producto, y entréguelas a usuarios
posteriores.
Safety Instructions
Instrucciones de seguridad
Sicherheitshinweise
Consignes de sécurité
1171.1307.42 - 05
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2
Gefahr von Verletzungen und Schäden am Gerät
Betreiben Sie das Gerät immer ordnungsgemäß, um elektrischen
Schlag, Brand, Verletzungen von Personen oder Geräteschäden zu
verhindern.
● Öffnen Sie das Gerätegehäuse nicht.
● Lesen und beachten Sie die "Grundlegenden Sicherheitshinweise",
die als gedruckte Broschüre dem Gerät beiliegen.
● Lesen und beachten Sie die Sicherheitshinweise in den folgenden
Abschnitten; möglicherweise enthält das Datenblatt weitere
Hinweise zu speziellen Betriebsbedingungen.
● Bewahren Sie die "Grundlegenden Sicherheitshinweise" und die
Produktdokumentation gut auf und geben Sie diese an weitere
Benutzer des Produkts weiter.
Risque de blessures et d'endommagement de l'appareil
L'appareil doit être utilisé conformément aux prescriptions afin d'éviter
les électrocutions, incendies, dommages corporels et matériels.
● N'ouvrez pas le boîtier de l'appareil.
● Lisez et respectez les "consignes de sécurité fondamentales"
fournies avec l’appareil sous forme de brochure imprimée.
● Lisez et respectez les instructions de sécurité dans les sections
suivantes. Il ne faut pas oublier que la fiche technique peut indiquer
des conditions d’exploitation supplémentaires.
● Gardez les consignes de sécurité fondamentales et la
documentation produit dans un lieu sûr et transmettez ces
documents aux autres utilisateurs.
1171.1307.42 - 05
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R&S®TS-PFG
1.1 General...........................................................................................................................7
1.2 Features......................................................................................................................... 8
1.3 Possible Applications...................................................................................................8
1.4 Safety Instructions........................................................................................................9
4.1 R&S TS-PFG................................................................................................................ 14
4.1.1 Mechanical Design........................................................................................................14
Contents
Contents
1 Use...........................................................................................................7
2 View.......................................................................................................10
3 Block Diagrams.................................................................................... 11
4 Design................................................................................................... 14
4.1.2 Interfaces...................................................................................................................... 14
4.1.3 Display Elements.......................................................................................................... 15
4.2 R&S TS‑PDC................................................................................................................ 16
4.2.1 Mechanical Design........................................................................................................16
4.2.2 Interfaces...................................................................................................................... 17
4.2.3 Display Elements.......................................................................................................... 18
4.2.3.1 R&S TS‑PDC up to Version 2.0 (R&S No. 1157.9804.02)............................................ 18
4.2.3.2 R&S TS‑PDC from Version 2.0 (R&S No. 1157.9804.12)............................................. 18
5 Functional Description........................................................................ 19
5.1 R&S TS-PFG................................................................................................................ 19
5.1.1 Overview....................................................................................................................... 19
5.1.1.1 Analog Hardware of Module..........................................................................................19
5.1.1.2 Synchronization.............................................................................................................19
5.1.1.3 Special Features for Standard Waveforms................................................................... 20
5.1.2 Relay Matrix and Analog Bus........................................................................................20
5.1.3 Cascading of Both Channels.........................................................................................21
5.1.4 Output of Standard Waveforms.....................................................................................22
5.1.4.1 Waveforms.................................................................................................................... 23
5.1.4.2 Configuration of a Standard Waveform.........................................................................23
5.1.5 Output of Arbitrary Waveforms......................................................................................23
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R&S®TS-PFG
5.1.5.1 Creation of Waveform................................................................................................... 24
5.1.5.2 Configuration of an Arbitrary Waveform........................................................................24
5.1.5.3 Addition of Markers....................................................................................................... 25
5.1.5.4 Filtering of Output Signal...............................................................................................25
5.1.5.5 Download optimization.................................................................................................. 25
5.1.6 Output of Arbitrary Sequences......................................................................................26
5.1.6.1 Creation of a Sequence................................................................................................ 26
5.1.6.2 Configuration of an Arbitrary Sequence........................................................................ 26
5.1.6.3 Marker Signals in Arbitrary Sequences.........................................................................27
5.1.6.4 Filtering of Output Signal...............................................................................................27
5.1.6.5 Improved Performance from Using Arbitrary Sequences..............................................27
5.1.7 Triggering...................................................................................................................... 28
5.1.8 Operating Mode............................................................................................................ 29
Contents
5.1.8.1 Continuous Mode.......................................................................................................... 29
5.1.8.2 Burst Mode....................................................................................................................30
5.1.9 Fixing of DC Offset Range............................................................................................ 30
5.1.10 Dynamic Adaptation of Waveform Amplitude................................................................31
6 Startup...................................................................................................33
6.1 Installation of R&S TS-PFG Module...........................................................................33
6.2 Installation of R&S TS‑PDC Module.......................................................................... 33
7 Software................................................................................................35
7.1 Driver Software............................................................................................................35
7.2 Soft Panel.....................................................................................................................35
7.3 R&S TS-PFG Programming Example........................................................................ 37
8 Self‑Test................................................................................................ 48
8.1 LED Test.......................................................................................................................48
8.2 Power‑On Test............................................................................................................. 48
8.3 TSVP Self‑Test.............................................................................................................49
9 Interface Description........................................................................... 50
9.1 R&S TS-PFG................................................................................................................ 50
9.1.1 Connector X10.............................................................................................................. 50
9.1.2 Connector X20.............................................................................................................. 52
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R&S®TS-PFG
9.1.3 Connector X30.............................................................................................................. 53
9.1.4 Connector X1 (cPCI Bus)..............................................................................................54
9.2 R&S TS‑PDC................................................................................................................ 55
9.2.1 Connector X20.............................................................................................................. 55
10 Specifications.......................................................................................57
Contents
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R&S®TS-PFG
Contents
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R&S®TS-PFG
1.1 General
Use
General
1 Use
This manual describes the function and operation of the ROHDE&SCHWARZ function
generator module R&S TS-PFG for use in the test system versatile platform R&S CompactTSVP. The hardware is implemented as a CompactPCI board that occupies only
one slot on the front side of the TSVP. The associated R&S TS‑PDC rear I/O module
(DC/DC converter module) is inserted at the same slot on the rear side.
The ROHDE&SCHWARZ function generator module R&S TS-PFG can be used wherever the simulation of single‑channel or multichannel, analog output signals is required.
The floating output of the signals prevents any interference on the device under test
(DUT), thereby ensuring that the application can be simulated under conditions that are
very close to actual.
The high dynamic range of the output voltage and the high sample rate allow output
signals with an extremely high resolution to be achieved. The module can generate
standard signal forms, such as sine‑wave, square‑wave,triangular and ramp, as well as
arbitrary signal forms. These can be output continuously or in pulsed mode.
Commercially available waveform editors can be used for defining the signal curves
(e.g. Analog Waveform Editor from National Instruments). Comprehensive trigger
options with local trigger and marker signals or the PXI trigger bus enable synchronization with other R&S measurement, stimulus or switch modules and PXI modules from
other manufacturers.
A LabWindows IVI‑C software driver is available for the general waveform generation
functions of the R&S TS-PFG module. Other hardware functions are controlled using
specific extensions of the driver. As is usual for a LabWindows driver, function panels
and online help are available.
The R&S TS-PFG module is inserted into the front of the R&S CompactTSVP chassis.
It uses the cPCI/PXI standard. The front connector is flush with the front panel of the
R&S CompactTSVP chassis and is used for connecting DUTs or measurement sensors. At the back, the R&S TS-PFG module is connected to the cPCI control bus and
the PXI trigger bus. As an alternative to the front connector, analog measurement signals can be tapped at the analog measurement bus of the R&S CompactTSVP.
The voltage supply of the R&S TS-PFG is made available to the module via the
R&S TS‑PDC rear I/O module with DC/DC converters.
The R&S TS-PFG module can only be used in the R&S CompactTSVP (TSVP = Test
System Versatile Platform).
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R&S®TS-PFG
1.2 Features
Possible Applications
Features of the R&S TS-PFG function generator module
●
2‑channel arbitrary function generator (both channels can be operated as independent generators)
●
Floating signal generation (max. 125 V working voltage)
●
Resolution (16 bit)
●
Sample rate up to 25 Msample/s per channel
●
Output voltage up to 40 Vpp per channel
(channels can be cascaded)
●
Output current up to ±250 mA per channel
●
Memory depth of 1 Msample per channel
●
Waveform linking and looping
●
Sample‑synchronous marker signal can be configured
●
Synchronization via PXI trigger bus
●
Channels can be optionally switched to 8 analog buses/outputs
●
Self‑test capability in conjunction with R&S TS‑PSAM module
●
LabWindows IVI‑C driver available
●
Used in R&S CompactTSVP
Use
1.3 Possible Applications
The R&S TS-PFG function generator module can be used for tasks such as the following:
●
Generation of sine‑wave, square‑wave, ramp and triangular signals
●
Generation of concatenated waveforms of any type
●
Sensor simulation (floating stimulation)
●
Generation of arbitrary signals
●
Stimulation of low‑frequency digital signals with variable level
●
Programmable clock‑pulse generators
●
Generation of DUT supply voltages
If the application requires additional stimulus channels, this can be achieved by adding
further R&S TS-PFG function generator modules and synchronizing them via the PXI
trigger bus.
The analog bus and a R&S switching module (e.g. R&S TS‑PMB) can be used to multiplex the output signals over a very high number of DUT pins.
Complex test operations can be performed using the digital marker signal which is output sample‑synchronously with the analog signal. Using a switchable connection of the
two output channels, the output voltage range can be doubled and/or DC signals generated with up‑modulated AC signals.
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R&S®TS-PFG
1.4 Safety Instructions
Use
Safety Instructions
The extremely compact design with primary matrix and signal conditioning occupies
just a single CompactPCI/PXI slot width, making it possible to create space‑saving yet
very powerful measurement and stimulus systems.
A self-test of the R&S TS-PFG function generator can be run in conjunction with the
R&S TS‑PSAM analog measurement and stimulus module. Diagnostic LEDs in the
front panel indicate the current status of the module.
Damage to device or individual modules due to excessive operating voltage
The R&S CompactTSVP/R&S PowerTSVP production test platform and the
R&S TS‑PFG function generator module are designed for operating voltages up to
125 V. If this operating voltage is exceeded, the device and the individual modules can
be damaged.
It is also important to ensure that this limit is not exceeded at any time, even after summation of voltages, between floating measurement or stimulus instruments and GND.
Risk of injury from electric voltage
To prevent injury caused by electric voltage, it is important to observe the requirements
specified in EN61010‑1 concerning operation with "hazardous active" voltages.
Figure 1-1 shows a number of typical permissible voltage configurations between the
analog buses and ground.
Figure 1-1: Permissible voltages on analog bus lines
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R&S®TS-PFG
View
2 View
Figure 2-1 shows the R&S TS-PFG function generator module without the associated
R&S TS‑PDC rear I/O module. The R&S TS‑PDC rear I/O module is shown in Fig-
ure 2-2.
Figure 2-1: View of R&S TS‑PFG module
Figure 2-2: View of R&S TS‑PDC rear I/O module
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R&S®TS-PFG
Block Diagrams
3 Block Diagrams
The following section provides a functional block diagram of the R&S TS-PFG module
as well as a detailed block diagram.
Figure 3-1 shows the functional block diagram of the R&S TS-PFG module.
Figure 3-2 shows a detailed block diagram of the R&S TS-PFG module.
Figure 3-1: Functional block diagram of R&S TS-PFG module
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R&S®TS-PFG
Block Diagrams
Figure 3-2: Detailed block diagram of R&S TS-PFG module
Figure 3-3: Block diagram of R&S TS‑PDC rear I/O module
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R&S®TS-PFG
Block Diagrams
Figure 3-4: R&S TS-PFG and R&S TS‑PDC modules in R&S CompactTSVP
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R&S®TS-PFG
4.1 R&S TS-PFG
4.1.1 Mechanical Design
Design
R&S TS-PFG
4 Design
The R&S TS-PFG module is designed as a long cPCI plug‑in module for mounting in
the front of the R&S CompactTSVP.
The height of the module's board is 3 HU (134 mm). The front panel is provided with a
locating pin to ensure that the module is correctly inserted into the R&S CompactTSVP.
The module is secured using the two fastening screws on the front panel.
The front interface X10 is used for connecting DUTs. Interface X30 connects the R&S
TS-PFG module to the analog bus backplane in the R&S CompactTSVP. Interfaces
X20/X1 connect the R&S TS-PFG module to the cPCI backplane/PXI control backplane.
Figure 4-1: Layout of interfaces on R&S TS-PFG module
4.1.2 Interfaces
Table 4-1: Interfaces on R&S TS-PFG
Designation Use
X1 cPCI bus backplane
X10 Device under test (DUT)
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R&S®TS-PFG
4.1.3 Display Elements
Design
R&S TS-PFG
Designation Use
X20 Backplane extension (PXI), rear I/O
X30 Analog bus
A detailed interface description with signal assignment to the connectors can be found
in Chapter 9, "Interface Description", on page 50.
On the front panel of the R&S TS-PFG are three light emitting diodes (LEDs) which
have the following meaning:
Figure 4-2: LED indicators of R&S TS-PFG
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R&S®TS-PFG
4.2 R&S TS‑PDC
Design
R&S TS‑PDC
Table 4-2: Display elements of R&S TS-PFG
LED Description
ERR (red) Error condition:
Lights up if, after the supply voltage is switched on,
a fault is detected on the R&S TS‑PFG during the
power‑on test.
COM (yellow) Communications:
Lights up when data is being exchanged via the
interface.
PWR (green) Supply voltage:
Lights up when all the necessary supply voltages
are present.
4.2.1 Mechanical Design
The R&S TS‑PDC module is a rear I/O module for mounting in the back of the
R&S CompactTSVP. The height of the module's board is 3 HU (134 mm). The module
is secured using the two fastening screws on the front panel. Connector X20 connects
the R&S TS‑PDC module to the backplane in the R&S CompactTSVP.
Damage to R&S TS‑PFG and R&S TS‑PDC modules
Incorrect connection of the R&S TS‑PFG and R&S TS‑PDC modules to the backplane
of the R&S CompactTSVP can result in damage to the two modules.
The R&S TS‑PDC module must always be inserted into the corresponding rear I/O slot
of the R&S TS-PFG module.
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R&S®TS-PFG
Design
R&S TS
‑PDC
Figure 4-3: Connectors and LEDs on R&S TS‑PDC module
4.2.2 Interfaces
Table 4-3: Interfaces on R&S TS
Designation Use
X20 Backplane extension (rear I/O)
A detailed interface description with signal assignment to the connector can be found
in Chapter 9, "Interface Description", on page 50.
‑
PDC
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R&S®TS-PFG
4.2.3 Display Elements
4.2.3.1 R&S TS‑PDC up to Version 2.0 (R&S No. 1157.9804.02)
4.2.3.2 R&S TS‑PDC from Version 2.0 (R&S No. 1157.9804.12)
Design
R&S TS‑PDC
The current status of the module is indicated by means of 8 green LEDs, whereby
each LED indicates the presence of an output voltage.
If the module is operating properly, all 8 LEDs must light up simultaneously.
The current status of the module is indicated by means of 10 LEDs.
In the switched‑on state, the green PWR LED indicates the power-on state. If the module is operating properly, the 8 green LEDs for each generated output voltage also light
up.
In the case of overload or overtemperature, the module shuts down automatically. The
fault is indicated by means of the red ERR LED.
Figure 4-4: LEDs on R&S TS‑PDC module from version 2.0
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R&S®TS-PFG
5.1 R&S TS-PFG
5.1.1 Overview
5.1.1.1 Analog Hardware of Module
Functional Description
R&S TS-PFG
5 Functional Description
Two independent channels each with its own voltage supply are used to output the
analog stimulus values. Both output channels are identical structure.
Each channel has a fast D/A converter downstream of which three lowpass filters and
a differential power amplifier with four level ranges are connected.
The ground‑referenced control unit (FPGA) transmits the digital data at the maximum
possible data rate via an insulated parallel interface. The FPGA updates the D/A converter for each individual channel according to the selected sample rate.
All of the necessary digital control signals (system clock, update signal, gain setting)
are generated by the FPGA and also passed to the analog section via isolation transformers.
The voltage supply of the analog front end is made available to the module via a rear
I/O module (R&S TS‑PDC) with DC/DC converters.
The analog signals are tapped via matrix relays at the front connector (X10) of the
module and fed to the analog measurement bus of the R&S CompactTSVP via further
coupling relays. Fixed current limiting is provided.
Higher output voltages can be generated by cascading the individual, electrically isolated channels.
5.1.1.2 Synchronization
Triggers can be received to allow synchronization with other devices, especially with
analyzer modules or digital measurement modules.
The trigger signals of the PXI trigger bus and two ground‑referenced trigger input signals are provided for this purpose.
In addition, a phase‑synchronous marker signal can be generated when arbitrary
waveforms or arbitrary sequences are output.
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R&S®TS-PFG
5.1.1.3 Special Features for Standard Waveforms
5.1.2 Relay Matrix and Analog Bus
Functional Description
R&S TS-PFG
The standard waveforms (sine‑wave, square‑wave, triangular, ramp) can be generated
using the R&S TS-PFG module to match the frequency extremely precisely. In the
case of waveforms with steep edges (square‑wave, ramp), however, shifts may occur
at the edges that are not visible with the other waveforms. The shift (jitter) corresponds
to one sampling interval, i.e. 40 ns at signal frequencies above 1 kHz.
For jitter‑free signal generation, the signal frequency must be selected such that the
period duration or the pulse width (in the case of a square wave) is an integer multiple
of 40 ns, or the signal must be programmed as an arbitrary waveform.
Using a full matrix, the two stimulus channels can be optionally connected to a local
analog bus (8‑line LABx).
Connection to the analog bus of the R&S CompactTSVP is possible via separate bus
coupling relays.
Both generator channels can be connected to ground.
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R&S®TS-PFG
Functional Description
R&S TS-PFG
Example:
●
Channel 1 of the R&S TS-PFG is connected to the local analog bus via matrix
relays.
●
The coupling relays are also used to connect the local analog bus lines to the analog bus of the R&S CompactTSVP.
●
A ground connection is set up on channel 1.
The corresponding function calls of the IVI‑C device driver are:
●
rspfg_Connect to connect the matrix relays
●
rspfg_ConfigureCoupling to connect the coupling relays
●
rspfg_ConfigureGround to connect the ground relay
5.1.3
Figure 5-1: Example showing relay connection on R&S TS-PFG channel 1
Cascading of Both Channels
Both channels of the R&S TS-PFG can be cascaded using one relay. In this way, it is
possible to place the sum of both channel voltages on the analog bus.
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R&S®TS-PFG
Functional Description
R&S TS-PFG
Example:
The high output of channel 2 is connected to the low output of channel 1.
The corresponding function call of the IVI‑C device driver is:
rspfg_Connect(vi, “CH1_LO“, “CH2_HI“);.
Figure 5-2: Example showing cascading of both R&S TS-PFG channels
5.1.4 Output of Standard Waveforms
In order to configure and output standard waveforms, the R&S TS-PFG must be
switched to the corresponding mode. For this purpose, the parameter
RSPFG_VAL_OUTPUT_FUNC is passed to the IVI‑C function
rspfg_ConfigureOutputMode. This affects both channels. If only one channel is to
be configured, the rspfg_ConfigureOutputModeChannel function must be used.
Opening the device driver or resetting the driver causes both channels of the R&S TSPFG to be set to RSPFG_VAL_OUTPUT_FUNC mode.
Standard waveforms can either be output continuously, or the number of signal periods
after which output of the signal stops can be configured. For further information, see
Chapter 5.1.8, "Operating Mode", on page 29.
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R&S®TS-PFG
5.1.4.1 Waveforms
5.1.4.2 Configuration of a Standard Waveform
Functional Description
R&S TS-PFG
The following standard waveforms can be generated using the R&S TS-PFG:
●
Sine‑wave
●
Triangular
●
Square‑wave
●
Ramp (rising)
●
Ramp (falling)
A DC voltage offset can be added to all waveforms. It is also possible to output a constant DC voltage only.
The following parameters can be set using the
rspfg_ConfigureStandardWaveform function of the IVI‑C driver for the R&S TS-
PFG:
●
Waveform type
●
Amplitude
●
DC component
●
Frequency
●
Start phase
The highest voltage value of a waveform that consists of a DC component plus a variable waveform component must not be higher than +20.0 V on one channel. The lowest voltage value of the output signal must not be lower than ‒20.0 V.
The adjustable frequency range is between 1.0 Hz and 1.0 MHz.
‑
In the case of the "square
nent to low component within the period duration) can be set in steps of one percent
using the rspfg_ConfigureDutyCycle function.
wave" waveform, the duty cycle value (ratio of high compo-
5.1.5 Output of Arbitrary Waveforms
In order to configure and output arbitrary waveforms, the R&S TS-PFG must be
switched to the corresponding mode. For this purpose, the parameter
RSPFG_VAL_OUTPUT_ARB is passed to the IVI‑C function
rspfg_ConfigureOutputMode. This affects both channels. If only one channel is to
be configured, the rspfg_ConfigureOutputModeChannel function must be used.
Arbitrary waveforms can either be output continuously, or the number of signal periods
after which output of the signal stops can be configured. For further information, see
Chapter 5.1.8, "Operating Mode", on page 29.
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R&S®TS-PFG
5.1.5.1 Creation of Waveform
5.1.5.2 Configuration of an Arbitrary Waveform
Functional Description
R&S TS-PFG
By calling the rspfg_CreateArbWaveform function, an arbitrary waveform can be
generated and stored in the waveform memory of the R&S TS-PFG. The return value
of this function allows an existing waveform to be referenced again at a later time by
other functions of the IVI‑C driver.
The size of the waveform memory is max. 1 Msample per channel.
It is also possible to store several smaller waveforms in the memory at the same time.
The data array comprising floating point numbers which is passed to the
rspfg_CreateWaveform function must consist of standardized values, i.e. values
from min. ‒1.0 to max. +1.0.
In order for a standardized arbitrary waveform that is already present in the waveform
memory to be output at a certain amplitude, a gain factor must be specified using the
rspfg_ConfigureArbWaveform function. This factor, multiplied by the standardized
values of the waveform, then gives the level of the individual waveform points (samples) in volts.
This function is also used to configure a DC voltage component (if applicable). As with
the standard waveforms, the sum of DC component plus variable waveform component must not be higher than +20.0 V on one channel. The lowest voltage value of the
arbitrary output signal must not be lower than ‒20.0 V.
If multiple arbitrary waveforms are present in the memory of the R&S TS-PFG, the last
waveform to be configured using the rspfg_ConfigureArbWaveform function (and
therefore activated) is output.
The output speed of the waveform is set for both channels using the
rspfg_ConfigureSampleRate function or for one channel using
rspfg_ConfigureSampleRateChannel. The slowest possible output speed is one
sample per second. The fastest possible output speed is 25 Msample/s. Not all sample
rates between these values are possible. The possible sample rates apart from
25 Msample/s can be calculated using the following formula:
Sample rate in seconds = 1.0 / (100.0e-9 + n * 20.0e-9), where n = 0, 1, 2, 3,…
If sample rates that are between the possible values are configured, the IVI‑C driver
sets a possible adjacent value automatically.
Alternatively, the output speed can also be set using the
rspfg_ConfigureArbFrequency function. This function can be used to set the frequency at which the entire arbitrary waveform is to be repeated. The arbitrary frequency is linked to the arbitrary sample rate by means of the following formula:
Arbitrary frequency = Arbitrary sample rate / Number of waveform samples
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R&S®TS-PFG
5.1.5.3 Addition of Markers
Functional Description
R&S TS-PFG
With the variant of the R&S TS-PFG function generator module (R&S No.
1157.9610.02), it is important to note that an arbitrary waveform must consist of at
least 18 samples if they are to be output with the maximum sample rate of 25 Msample
per second. At lower sample rates, there is no limit with regard to the minimum length
of the waveform.
When arbitrary signals are output, the individual samples can also be linked to marker
signals. These markers allow, for example, other devices to be synchronized with certain sections of an arbitrary waveform.
For each of the two channels of the R&S TS-PFG, a marker output with the two possible output voltages 0.0 V and 3.3 V is provided at the front connector X10.
An existing arbitrary waveform can be linked to a marker data array by calling the IVI‑C
function rspfg_ConfigureArbMarker.
5.1.5.4 Filtering of Output Signal
Arbitrary output signals can be smoothed using a downstream lowpass filter. Each of
the two channels of the R&S TS-PFG has its own filter.
The following three filter frequencies can be set using the IVI‑C driver function
rspfg_ConfigureFilter:
●
3 kHz
●
100 kHz
●
3 MHz
5.1.5.5 Download optimization
The SSRAM of the TS-PFG includes an optimization for the handling of the waveforms
from driver version 01.59 (GTSL 3.40). For compatibility reasons it is partly deactivated
by default. To benefit from the full optimization the attribute
"RSPFG_ATTR_WFM_TRANSFER_OPTIMIZED" must be set. The transferred waveforms will then be saved in the SSRAM memory, until explicitly deleted by the user
(rspfg_ClearArbWaverform). A full memory error might occur. This error does not
occur when the optimization is switched off, because the waveforms are constantly
being transmitted to the starting address of the memory. The function rspfg_reset
does not reset the attribute "RSPFG_ATTR_WFM_TRANSFER_OPTIMIZED". It is sufficient to set the condition during the initialization.
For the optimization to work flawlessly, firmware version 03.04 must be installed on the
TS-PFG. This version is part of GTSL 3.41 and is available as a subsequent firmware
update from this version.
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R&S®TS-PFG
5.1.6 Output of Arbitrary Sequences
5.1.6.1 Creation of a Sequence
Functional Description
R&S TS-PFG
In order to configure and output arbitrary sequences, the R&S TS-PFG must be
switched to the corresponding mode. For this purpose, the parameter
RSPFG_VAL_OUTPUT_SEQ is passed to the IVI‑C function
rspfg_ConfigureOutputMode. This affects both channels. If only one channel is to
be configured, the rspfg_ConfigureOutputModeChannel function must be used.
If multiple arbitrary waveforms are present in the memory of one channel of the R&S
TS-PFG, they can be joined together to form a sequence and then output. A sequence
can consist of up to 256 consecutively called arbitrary waveforms. It is possible to
repeat each subwaveform up to 16382 times. The complete sequence can then be output only once. It must then be restarted again.
Continuous, automatically repeating output of an arbitrary sequence is not possible.
By calling the rspfg_CreateArbSequence function, an arbitrary sequence can be
generated and stored in the waveform memory of the R&S TS-PFG. The return value
of this function allows this sequence to be referenced again at a later time by other
functions of the IVI‑C driver.
Two data arrays of the same length are passed to the function. The first array consists
of reference values (handles) to existing arbitrary waveforms. In the sequence, all
waveforms are played back in the order in which they are listed in this array. The second array consists of integer values that indicate how often the waveform of the first
array with the same array index is to be played back.
Multiple arbitrary sequences can be defined at the same time and stored in the memory of the R&S TS-PFG.
5.1.6.2 Configuration of an Arbitrary Sequence
To enable an arbitrary sequence that consists of standardized arbitrary waveforms to
be output at a certain amplitude, a gain factor must be specified using the
rspfg_ConfigureArbSequence function. This factor, multiplied by the standardized
values of the waveforms, then gives the level of the individual waveform points (samples) in volts.
This function is also used to configure a DC voltage component (if applicable). As with
the standard and arbitrary waveforms, the sum of DC component plus variable waveform component must not be higher than +20.0 V on one channel. The lowest voltage
value of the arbitrary output signal must not be lower than ‒20.0 V.
If multiple arbitrary sequences are present in the memory of the R&S TS-PFG, the last
waveform to be configured using the rspfg_ConfigureArbSequence function (and
therefore activated) is output. The output speed of the waveform is set for both channels using the rspfg_ConfigureSampleRate function or for one channel using
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R&S®TS-PFG
5.1.6.3 Marker Signals in Arbitrary Sequences
Functional Description
R&S TS-PFG
rspfg_ConfigureSampleRateChannel. The slowest possible output speed is one
sample per second. The fastest possible output speed is 25 Msample/s. Not all sample
rates between these values are possible. The possible sample rates apart from
25 MS/s can be calculated using the following formula:
Sample rate in seconds = 1.0 / (100.0e-9 + n * 20.0e-9), where n = 0, 1, 2, 3,…
If sample rates that are between the possible values are configured, the IVI‑C driver
sets a possible adjacent value automatically.
With the variant of the R&S TS-PFG function generator module (R&S No.
1157.9610.02), it is important to note that each subwaveform of the arbitrary sequence
must consist of at least 18 samples if the sequence is to be output with the maximum
sample rate of 25 Msample per second. At lower sample rates, there is no limit with
regard to the minimum length of the subwaveforms.
All marker signals that have been defined for the individual arbitrary waveforms of
which the arbitrary sequence consists, are also output at the front connector X10 of the
R&S TS-PFG when the sequence is output.
Information on how to add marker signals to arbitrary waveforms can be found in
Chapter 5.1.5.3, "Addition of Markers", on page 25.
5.1.6.4 Filtering of Output Signal
As with arbitrary output signals, arbitrary sequences can also be smoothed using a
downstream lowpass filter. Each of the two channels of the R&S TS-PFG has its own
filter.
The following three filter frequencies can be set using the IVI‑C driver function
rspfg_ConfigureFilter:
●
3 kHz
●
100 kHz
●
3 MHz
5.1.6.5 Improved Performance from Using Arbitrary Sequences
In some cases, skillful use of an arbitrary sequence can result in a considerable
improvement in performance with regard to program execution speed compared to
using an arbitrary waveform.
An additional improvement in perfomance can be obtained by optimizing the download
process (see Chapter 5.1.5.5, "Download optimization", on page 25).
The following example is intended to demonstrate the effective use of an arbitrary
sequence:
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R&S®TS-PFG
Functional Description
R&S TS-PFG
Example:
A bit sequence is to be generated at the output of the function generator, whereby the
high bits are to consist of 70 sine‑wave periods with a frequency of 125 kHz. A level of
0.0 V is output for all low bits.
If a sine‑wave period is formed from ten waveform points, a total of 700 samples will be
required for a high bit. At a constant sample rate, this means that 700 samples of the
0.0 V level are also required for the low bit. If a bit sequence consisting of 100 bits is to
be output, the total number of samples to be output will be 70000.
Loading an arbitrary waveform consisting of 70000 waveform points to the sample
memory of the R&S TS-PFG will take approx. 360 ms (if, for example, the R&S CompactTSVP is controlled by an external PC via a PCI bridge).
The same waveform output can be achieved by using an arbitrary sequence. In this
way, it is possible to reduce the time required to configure the R&S TS-PFG to approx.
15 ms. Here, two different arbitrary waveforms are defined first of all:
●
One sine‑wave period consisting of ten samples.
●
One waveform consisting of one single 0.0 V sample.
In the next step, the arbitrary sequence is defined by specifying in a data array the
waveforms which are to be output and the order in which they are to be output.
In a second data array with the same length, it is specified how often the waveform of
the corresponding array position is to be repeated. In our example, the length of the
two data arrays is max. 100 because 100 bits are to be output. If there are sections in
the waveform to be output which contain several identical bits that are to be output
consecutively, it is also possible to reduce the length of the two data arrays. For this
purpose, the number of repetitions of the arbitrary waveform is simply multiplied at the
corresponding sections.
This method means that instead of the previous 70000 waveform points only 11 waveform points plus the data arrays with the information on how the sequence is structured
then need to be sent to the R&S TS-PFG. In this example, the time required for configuration of the function generator is reduced by 96 percent.
5.1.7 Triggering
The output of waveforms on one channel or the synchronized output on both channels
of the R&S TS-PFG function generator can be started by means of trigger events. One
of eight PXI trigger lines available in the R&S CompactTSVP can be used as the trigger input.
In this case, a different plug‑in board (e.g. the analog stimulus and measurement module R&S TS‑PSAM) which is installed in the R&S CompactTSVP and which can generate PXI trigger signals, functions as the trigger source.
It is also possible to trigger the R&S TS-PFG via an external TTL signal fed in at the
front connector X10. Both channels can be triggered by trigger inputs XTI1 and XTI2.
The third way in which the beginning of signal output can be started is software triggering. Here, signal output on a channel of the R&S TS-PFG is started from a software
application by means of the IVI‑C driver function call
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R&S®TS-PFG
Functional Description
R&S TS-PFG
rspfg_SendChannelSoftwareTrigger from a software application. Both channels
can be started synchronously using the rspfg_SendSoftwareTrigger function,
which does not act on a specific channel.
The IVI‑C driver function rspfg_ConfigureTriggerSource is used to configure
which of the three described trigger sources is to be implemented. After the device
driver is opened or the driver is reset, "software triggering" is set at the trigger source
for both channels of the R&S TS-PFG.
If signal output is to be delayed after a trigger event has occurred, this delay can be
configured using the rspfg_ConfigureTriggerDelay function.
Following configuration of the trigger source and trigger delay, the R&S TS-PFG is
switched to the "ready to receive trigger signals" state by calling the
rspfg_InitiateGeneration function and then waits for the trigger event.
If the rspfg_AbortGeneration function is called before a trigger event occurs, the
function generator is switched back to the "insensitive to trigger signals" state. If a trigger event has already occurred thereby starting signal output, this function causes signal output to be aborted.
5.1.8 Operating Mode
The two channels of the R&S TS-PFG function generator can be used in two different
operating modes: continuous mode or burst mode.
Either the RSPFG_VAL_OPERATE_CONTINUOUS or RSPFG_VAL_OPERATE_BURST
parameter is passed to the rspfg_ConfigureOperationMode function.
Opening the device driver or resetting the driver causes both channels of the R&S TSPFG to be set to the RSPFG_VAL_OPERATE_CONTINUOUS operating mode.
5.1.8.1 Continuous Mode
In continuous mode, the previously configured signal is output continuously immediately after the device driver function rspfg_InitiateGeneration is called. In this
operating mode, the trigger source which the user has configured for the used channel
is irrelevant. In this mode, the trigger source is always set internally to the software trigger and, at the end of the rspfg_InitiateGeneration function, a software trigger
is automatically sent to each channel that is in continuous mode.
After initialization of the device driver by means of the rspfg_init and
rspfg_InitWithOptions function or after resetting of the R&S TS-PFG with the
rspfg_reset function, both channels of the function generator remain in continuous
mode and output 0.0 V DC as the signal.
A continuously output waveform can be aborted using the rspfg_AbortGeneration
function. Here, it is important to note that only the variable component of the waveform
is ended, i.e. drops to 0.0 V. If a DC voltage component of the wave has been configured, this continues to be applied at the channel output.
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R&S®TS-PFG
5.1.8.2 Burst Mode
Functional Description
R&S TS-PFG
Unlike the standard waveforms and arbitrary waveforms which can be output continuously, the arbitrary sequence behaves differently in continuous mode. An arbitrary
sequence cannot be output continuously. Once it has been output, renewed output
must be restarted using the rspfg_InitiateGeneration function.
In burst mode, it is possible to determine how often a certain waveform is to be output
consecutively. This is determined using a parameter of the device driver function
rspfg_ConfigureBurstCount. The permissible value range of the parameter is
from 1 to 16382. The value 0 (defined as RSPFG_VAL_BURST_COUNT_INFINITE) is
also permitted. In this case, the signal is output continuously.
Unlike in continuous mode, signal output in burst mode is only started by a trigger
event which must occur after the rspfg_InitiateGeneration function is called.
This can be a software trigger, a PXI trigger or an external TTL trigger signal at the
front connector of the R&S TS-PFG. The rspfg_ConfigureTriggerSource function is used to determine which of these three trigger types is to be used. When waveform output has been completed, the voltage level of the last trace point continues to
be applied at the channel output of the function generator.
Once again, the arbitrary sequence behaves differently here. It cannot be output continuously and also cannot be output multiple times in succession. Once it has been output, renewed output must be restarted using the rspfg_InitiateGeneration function and a subsequent trigger event.
5.1.9 Fixing of DC Offset Range
The hardware of the R&S TS-PFG contains four gain ranges for the DC voltage component of a waveform (DC offset). These ranges are 20 V, 10 V, 5 V and 1 V. To output
a DC voltage component programmed by the user, the optimum gain range must first
be set at the hardware and then the appropriate D/A converter value must be calculated.
If the DC voltage component is to be changed and the new value is in a different gain
range, slight voltage jumps will occur when the switchover takes place at the output of
the corresponding R&S TS-PFG channel, because activation of the new gain range
and programming of the associated A/D converter value can only occur in sequence.
Example:
The DC voltage component of a waveform is to be reduced from 11 V to 9 V:
●
The device driver first switches the gain range of the DC voltage component from
20 V to 10 V. As the A/D converter value is still unchanged, this causes the voltage
at the output of the R&S TS-PFG channel to drop briefly to approx. 5.5 V (11 V/
20 V * 10 V).
●
In the second step, the A/D converter value which corresponds to an output voltage of 9 V in the 10 V gain range is then set. The voltage at the channel output of
the R&S TS-PFG now increases from 5.5 V to the desired 9 V.
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R&S®TS-PFG
Functional Description
R&S TS-PFG
In some cases, these effects are undesirable during switchover of the gain range. In
such cases, there is the possibility of fixing the gain range of the DC voltage component. This is done using the rspfg_ConfigureDCOffsetRange function and the
passed parameter offsetRange, e.g. 20.0 V. The 20 V range is then used even if a
DC voltage component of less then 10 V is set.
The disadvantage of this method is that the available D/A converter resolution is lower,
which in turn means lower accuracy of the output voltage at low voltage values. If an
output voltage of 0.5 V is configured and the 1 V gain range is active, the output voltage will deviate by a maximum of approx. +/‒250 μV from the nominal value. In the
20 V gain range, the output voltage of 0.5 V can only be set with an accuracy of
approx. +/‒5 mV.
After initialization of the device driver by means of the function rspfg_init or
rspfg_InitWithOptions or after resetting of the R&S TS-PFG using the
rspfg_reset function, automatic switchover of the DC voltage gain range is config-
ured on both channels. This corresponds to calling the
rspfg_ConfigureDCOffsetRange function with the value 0.0 V (defined as
RSPFG_OFFSET_RANGE_AUTO) which is passed as the parameter offsetRange.
5.1.10 Dynamic Adaptation of Waveform Amplitude
The functionality described in this chapter is only supported by the variant of the R&S
TS-PFG function generator module with R&S No. 1157.9610.02. Firmware version
3.03 or higher is required.
The amplitude of the standard waveform to be output is determined using the
rspfg_ConfigureStandardWaveform function. For this purpose, the software
driver sets the most suitable of the four different gain ranges 20 V, 10 V, 5 V or 1 V at
the hardware and calculates the appropriate waveform points which are then written to
the waveform memory of the R&S TS-PFG.
If the amplitude of the waveform is to be changed by calling the
rspfg_ConfigureStandardWaveform function again, the individual points must be
recalculated for the waveform memory. This leads to interruption of signal output until
writing to the waveform memory has been completed. Only then is output of the waveform with the new amplitude restarted.
In some cases, interruption of the output waveform when the amplitude is changed is
undesirable. For this reason, the software driver provides a function with which the
individual waveform points of the memory can be multiplied dynamically in the FPGA of
the R&S TS-PFG by a factor between 0.0 and 1.0 and thereby reduced. The name of
this function is rspsfg_ConfigureDynamicACAmplitude. A desired amplitude
value which must be less than or equal to the amplitude value that was previously set
using the rspfg_ConfigureStandardWaveform function is passed as the parameter.
A typical program execution sequence could be as follows:
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R&S®TS-PFG
Functional Description
R&S TS-PFG
rspfg_AbortGeneration
rspfg_ConfigureStandardWaveform
rspfg_ConfigureDynamicACAmplitude
rspfg_InitiateGeneration
rspfg_ConfigureDynamicACAmplitude
R&S TS-PFG outputs 0.0 V constantly
E.g. 10.0 Vpp are configured,
R&S TS-PFG continues to output 0.0 V
E.g. 2.0 Vpp are configured,
R&S TS-PFG continues to output 0.0 V
R&S TS-PFG starts output of a standard waveform
with ampl. 2.0 Vpp
Seamless changeover to output of the standard
waveform with a changed amplitude of e.g. 5.0 Vpp
Calling the rspfg_ConfigureStandardWaveform function again ends the mechanism for dynamic amplitude adjustment. A waveform with the passed amplitude is output on the corresponding channel of the R&S TS-PFG.
With the output of arbitrary waveforms or sequences consisting of arbitrary waveforms,
the magnitude of the output levels can be changed dynamically using the
rspfg_ConfigureDynamicACAmplitude function in the same way as for standard
waveforms. In the program execution sequence shown above, the functions
rspfg_ConfigureArbWaveform and rspfg_ConfigureArbSequence would simply need to be used instead of the rspfg_ConfigureStandardWaveform function.
In these two functions, the gain factor in volts by which the individual points of the arbitrary waveform (values between 0.0 and 1.0) are multiplied is specified instead of the
amplitude of a waveform. The amplitude passed in the
rspfg_ConfigureDynamicACAmplitude function must be between 0.0 V and the
previously configured gain factor for arbitrary waveforms.
Dynamic amplitude control using the rspfg_ConfigureDynamicACAmplitude
function only affects the variable component of a waveform (AC amplitude). The DC
voltage component (DC offset) of the output waveform remains unchanged.
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R&S®TS-PFG
Startup
Installation of R&S TS
6 Startup
6.1 Installation of R&S TS-PFG Module
To install the R&S TS-PFG plug-in module, proceed as follows:
Damage to backplane caused by bent pins
Bent pins can cause permanent damage to the backplane.
Check the backplane connectors for bent pins.
Any bent pins must be straightened.
When inserting the plug‑in module, guide it with both hands and carefully push it into
the backplane connectors.
‑PDC Module
1. Power down and switch off the R&S CompactTSVP.
2. Select a suitable front‑side slot.
3. Remove the corresponding section of the front panel from the TSVP chassis by
undoing the screws.
4. Push in the plug‑in module using moderate pressure
5. The upper catch pin of the plug‑in module must be inserted into the right hole in the
TSVP chassis and the lower catch pin into the left hole.
The module is correctly located when a distinct "stop" can be felt.
6. Securely tighten the screws at the top and bottom of the front panel of the plug‑in
module.
6.2 Installation of R&S TS‑PDC Module
To install the plug‑in module, proceed as follows:
Damage to backplane caused by bent pins
Bent pins can cause permanent damage to the backplane.
Check the backplane connectors for bent pins.
Any bent pins must be straightened.
When inserting the plug‑in module, guide it with both hands and carefully push it into
the backplane connectors.
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R&S®TS-PFG
Startup
Installation of R&S TS‑PDC Module
The R&S TS-PFG module must already have been installed.
1. Select the corresponding rear I/O slot for the R&S TS-PFG module.
2. Remove the corresponding section of the rear panel from the R&S CompactTSVP
chassis by undoing the two screws.
3. Push in the plug-in module using moderate pressure
The module is correctly located when a distinct "stop" can be felt.
Note: The R&S TS‑PDC module must be inserted with particular care, making cer-
tain that the connector is correctly guided into the socket opening in the backplane
– it must not be inserted at an angle or with incorrect alignment, etc. The short printed board guides alone do not ensure absolutely reliable guiding.
Multiple adjacent R&S TS‑PDC modules should always be inserted in the order
"from left to right" and removed in the reverse order. As the spaces are so narrow,
care must be taken not to damage any components on the solder side of the module.
4. Tighten the two fastening screws on the front panel of the module.
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R&S®TS-PFG
7.1 Driver Software
Software
Soft Panel
7 Software
A LabWindows IVI driver which supports the classes IVI FGEN and IVI SWITCH is
provided to enable actuation of the R&S TS-PFG function generator module. All additional functions of the hardware are controlled using specific extensions of the driver.
The driver is part of the R&S GTSL software. All the functions of the driver are described fully in the online help and in the LabWindows/CVI function panels. The following
software modules are installed during driver installation:
Table 7-1: Driver installation – R&S TS‑PFG
Module Path Remarks
rspfg.dll <GTSL directory>\Bin
rspfg.chm <GTSL directory>\Bin
rspfg.fp <GTSL directory>\Bin
rspfg.sub <GTSL directory>\Bin
rspfg.lib <GTSL directory>\Bin
rspfg.h <GTSL directory>\Include
The IVI and VISA libraries from National Instruments are needed to run the driver.
7.2 Soft Panel
The software package of the R&S TS-PFG module includes a soft panel (see Fig-
ure 7-1). The soft panel is based on the IVI driver and enables interactive operation of
the module on the screen using the mouse.
Driver
Help file
LabWindows/CVI function panel
file, function panels for CVI development environment
LabWindows/CVI attribute file.
This file is required by some
"function panels".
Import library
Header file for driver
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R&S®TS-PFG
Software
Soft Panel
Figure 7-1: Soft panel of R&S TS-PFG
Operation of the soft panels is described in "Software Description for R&S GTSL".
In the R&S TS-PFG soft panel, arbitrary waveform data can be loaded by reading in
external files. This data can exist in four different formats: "ASCII", "Binary Little
Endian", "Binary Big Endian" and "AWD". The value range of the data is allowed to be
greater than +/‒1.0 volt as the import function of the soft panel can perform a standardization routine. Only values between ‒1.0 volt and +1.0 volt can be passed to the functions of the R&S TS-PFG IVI‑C driver which are used for creating arbitrary waveforms.
●
ASCII data format
The individual waveform points are stored in a text file with the extension .txt as
floating‑point numbers or integer values without specification of the unit "volt". A
line break is used as the separator. All lines that do not begin with a number are
interpreted as a comment. Space characters at the beginning of a line are ignored.
●
Binary Little Endian
Data format of a binary file with the extension .bin. A waveform point is represented by two bytes that form a 16‑bit integer value. The least significant byte is stored
first, i.e. at the smaller memory address.
●
Binary Big Endian
Data format of a binary file with the extension .bin. A waveform point is represented by two bytes that form a 16‑bit integer value. The most significant byte is stored
first, i.e. at the smaller memory address.
●
AWD
Data format of a binary file with the extension .acv. The file begins with a comment that ends with a new‑line character (0x0a). This is followed by the waveform
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R&S®TS-PFG
7.3 R&S TS-PFG Programming Example
Software
R&S TS-PFG Programming Example
points, each consisting of four bytes. The arrangement of the four bytes corresponds to the float data type.
/*
Generating different output signals with and without trigger conditions.
The different examples just show the order of function calls used to output
a special signal.
Error handling is not considered in this example in order to keep it easy to read.
The return status should be checked after each device driver call.
*/
/* rspfg ivi-driver header file */
#include "rspfg.h"
static ViSession s_VI;
static ViStatus s_Status;
main()
{
double arb_wfm_A[] = {-0.9, 0.8, -0.7, 0.6, -0.5, 0.4, -0.3, 0.2, -0.1, 0.0};
double arb_wfm_B[] = { 0.5, 0.6, 0.7, 0.8, 0.9, 0.9, 0.8, 0.7, 0.6, 0.5};
ViInt32 arb_wfm_A_handle;
ViInt32 arb_wfm_B_handle;
double marker_wfm[] = { 0.0, 0.0, 1.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0};
ViInt32 arb_seq[3];
ViInt32 arb_seq_loop_array[3];
ViInt32 arb_seq_handle;
/*
The resource descriptor must be adapted to the system.
Init the rspfg driver.
After the fuction call the module will generate a dc voltage output
signal of 0 volts on both channels.
*/
s_Status = rspfg_InitWithOptions ( "PXI6::12::0::INSTR", VI_TRUE, VI_TRUE, "", &s_VI);
/* Connect channel 1 to front connector X10. */
s_Status = rspfg_Connect (s_VI, "CH1_Lo","ABa2");
s_Status = rspfg_Connect (s_VI, "CH1_Hi","ABa1");
/* Connect channel 2 to front connector X10. */
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R&S®TS-PFG
Software
R&S TS-PFG Programming Example
s_Status = rspfg_Connect (s_VI, "CH2_Lo","ABb2");
s_Status = rspfg_Connect (s_VI, "CH2_Hi","ABb1");
/* Open ground relays of both channels */
s_Status = rspfg_ConfigureGround(s_VI, "CH1", VI_FALSE);
s_Status = rspfg_ConfigureGround(s_VI, "CH2", VI_FALSE);
/* Wait until switching relays are settled. */
s_Status = rspfg_WaitForDebounce (s_VI, 1000);
/*
The following three function calls are optional at this place,
because this values are default values which have been already
set in the functions rspfg_InitWithOptions().
*/
/* Configure continuous generation of the output signal. */
s_Status = rspfg_ConfigureOperationMode (s_VI, "CH1", RSPFG_VAL_OPERATE_CONTINUOUS);
/* Configure continuous generation of the output signal. */
s_Status = rspfg_ConfigureOperationMode (s_VI, "CH2", RSPFG_VAL_OPERATE_CONTINUOUS);
/* Configure standard function output for both channels. */
s_Status = rspfg_ConfigureOutputMode (s_VI, RSPFG_VAL_OUTPUT_FUNC);
/*
Configure sine wave output on channel 1 and triangle output on channel two with
2.0 volts amplitude peak to peak,
frequency: 1000 Hz,
phase: 0 Hz,
dc offset voltage: 0.0 volt.
*/
s_Status = rspfg_ConfigureStandardWaveform (s_VI, "CH1", RSPFG_VAL_WFM_SINE,
2.0, 0.00, 1000, 0.00);
s_Status = rspfg_ConfigureStandardWaveform (s_VI, "CH2", RSPFG_VAL_WFM_TRIANGLE,
2.0, 0.00, 1000, 0.00);
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R&S TS-PFG Programming Example
Figure 7-2: Oscilloscope: Standard signals on both channels, not synchronous
*/
/*
Note that both channels haven't been startet at the same moment.
The signals are phase locked but they show a phase shift to each other.
To start both channels of the function generator synchronously at the same
moment, first prevent the generator from generating an output signal with
function rspfg_AbortGeneration(), then optionally set or change output
settings and subsequently start signal generation on both channels with
function rspfg_InitiateGeneration().
*/
/* Stop generation of output signals */
s_Status = rspfg_AbortGeneration(s_VI);
/*
Start generation of output signals synchronously on both channels.
In CONTINUOUS mode the generator will immediately output signals without
any trigger event.
*/
s_Status = rspfg_InitiateGeneration(s_VI);
/*
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R&S TS-PFG Programming Example
Figure 7-3: Oscilloscope: Standard signals on both channels, synchronous
*/
/*
Switch to burst mode. Only the configured number of waveforms
will be output at a specified trigger event. After initialization of the
device driver, the default trigger source is set to software trigger.
*/
/* Stop generation of output signal.*/
s_Status = rspfg_AbortGeneration (s_VI);
/* Configure number of bursts. */
s_Status = rspfg_ConfigureBurstCount (s_VI, "CH1", 2);
s_Status = rspfg_ConfigureBurstCount (s_VI, "CH2", 1);
/* Configure burst generation of the output signal. */
s_Status = rspfg_ConfigureOperationMode (s_VI, "CH1", RSPFG_VAL_OPERATE_BURST);
s_Status = rspfg_ConfigureOperationMode (s_VI, "CH2", RSPFG_VAL_OPERATE_BURST);
/*
Configure sine wave output on channel 1 with 1.0 volts amplitude peak to peak,
with
frequency: 2000 Hz,
phase: 0 Hz,
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R&S TS-PFG Programming Example
dc offset voltage: 0.0 volt.
*/
s_Status = rspfg_ConfigureStandardWaveform (s_VI, "CH1", RSPFG_VAL_WFM_SINE,
2.0, 0.00, 2000, 0.00);
/* Configuration of channel 2 is not changed */
/*
Initiate generating signal generator output.
Channel 1 waits for the software trigger event and then shows 2 signal bursts.
Channel 2 waits for the software trigger event and then shows 1 signal burst.
*/
s_Status = rspfg_InitiateGeneration (s_VI);
/* Start generating signal generator output. */
s_Status = rspfg_SendSoftwareTrigger (s_VI);
/*
Figure 7-4: Oscilloscope: Bursts consisting of standard signals on both channels
*/
/*
Output of an arbitrary waveform on channel 2
*/
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R&S TS-PFG Programming Example
/* Stop generation of output signal.*/
s_Status = rspfg_AbortGeneration (s_VI);
/* Create the arbitrary waveform */
s_Status = rspfg_CreateArbWaveform(s_VI, 10, arb_wfm_A, &arb_wfm_A_handle );
/* switch to arbitrary waveform mode */
s_Status = rspfg_ConfigureOutputModeChannel(s_VI, "CH2", RSPFG_VAL_OUTPUT_ARB );
/* Configure the arbitrary waveform on channel 2 */
s_Status = rspfg_ConfigureArbWaveform(s_VI, "CH2", arb_wfm_A_handle, 1.0, 0.0 );
/* Configure sample rate on channel 2 */
s_Status = rspfg_ConfigureSampleRateChannel(s_VI, "CH2", 1.0e4 );
/* Initiate generating signal generator output.
Channel 1 waits for the software trigger event and then shows 2 sine wave
signal bursts.
Channel 2 waits for the software trigger event and then shows 1 arbitrary
signal burst.
*/
s_Status = rspfg_InitiateGeneration (s_VI);
/* Start generating signal generator output. */
s_Status = rspfg_SendSoftwareTrigger (s_VI);
/*
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R&S TS-PFG Programming Example
Figure 7-5: Oscilloscope: Burst of an arbitrary signal on channel 2 (green)
*/
/*
Switch channel 2 to continuous output of the arbitrary wavefrom.
Continuous mode doesn't need any trigger event.
The arbitrary signal is immediately output continuously.
*/
s_Status = rspfg_ConfigureOperationMode (s_VI, "CH2", RSPFG_VAL_OPERATE_CONTINUOUS);
/*
Initiate generating signal generator output.
Channel 1 waits for the software trigger event and then shows 2 sine wave
signal bursts.
Channel 2 is already running but it is restarted and outputs the arbitrary
signal continuously now.
*/
s_Status = rspfg_InitiateGeneration (s_VI);
/* Start generating signal generator output. */
s_Status = rspfg_SendChannelSoftwareTrigger (s_VI, "CH1");
/*
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R&S TS-PFG Programming Example
Figure 7-6: Oscilloscope: Continuous arbitrary signal on channel 2 (green)
*/
/*
Add a marker signal to the arbitrary waveform of channel 2.
The marker signal shows up at the third sample of the arbitrary waveform
*/
/* Associate the marker waveform to an existing arbitrary waveform */
s_Status = rspfg_ConfigureArbMarker(s_VI, arb_wfm_A_handle, 10, marker_wfm);
/* Configure the marker: enable the marker and set it polarity to high */
s_Status = rspfg_ConfigureMarkerOutput(s_VI, "CH2", VI_TRUE,
RSPFG_VAL_MARKER_POL_HIGH_ACTIVE);
/* Initiate generating signal generator output. */
s_Status = rspfg_InitiateGeneration (s_VI);
/* Start generating signal generator output. */
s_Status = rspfg_SendChannelSoftwareTrigger (s_VI, "CH1");
/*
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R&S TS-PFG Programming Example
Figure 7-7: Oscilloscope: Marker signal (brown) of arbitrary signal on channel 2 (green)
*/
/*
Output of an arbitrary sequence on channel 1
*/
/* Stop generation of output signal.*/
s_Status = rspfg_AbortGeneration (s_VI);
/* Create the second arbitrary waveform */
s_Status = rspfg_CreateArbWaveform(s_VI, 10, arb_wfm_B, &arb_wfm_B_handle );
/* Create an arbitrary sequence from both arbitrary waveforms */
arb_seq[0] = arb_wfm_A_handle;
arb_seq[1] = arb_wfm_B_handle;
arb_seq[2] = arb_wfm_A_handle;
arb_seq_loop_array[0] = 1;
arb_seq_loop_array[1] = 1;
arb_seq_loop_array[2] = 1;
s_Status = rspfg_CreateArbSequence(s_VI, 3, arb_seq, arb_seq_loop_array, &arb_seq_handle );
/* switch to arbitrary sequence mode */
s_Status = rspfg_ConfigureOutputModeChannel(s_VI, "CH1", RSPFG_VAL_OUTPUT_SEQ );
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/* Configure the arbitrary waveform sequence on channel 1 */
s_Status = rspfg_ConfigureArbSequence(s_VI, "CH1", arb_seq_handle, 1.0, 0.0 );
/* Configure sample rate on channel 1 */
s_Status = rspfg_ConfigureSampleRateChannel(s_VI, "CH1", 1.0e4 );
/*
Initiate signal generator output.
Channel 1 waits for the software trigger event and then shows the
arbitrary sequence once.
Channel 2 was stopped but it is restarted and ouputs the arbitrary
signal continuously.
*/
s_Status = rspfg_InitiateGeneration (s_VI);
/* Start generating signal generator output on channel 1. */
s_Status = rspfg_SendSoftwareTrigger (s_VI);
/*
Figure 7-8: Oscilloscope: Arbitrary sequence on channel 1 (yellow)
*/
/*
Please note: An arbitrary sequence can only be output once.
It doesn’t matter if the R&S TS-PFG channel is in CONTINUOUS mode or
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R&S TS-PFG Programming Example
in BURST mode.
*/
/* Stop generation of output signal. */
s_Status = rspfg_AbortGeneration (s_VI);
/*
Figure 7-9: Oscilloscope: All variable signals have been switched off
*/
/* Close the device driver */
s_Status = rspfg_close (s_VI);
}
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R&S®TS-PFG
8.1 LED Test
Power‑On Test
8 Self‑Test
The R&S TS-PFG function generator has an integrated self-test capability. The following tests are possible:
●
LED test
●
Power‑on test
●
TSVP self‑test
When the device is switched on, all three LEDs light up for approx. one second. This
indicates that the 5 V supply voltage is present and all LEDs are OK. The following
statements can be made regarding the different LED states:
Table 8-1: Statements regarding LED test
Self‑Test
LED Description
One LED does not light up Hardware problem on the module; LED defective
No LEDs light up No +5V supply
If diagnostics suggest a problem with the supply voltage, the LEDs for the associated
R&S TS‑PDC rear I/O module must be inspected visually. If a supply voltage failure is
confirmed, the R&S TS‑PDC module must be replaced.
8.2 Power‑On Test
The power‑on test runs at the same time as the LED test. The following statements
can be made regarding the different display states of the LEDs:
Table 8-2: Statements regarding power
LED Description
PWR LED (green) ON All supply voltages are present
PWR LED (green) OFF At least one supply voltage is missing
ERR LED (red) OFF If the green LED is lit at the same time, there are no
‑
on test
detectable faults
ERR LED (red) ON There is a hardware fault. The power‑on test has
detected a fault on the R&S TS-PFG.
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R&S®TS-PFG
8.3 TSVP Self‑Test
Self‑Test
TSVP Self‑Test
The TSVP self‑test runs an in‑depth test on the R&S TS-PFG module and generates a
detailed log. This is done using the "Self-Test Support Library".
The R&S TS‑PSAM analog stimulus and measurement module is used as a measurement unit in the TSVP self‑test. Correct operation of the modules in the system is
ensured by measurements on the analog bus.
Information about starting the self‑test and about the sequence of the necessary steps
can be found in the GTSL software description or GTSL online help.
A detailed description of the checked parameters and processes can be found in the
service manual for the R&S CompactTSVP / R&S PowerTSVP.
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R&S®TS-PFG
9.1 R&S TS-PFG
9.1.1 Connector X10
Interface Description
R&S TS-PFG
9 Interface Description
Figure 9-1: R&S TS-PFG connector X10
Table 9-1: Pin assignment of R&S TS-PFG connector X10
1 LABA1
2 LABB1
3 LABC1
4 LABD1
5
A B C
LABA2
LABB2
LABC2
LABD2
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R&S®TS-PFG
Interface Description
R&S TS-PFG
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28 GND GND GND
29 MO1 GND MO2
30 XTI1 GND XTI2
31 GND GND GND
32 GND GND CHA-GND
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R&S®TS-PFG
9.1.2 Connector X20
Interface Description
R&S TS-PFG
Figure 9-2: R&S TS-PFG connector X20
Figure 9-3: Pin assignment of R&S TS-PFG connector X20
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R&S®TS-PFG
9.1.3 Connector X30
Interface Description
R&S TS-PFG
Figure 9-4: R&S TS-PFG connector X30
Table 9-2: Pin assignment of R&S TS-PFG connector X30
7
6
5 ABC1
4
3 ABC2
2
1 ABD2
E D C B A
GND
ABB1
ABA2
ABA1
ABB2
ABD1
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R&S®TS-PFG
9.1.4 Connector X1 (cPCI Bus)
Interface Description
R&S TS-PFG
Figure 9-5: R&S TS-PFG connector X1
Figure 9-6: Pin assignment of R&S TS-PFG connector X1
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R&S®TS-PFG
9.2 R&S TS‑PDC
9.2.1 Connector X20
Interface Description
R&S TS‑PDC
Figure 9-7: R&S TS‑PDC connector X20 (viewed from mating side)
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R&S®TS-PFG
Interface Description
R&S TS‑PDC
Figure 9-8: R&S TS‑PDC – assignment of connector X20
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R&S®TS-PFG
10 Specifications
Specifications
The specifications for the R&S TS-PFG module are given in the corresponding data
sheets.
If discrepancies exist between the data given in this manual and the values in the data
sheet, the values in the data sheet take precedence.
57User Manual 1152.3820.12 ─ 12
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