Triguard SC300E
MPP
Processor Module
(MPP)
Issue 6
Three MPPs are fitted in the three right hand slots of the main chassis. They provide a central
processing
Operation of the system is software controlled by the Real Time Task Supervisor (RTTS) which
continuously
facility for the Triguard SC300E system.
executes the following functions:
October 2005
•
Polling of inputs and outputs
•
Diagnostics to detect internal faults, power outages, voting agreement and the health
of the processor module microprocessor
•
Tracking of maintenance activities such as hot repair
•
Detection of latent faults in I/O modules
•
Execution of safety and control logic
•
Data acquisition and Sequence Of Events (SOE) for transmission to an operator
workstation
008-5100
2
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SC300E
Diagnostic
port
Switch S1
Switch S2
Connector J1
Keyswitch
Connector J2
Microprocessor
80486DX
Back up batteries
Figure 1-1 MPP General view and front panel detail
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ASSOCIATED DOCUMENTATION
SC300E MPP Processor Module
Reference No
008-5097
008-5105
008-5115
008-5217
SPECIFICATION
Model
Processor
EPROM
RAM
RAM backup battery (optional)
Inter processor communication
Diagnostic port
Title
Chassis User Manual
MBB Bus Extender Module User Manual
TBA Bus Expansion Adaptor User Manual
TBT Bus Terminator User Manual
MPP
Intel family
1 Mbyte fitted
1 Mbyte fitted
Lithium battery, shelf life 8 to 10 years
(program holdup 6 months) (Spares available)
Serial high speed, read only
For factory testing purposes
4 position keyswitch
Indicators
Module power consumption
Overall size (mm)
Overall size (inches)
On Line, Program, Test, Reset
Run, On Line, Program, Test, Health, I/O
Battery, Communications
Scan,
10W
400(9U)H x 397L x 28W
15.75H x 15.63L x 1.1W
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SC300E
Environmental s p ecifica t i o n s
The maximum ambient temperature measured at the hottest point within the Triguard system
shall
not be greater than 60 degrees centigrade.
Temperature operating:
Temperature
Humidity
EMC/RFI
Vibration/Shock
Certification:
General Certification: Ref. SC300E Product Guide (ref 008-5209)
storage:
Immunity
+5°C to 60°C
-
25°C to +70°C
5% to 95% non-condensing at ambient <40°C
Tested and certified to IEC 1131-Part 2 1994
Tested and certified to IEC 1131-Part 2 1994
TRANSPORT AND HANDLING
The processor module must be transported and stored in its original packing material which
should
be
retained for this purpose.
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SC300E MPP Processor Module
TECHNICAL DESCRIPTIO
N
Physical
The MPP is a 9U high PCB with integral front panel. Some aspects of MPP operation are
determined
by
link settings.
External connections
Each module is plugged into the main chassis backplane bus system via two DIN41612
connectors J1 and J2 (Figure 1-1 ). Figure 2-1 shows the main chassis backplane bus
interconnections.
Diagnostic port
A 9-pin D-type connector is provided on the front panel. The pinout is listed in Table 2-4. The
diagnostic port signals are also available at connector ‘g’ at the rear of the chassis backplane
(Tabl
e 2-5).
Chassis backplane
The signals passing through J2 are available at the rear of the main chassis backplane. The
rear backplane connectors are shown in Figure 2-2
Chassis User Manual (Ref 008-5097).
. For additional information, refer to the
Connector J1 links the MPP to the I/O modules and is represented on the rear of the chassis
backplane
(96 pins in three columns a, b and c). Pins 07 to 10 of columns ‘b’ and ‘c’ are
extended to enable the installation of the chassis address setting links (see Figure 2-5).
Column ‘b’ of connectors J2 links each MPP to the other MPPs via the Inter-Processor
Communications Bus.
Columns ‘a’ and ‘c’ of connectors J2 link each MPP to the expansion bus via rear backplane
connectors
by
Area ‘d’. Area ‘d’ consists of extensions to the pins of the J1 mating connector
‘e’.
specially
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SC300E
Connector summary
Connector
J3 (diagnosic port)
J1 (I/O bus)
J2 (expansion bus)
e (expansion bus)
f (watchdog)
g (diagnosic)
Location
MPP front panel (Figure 1-1) 9-pin D type socket female
MPP rear edge (Figure 1-1)
MPP rear edge (Figure 1-1)
Rear of backplane (Figure2-1) 96-pin DIN41612 type C female
Rear of backplane
Rear of backplane
CONTROLS AND INDICATORS
Keyswitch
User control is by the four position front panel keyswitch.
The
switch positions as follows:
Type
96-pin DIN41612 type C male
96-pin DIN41612 type C male
2-pin Combicon
26-pin IDC socket
ON LINE (1)
PROGRAM (2) :
TEST (3)
RESET
The keyswitch can only be removed at the ON LINE (Position 1) setting.
(4)
:
:
:
Position for normal operating mode
Position for loading application
Reserved for future use
Holds microporcessor in reset mode
NOTE
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LED indicators
Triguard
SC300E MPP Processor Module
The front panel LED’s illuminate to indicate the following conditions:
RUN (gree n):
ON
-
LINE (yellow):
PROGRAM (yellow): MPP in program mode
TEST (yellow):
HEALTH (green):
I/O SCAN (yellow):
BATTERY (green):
SIO COMMS (yellow): Scan of serial I/O module in progress
Reserved for future use
MPP running (as indicated by mi
output)
MPP on line
Microprocessor running (as indicated by microprocessor address
strobe monitoring c
Scan of I/O modules in progress
Backup batteries (1 or 2) healthy
ircuit)
croprocessor supervisory watchdog
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Figure 2-1 Backplane bus interconnections
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SC300E MPP Processor Module
UNIT
ID
UNIT
ID
0
1
2
3
UNIT
ID
0
1
2
3
0
1
2
3
Figure 2-2 MPP Related back
plane connectors
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Figure 2-3 MPP Block diagram
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SC300E MPP Processor Module
THEORY OF OPERATION
SC300E system overview
A block diagram showing the signal flow between the main functional areas of the MPP is
shown in Figure 2-3 . External communication is via the chassis backplane wiring as
summarised in Figure 2-1
.
All SC300E input and output modules interface to three isolated I/O communications buses
(shown collectively as the Processor-I/O Bus in Figure 2-1 ), each being controlled by one of
the
MPPs.
At the input modules, field signals are filtered and then split, via isolating circuitry, into three
identical, signal processing paths. Each path is controlled by a microcontroller that
coordinates signal path processing, testing and signal status reporting to its respective M
via one of the I/O communications buses.
Each of the MPPs communicates with its neighbours via read only, serial communications
links (Figure 2-4).
PP,
Figure 2-4 Read serial communications only links
The MPPs synchronise at least once per application logic execution cycle, and each reads the
input, output and diagnostic status of its neighbours. Each MPP correlates and corrects its
memory image of the current state of the system using a 2-oo-3 software vote, logging any
discrepancies found in a local diagnostic history table.
Each MPP then executes its programmed application logic and sets its respective outputs, via
the
I/O communications bus, to the required state.
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Commanded output states are received by an output module’s microcontrollers which, using
2-oo-3 hardware voters, set the outputs to the field. Any discrepancy between a commanded
output state and the field output is detected by the microcontrollers and reported to the
appropriate MPP
OFFLINE/STARTUP DIAGNOSTICS
When a SC300E’s MPPs are f
•
Initialisation of all SRAM
•
Memory configuration and size checks
•
RTTS and application logic copied to SRAM
•
All program checksums recalculated and checked
•
Configuration and checksums of neighbouring MPPs read and confirmed
•
Initialisation of synchronisation registers
•
Synchronisation registers of neighbouring processors read
A processor will then pause, waiting for the other two MPPs to complete their startup
diagnostics.
irst powered up, the following diagnostic routines are executed:
At powerup a SC300E system must have three healthy MPPs, otherwise the startup
diagnostics will prevent execution of the system application logic.
In the event of a processor failing a replacement MPP can be brought online using a warm start
command. Warm start commands can be issued from a TriBuild workstation or by use of an
application logic assigned input. A newly installed MPP will execute its startup diagnostics,
monitor the running MPP’s synchronisation registers and await a warm start command. At this
point checksums will be
neighbours and commences execution of its application logic.
confirmed and the new MPP acquires I/O data tables from its
Online/continuous diagnostics
All memory reads and writes are automatically checked for errors by the MPPs' error checking
and
correcting circuitry. Single memory errors are detected and corrected, all multiple errors
are flagged.
Software Implemented Fault Tolerant (SIFT) votes the data tables between the MPPs using a
majority
'read neighbour's data' cycle.
Corrected memory errors are logged in diagnostic history tables. These tables can be
accessed
errors are detected an
vote algorithm, any errors being logged and corrected by the processors during their
by
application logic functions and be used to generate system alarms. If multiple
MPP will be halted. An MPP’s I/O hot repair task regularly scans all
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configured I/O slots to determine their status. All I/O modules have identity type registers
which allow the hot repair task to confirm the status of all fitted modules.
SC300E MPP Processor Module
Circuit de
The block diagram (Figure 2-3 ) shows the main functional areas of the MPP circuit. Overall
control of the circuit is by the microprocessor. At a lower level, individual parts of the circuit are
controlled
tails
by
Programmable logic (PALs) and peripheral devices.
Power supplies
The two 5.4Vdc supplies from the chassis PSUs are fused on entry to the MPP by 3A fuses
F1 and F2 respectively. Both supplies are then fed via three pairs of auctioneering diodes to
three 5V
The 12V
regulators. Each of the regulator outputs feeds a separate area of the MPP circuit.
outputs from the chassis PSUs are not used by the MPP.
System clock and supervisory circuits
The 32MHz system clock to the microprocessor is derived from a crystal oscillator. 16MHz
and 8MHz clock signals for use elsewhere in the system are obtained by dividing the system
clock.
A microprocessor supervisory chip operates as follows:
•
Generates a reset signal to the microprocessor during a cold start
•
Monitors the charge state of the backup batteries and drives the Battery LED on the
front panel
•
Generates the basic watchdog signal. This signal controls the Run LED on the front
panel.
A secondary watchdog circuit monitors the Address Strobe pulses from the
microprocessor. Its output controls the Health LED on the
front panel.
Memory
The MPP has eight 32-pin DIL sockets used to mount the EPROMs which contain the
operating system RTTS.
Ten 32-pin sockets are provided for byte-wide SRAM in two banks of five. SRAM is supported by
one or two backup batteries in the absence of an external power supply.
Error detection and correction (EDC)
A 32-bit EDC processor detects and corrects single bit errors during reads from SRAM.
Dual port controller
The dual port controller controls accesses to SRAM by the Microprocessor and the
Communicator.
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SC300E
Configuration registers
The MPP is configured by setting 8-bit DIP switches S1 and S2 as listed in Table 2-3 and
Table 2-4.
Chassis address link settings
The correct link combination for the main chassis is shown in Figure 2-5
The
physical locations of the chassis address setting links are indicated by small triangles in
columns ‘b’ and ‘c’ of areas ‘d’ in Table 2-2. On the chassis backplane and in the links are
identified as UNIT ID0 to UNIT ID3.
.
Figure 2-5 Main chassis link address settings
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SC300E MPP Processor Module
SUPPLEMENTARY INFORM
Table 2-2. Configuration register switch settings
Switch
S1
S2
Element
1
2
3
4
5to
7
8
1
2
3
Cross load
Cross load from 2 Cross load from 0 (Default)
St
Load from EPROM
Baud rate (Default see Table
4)
Copy RTTS to RAM (Default) Do not copy
No shadow
Not used
Not used
ATION
Switch ON
art RTTS (Default)
Shadow (Default)
Function Selected
Switch OFF
No cross load (Default)
Start Monitor
No load (Default)
Baud rate (Table 4)
Not used (Default)
Not
used (Default)
Switch position
S 1-5
OFF
OFF
OFF
ON ON
OFF
ON
S-1-6
ON
4
5to
7 Baud rate (Table 4)
8
Table 2-3. Configuration register switch settings for baud rate
S 1-7
OFF
OFF
OFF
OFF
OFF
ON
OFF
ON
No set
Not used
Baud rate
957 Monitor S 2-5
9600
9600
ON
9600
9600
ON ON
4800
2400
ON
Switch positi
OFF
OFF
ON
OFF
S 2-6
OFF
OFF
OFF
OFF
Set memory to CCH (Default)
Baud rate (Default see Table 4)
Not used (Default)
on
S 2-7
OFF
OFF
OFF
OFF
ON
ON
Baud rate
CSI/O OFF
9600 (Default ON
9600
9600
9600
4800
2400
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Table 2-3. Configuration register switch settings for baud rate
Switch position
S 1-5
OFF
ON ON ON
S-1-6
S 1-7
ON ON
The diagram below (Figure 2-6 ) shows S1 in its default condition, i.e. elements
3, 5, 6, 7 and 8 all ON (CLOSED), and, elements 1, 2 and 4 all OFF (OPEN).
Baud rate
957 Monitor
1200
19200 (Defaul
S 2-5
t)
ON ON ON
NOTE
Switch position
S 2-6
OFF
ON ON
S 2-7
Baud rate
CSI/O OFF
1200
19200
Figure 2-6 Switch S1 shown in Default condition
Table 2-4. Pinout for
Pin
1
2
3 TxD
4
5
Signal
Unused
RxD
DTR
0V
front panel diagnostic
Pin
6
7 RTS
8 CTS
9
- -
Signal
DSR
Unused
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SC300E MPP Processor Module
Figure 2-7 Diagnostic port pinouts
Table 2-5. Pinout for rear backplane diagnostic Port ‘g’
Pin
1
3 TxD
5
7 RTS
9 CTS
11
13
15
17
19
Signal
DSR
nc
RxD
0V
nc
nc
nc
Pin
2
4
6
8
10
12
14
16
18
20
Signal
nc
nc
nc
nc
nc
nc
DTR
nc
nc
nc
21
23
25
nc
nc
nc
22
24
26
nc
nc
nc
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Figure 2-8 Rear backplane diagnostic port
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SERVICING
SCOPE
The MPP is not field-repairable.
replacement of SRAM backup batteries, and the total replacement of faulty MPPs. Spare keys
ar e av ail able.
Faulty MPPs should be returned for repair.
Before a spare MPP is fitted, ensure that both the positions of the links and the types of pre
programmed device are identical to those on the MPP that is being replaced.
While MPPs are out of the chassis it is good practice always to leave the front panel
keyswitch in the RESET position.
Do not attempt to repair a fault by replacing blown fuses F1 or F2. The fault that caused the
fuse(s)
to
fail will remain.
Field servicing operations are confined to the routine
CAUTION 1
-
CAUTION 2
Spare MPPs should normally contain a full complement of pre-programmed devices. Should it
be necessary to transfer pre-programmed devices (EPROMs only) from a faulty MPP to a good
one, use the normal handling procedures for electrostatically sensitive devices and take
extreme care not to bend the IC pins.
DIAGNOSIS
A faulty MPP will be apparent by the abnormal state of its front panel LEDs. This may be
accompanied by audible alarms etc.
Note that in normal operation, the On Line, Run and Health LEDs will be on and the Test LED
will flicker at a rate determined by the preset ladder scan rate.
CONFIGURATION
Configuration is via links on the board.
Module Link settings
Link settings are given in Table 3-1
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SC300E MPP Processor Module
The locations of the links are shown in general view showing link locations.
Fit Link
LK1
LK1
LK2
LK3
LK3
LK4
LK5
LK5
LK6
LK7
LK8
Table 3-1. Module link settings
Across Pins
1
2&3
Fit link
1&2
2&3
1 & 2 and 3 & 4
1&2 4Mbit RAM devices
2&3 1Mbit Ram devices
1 & 2 and 3 & 4
Fit link
1&2
& 2 Data error monitoring
8MHz clock
RTS-CTS loopback
5ms real time clock
10ms real time clock
Loopback operation
Loopback operation
Write operations to flash memory
1Mbit or 2Mbit EPROMs
For Condition
Factory default
Yes
No
Yes
No
Yes
No (test use only)
No
Yes
No (test use only)
No
Yes
LK8
LK9
LK10
LK11
LK12
LK13
LK14
LK14
LK14
3&4
1 & 2 and 3 & 4
Fit link
Fit all links
Fit link
Fit link
Position 1 Logic 5V
Posi
Position 3
tion 2 Battery backup enabled
<1Mbit EPROMs
Loopback operation
Slow EPROM (<70ns)
Loopback operation
CPU self test
Supervisory watchdog
Battery backup disabled
No
No (test use o
Yes
No (test use only)
Yes
No
Not applicable on
Modules
and above
No
Yes
at
nly)
Rev 04
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SC300E
REMOVAL AND REPLACEMENT
Removal
CAUTION
To prevent battery drain in storage, the backup batteries fitted to new modules have insulation
tabs fitted to their positive terminal.
LK14 to Position 2 to enable battery backup.
link
Remove these tabs before installing new modules. Ensure
The following applies to both faulty and non-faulty MPPs:
1.
Turn the front panel keyswitch to RESET.
2.
Remove the MPP.
Replacement and warm start with two MPPs already running
1.
2.
3.
4.
Turn the new MPPs front panel keyswitch to RESET.
Insert the new MPP.
Turn the new MPPs front panel keyswitch to RUN. This will initiate a self test
procedure.
Wait for the following LED states to stabilise on the MPP front panel:
RUN -on
ON LINE -
PROGRAM
on
-off
5.
TEST
-on
HEALTH -on
I/O SCAN -
BATTERY
SI/O COMMS-off
At a TriBuild workstation:
a)
b)
c)
-off
From the TriBuild main menu select View.
From the View drop-down menu select Diagnostics.
From the Diagnostics drop-down menu select Warm Start Processor.
on
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6.
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The new MPP is on line when all three sets of MPP LEDs indicate the same.
SC300E MPP Processor Module
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SC300E
BATTERY REPLACEMENT
Fresh batteries will sustain SRAM for a total of about six months (either in one long stretch, or
in several shorter stretches). The backup batteries should be replaced where it is known that
the total battery drain period is approaching six months or once every five years (whichever
occurs first).
If the SC300E System is Operating
1.
2.
3.
4.
5.
Remove one of the three MPPs.
Remove and safely dispose of both batteries.
Wait about 5 minutes for any capacitance in the system to discharge.
Ensuring the correct polarity Figure 1-1,fit the new batteries.
Replace the MPP and perform a war
m start.
6.
Repeat the above procedure for each of the remaining MPPs in turn.
If the SC300E System is Not Operating
If the system is not powered up, the data in SRAM is being supported by the backup batteries.
To
preserve this data it is important not to remove both batteries at once.
If only one battery is fitted, install a new battery in the vacant slot before removing the old
battery.
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SERVICE SUPPORT
SERVICE SUPPORT
Spare parts and technical advice can be obtained from your local area offices.
LIST OF SPARES
Circuit ref
B1, B2
Model No.
AB002LGX
Details
3V Lithium batteries (set of
two)
NOTE
3MPPs would require three
sets of batteries
: A chassis containing
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