RICHTEK RT9263CCX5, RT9263ECX5 Datasheet

Preliminary

RT9263

High Efficiency, Low Supply Current,

Step-up DC/DC Converter

General Description

The RT9263 is a compact, high efficient, step-up

DC/DC converter with an adaptive current mode

PWM control loop, providing a stable and high

efficient operation over a wide range of load

currents. It operates in both continuous and

discontinuous current modes in stable waveforms

without external compensation.

The low start-up input voltage below 1V makes

RT9263 suitable for 1 to 4 battery cell applications

providing up to 400mA output current. The 550KHz

high switching rate minimized the size of external

components. Besides, the 17µA low quiescent

current together with high efficiency maintains long

battery lifetime.

Ordering Information

RT9263

 

Package type
X5 : SOT89-5

Operating temperature range

C: Commercial standard

C : Chip enable control
E : Driver for external power devices

Typical Application Circuit

Features

z

1.0V Low Start-up Input Voltage

z

High Supply Capability to Deliver 3.3V 100mA

with 1V Input Voltage

z

17µµµµA Quiescent (Switch-off) Supply Current

z

90% Efficiency

z

550KHz Fixed Switching Rate

z

Providing Flexibility for Using Internal and

External Power Switches

z

SOT89-5 Package

Applications

PDA

z

Portable Instrument

z

DSC

z

Pin Configurations

Part Number Pin Configurations

321

321

TOP VIEW

1. CE

2. VDD

3. FB

4. LX

5. GND

TOP VIEW

1. EXT

2. VDD

3. FB

4. LX

5. GND

RT9263CCX5

(Plastic SOT89-5)

RT9263ECX5

(Plastic SOT89-5)

54

54

+

V

IN

VDD

CE

RT9263CCX5

GND FB

LX

100pF

R1

1.6M

R2

980K

L1

4.7µH

D1

1N5819

C2
1µF

+

C1
100µF

100µF

3.3V
V

OU T1

Fig. 1 RT9263CCX5 Typical Application for Portable Instruments below 400mA

DS9263-00 November 2001 www.richtek-ic.com.tw

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RT9263

Preliminary

V

IN

3. 3/ 5V
V

+

VDD

RT9263ECX5

GND FB

100p F

LX

EXT

R1

1.6M

R2

980K

Q1
NMOS

L1

4.7µH

D1

1N58 19

C2
1µF

+

C1
100µF

100µF

3.3V
V

OU T1

Fig. 2 0.4A ~ 1A Output Current Application

L1

+

IN

100µF

VDD

RT9263ECX5

GND FB

10µH

EXT

LX

Q1
NMOS

0.1µF

Rm

0.05~0.1

D1

15V
V

+

OU T1

C1
100µF

R1

2.2M

R2

C2

200K

Ω

1µF

Fig. 3 High Voltage Application (Rm should be added when IL > 100mA)

3.3/5V
V

IN

Chip Ena bl e

+

100µF

VDD

RT9263CCX5

CE GND FB

L1

10µH

LX

Q1
NMOS

0.1µF

D1

R1

2.2M

R2

200K

C2
1µF

15V
V

+

C1
100µF

Fig.4 High Voltage Application with Shutdown Control

OU T1

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Function Block Diagram

Preliminary

RT9263

VDD

FB

CE

VDD

FB

1.25V

1. 25 V

RT9263CCX5

_

Loop Control Circuit

+

RT9263ECX5

_

Loop Control Circuit

+

LX

Q1
NMOS

R1

GND

EXT

LX

Q1
NMOS

R1

GND

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RT9263

Pin Description

Preliminary

Pin No.

Pin Name

Pin Function

RT9263CCX5 RT9263ECX5

Output pin for driving external NMOS or NPN

-- 1 EXT

1--CE

When driving an NPN, a resistor should be added for limiting base

Chip enable

RT9263CCX5 gets into shutdown mode when CE pin set to low.

22VDD

33FB

Input positive power pin of RT9263

Feedback input pin

Internal reference voltage for the error amplifier is 1.25V.

44LX

55GND

Pin for switching

Ground

Absolute Maximum Ratings

z Supply Voltage -0.3V to 6V

z LX Pin Switch Voltage -0.3V to (VDD + 0.8V)

z Other I/O Pin Voltages -0.3V to (VDD + 0.3V)

z LX Pin Switch Current 2.5A

z EXT Pin Driver Current 30mA

z Power Dissipation, P

SOT89-5 0.5W

• Package Thermal Resistance

SOT89-5, θ

z Operating Junction Temperature 150°C

z Storage Temperature Range -65°C ~ +150°C

JA

@ TA = 25°C

D

300°C/W

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Preliminary

Electrical Characteristics

(VIN = 1.5V, VDD set to 3.3V, Load Current = 0, TA = 25°C, unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Units

RT9263

Start-UP Voltage

Operating VDD Range V

No Load Current I (VIN)

Switch-off Current I (VDD) I

Shutdown Current I (VIN)

Feedback Reference Voltage

Switching Rate

Maximum Duty

LX ON Resistance

Current Limit Setting

EXT ON Resistance to VDD

EXT ON Resistance to GND

Line Regulation

Load Regulation

CE Pin Trip Level

Temperature Stability for FB, LFB, LBI

Thermal Shutdown

Thermal Shutdown Hysterises

V

ST

DD

I

NO LOAD

SWITCH OFF

I

OFF

V

REF

F

S

D

MAX

I

LIMIT

∆V

LINE

∆V

LOAD

T

S

T

SD

∆T

SD

IL = 1mA

Start-up to I

VIN = 1.5V, V

> 250µA

DD1

OUT

= 3.3V

VIN = 6V

CE Pin = 0V, VIN = 4.5V

Close Loop, VDD = 3.3V

VDD = 3.3V

VDD = 3.3V

VDD = 3.3V

VDD = 3.3V

VDD = 3.3V

VDD = 3.3V

VIN = 1.5 ~ 2.5V, IL = 1mA

VIN = 2.5V, IL = 1 ~ 100mA

VDD = 3.3V

-- 0.98 1.05 V

0.8 -- 6 V

-- 47 --

-- 17 --

-- 0.1 1

1.225 1.25 1.275 V

-- 550 -- KHz

-- 92 -- %

-- 0.25 --

-- 2 --

-- 40 --

-- 30 --

-- 10 --

-- 0.25 --

0.2 0.8 1.4 V

Guaranteed by Design -- 50 --

Guaranteed by Design -- 165 --

Guaranteed by Design -- 10 --

µA

µA

µA

Ω

A

Ω

Ω

mV/V

mV/mA

ppm/

°C

°C

°C

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RT9263

I

(

A)

µ

Typical Operating Charateristics

Preliminary

Efficiency

V

= 3.3V ; TA = 25°C

OUT

No Load Current

90

80

70

60

50

( A)

40

DD

I

30

20

10

Refer to Application Cir cuit Fig.1

0

1 1.2 1.5 2 2.5 3

Input Voltage (V)

TA = 25°C
V

OUT

= 3.3V

Efficiency

V

= 5.0V; TA = 25°C

OUT

No Load Current

140

T

120

100

80

60

DD

40

20

Refer to Application Cir cuit Fig.1

0

1 1.2 1.5 2 2.5 3 4

Input Voltage (V)

V

A

OUT

= 25°C

= 5.0V

1.4

Start Up Voltage

TA = 25°C
V

= 3.3V

OUT

1.3

1.2

1.1

1.0

Input Voltage (V)

0.9

Refer to Application Cir cuit Fig.1

0.8
020406080100

I

(mA)

I

(mA) in constant resistance load

LOAD

LOAD

1.25

TA = 25°C

1.20

V

OUT

1.15

1.10

1.05

1.00

0.95

Input Voltage (V)

0.90

0.85

0.80

Refer to Application Circuit Fig.1

0 25 50 75 100

Start Up Voltage

= 5.0V

I

I

(mA) in constant resistance load

LOAD

LOAD

(mA)

www.richtek-ic.com.tw DS9263-00 November 2001

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Preliminary

Application Note

Output Voltage Setting

Referring to application circuits Fig.1 to Fig.4, the

output voltage of the switching regulator (V

be set with Eq.1.

1OUT ×+=

2R

V25.1)

1R

1(V

Feedback Loop Design

Referring to application circuits Fig.1 to Fig.4, The

selection of R1 and R2 based on the trade-off

between quiescent current consumption and

interference immunity is stated below:

• Follow Eq.1

• Higher R reduces the quiescent current (Path

current = 1.25V/R2), however resistors beyond

5MΩ are not recommended.

• Lower R gives better noise immunity, and is less

sensitive to interference, layout parasitics, FB

node leakage, and improper probing to FB pins.

• A proper value of feed forward capacitor parallel

with R1 on Fig.1 to Fig.4 can improve the noise

immunity of the feedback loops, especially in an

improper layout. An empirical suggestion is around

100pF ~ 1nF for feedback resistors of MΩ, and

10nF ~ 0.1µF for feedback resistors of tens to

hundreds KΩ.

OUT1

) can

Eq.1

RT9263

PRECAUTION 1: Improper probing to FB pin will

cause fluctuation at V

and system chips because V

to an over-rated level due to unexpected interference

or parasitics being added to FB pin.

PRECAUTION 2: Disconnecting R1 or short circuit

across R2 may also cause similar IC damage as

described in precaution 1.

PRECAUTION 3: When large R values were used in

feedback loops, any leakage in FB node may also

cause V

voltage fluctuation, and IC damage. To

OUT1

be especially highlight here is when the air moisture

frozen and re-melt on the circuit board may cause

several µA leakage between IC or component pins.

So, when large R values are used in feedback loops,

post coating, or some other moisture-preventing

processes are recommended.

Prober Parasitics

_

Q

+

. It may damage RT9263

OUT1

may drastically rise

OUT1

V

OU T1

R1

FB Pin

R2

For applications without standby or suspend modes,

lower values of R1, and R2 are preferred. For

applications concerning the current consumption in

standby or suspend modes, the higher values of R1,

and R2 are needed. Such “high impedance feedback

loops” are sensitive to any interference, which require

careful layout and avoid any interference, e.g.

probing to FB pins.

Layout Guide

• A full GND plane without gap break.

• V

to GND noise bypass – Short and wide

OUT1

connection for C2 to Pin2 and Pin5.

• V

to GND noise bypass – Add a 100µF capacitor

IN

close to L1 inductor, when VIN is not an idea

voltage source.

• Minimized FB node copper area and keep far

away from noise sources.

• Minimized parasitic capacitance connecting to LX

and EXT nodes, which may cause additional

switching loss.

DS9263-00 November 2001 www.richtek-ic.com.tw

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RT9263

Package Information

Preliminary

Symbol

D

D1

C

C1

e e

b

b1 b

B

A

A

H

Dimensions In Millimeters Dimensions In Inches

Min Max Min Max

A 1.400 1.600 0.055 0.063

b 0.360 0.520 0.014 0.020

B 2.400 2.600 0.094 0.102

b1 0.406 0.533 0.016 0.021

C -- 4.250 -- 0.167

C1 0.800 -- 0.031 --

D 4.400 4.600 0.173 0.181

D1 -- 1.700 -- 0.067

e 1.400 1.600 0.055 0.063

H 0.380 0.430 0.014 0.017

5-Lead SOT-89 Surface Mount

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Preliminary

RT9263

DS9263-00 November 2001 www.richtek-ic.com.tw

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RT9263

Preliminary

RICHTEK TECHNOLOGY CORP.

Headquarter

6F, No. 35, Hsintai Road, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: [phone] Fax: [phone]

www.richtek-ic.com.tw DS9263-00 November 2001

RICHTEK TECHNOLOGY CORP.

Taipei Office (Marketing)

8F-1, No. 137, Lane 235, Paochiao Road, Hsintien City

Taipei County, Taiwan, R.O.C.

Tel: [phone] Fax: [phone]

Email: [e-mail]

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