Richtek RT9173D Schematic [ru]

RT9173D

Cost-Effective, Peak 3A Sink/Source Bus Termination Regulator

General Description

The RT9173D is a simple, cost-effective and high-speed

linear regulator designed to generate termination voltage

in double data rate (DDR) memory system to comply with

the JEDEC SSTL_2 and SSTL_18 or other specific

interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices

requirements. The regulator is capable of actively sinking

or sourcing continuous 2A or up to 3A transient peak

current while regulating an output voltage to within 40mV.

The output termination voltage cab be tightly regulated to

track 1/2V

the desired output voltage can be pro-grammed by externally

forcing the REFEN pin voltage.

The RT9173D also incorporates a high-speed differential

amplifier to provide ultra-fast response in line/load transient.

Other features include extremely low initial offset voltage,

excellent load regulation, current limiting in bi-directions

and on-chip thermal shut-down protection.

The RT9173D are available in the SOP-8 (Exposed Pad)

surface mount packages.

by two external voltage divider resistors or

DDQ

Features

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Ideal for DDR-I, DDR-II and DDR-III V

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z Sink and Source Current

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` 2A Continuous Current

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` Peak 3A for DDRI and DDRII

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` Peak 2.5A for DDRIII

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z Integrated Power MOSFETs

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z Generates Termination Voltage for SSTL_2,

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Applications

TT

SSTL _18, HSTL, SCSI-2 and SCSI-3 Interfaces

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z High Accuracy Output Voltage at Full-Load

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z Output Adjustment by Two External Resistors

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z Low External Component Count

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z Shutdown for Suspend to RAM (STR) Functionality

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with High-Impedance Output

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z Current Limiting Protection

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z On-Chip Thermal Protection

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z Available in SOP-8 (Exposed Pad) Packages

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z V

and V

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IN

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z RoHS Compliant and 100% Lead (Pb)-Free

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No Power Sequence Issue

CNTL

Applications

Ordering Information

RT9173D

Package Type
SP : SOP-8 (Exposed Pad-Option 1)

Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)

Note :

Richtek products are :

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

z Desktop PCs, Notebooks, and Workstations

z Graphics Card Memory Termination

z Set Top Boxes, Digital TVs, Printers

z Embedded Systems

z Active Termination Buses

z DDR-I, DDR-II and DDR-III Memory Systems

Pin Configurations

(TOP VIEW)

GND

8

NC

7

NC

6

9

VCNTL

5

NC

VIN

GND

REFEN

VOUT

2

3

4

SOP-8 (Exposed Pad)

DS9173D-07 April 2011

www.richtek.com

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RT9173D

Typical Application Circuit

V

= 3.3V

CNTL

VIN = 2.5V/1.8V/1.5V

2N7002

EN

R1 = R2 = 100kΩ, RTT = 50Ω / 33Ω / 25Ω

C

OUT(MIN)

CSS = 1μF, CIN = 470μF (Low ESR), C

Test Circuit

= 10μF (Ceramic) + 1000μF under the worst case testing condition

R

TT

R

1

R

C

2

CNTL

REFEN

SS

= 47μF

VIN

RT9173D

GND

GND

VCNTL

VOUT

C

C

CNTL

IN

C

OUT

2.5V/1.8V/1.5V 3.3V

1.25V/0.9V/0.75V

VIN

REFEN

VCNTL

RT9173D

GND

VOUT

V

OUT

Figure 1. Test Circuit for Typical Operating Characteristics Curves

DS9173D-07 April 2011www.richtek.com

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Functional Pin Description

RT9173D

VIN (Pin 1)

Input voltage which supplies current to the output pin.

Connect this pin to a well-decoupled supply voltage. To

prevent the input rail from dropping during large load

transient, a large, low ESR capacitor is recommended to

use. The capacitor should be placed as close as possible

to the VIN pin.

GND [Pin 2, Exposed pad (9)]

Common Ground (Exposed pad is connected to GND).

The GND pad area should be as large as possible and

using many vias to conduct the heat into the buried GND

plate of PCB layer.

REFEN (Pin 3)

Reference voltage input and active low shutdown control

pin. Two resistors dividing down the VIN voltage on the pin

to create the regulated output voltage. Pulling the pin to

ground turns off the device by an open-drain, such as

2N7002, signal N-MOSFET.

VOUT (Pin 4)

Regulator output. VOUT is regulated to REFEN voltage

that is used to terminate the bus resistors. It is capable of

sinking and sourcing current while regulating the output

rail. To maintain adequate large signal transient response,
typical value of 1000μF AL electrolytic capacitor with 10μF

ceramic capacitors are recommended to reduce the effects

of current transients on VOUT.

VCNTL (Pin 6)

VCNTL supplies the internal control circuitry and provides

the drive voltage. The driving capability of output current is

proportioned to the VCNTL. Connect this pin to 3.3V bias
supply to handle large output current with at least 10μF

capacitor from this pin to GND.

NC (Pin 5, 7, 8)

No Internal Connect.

Function Block Diagram

REFEN

VCNTL

Current Limit

Thermal Protection

+

EA

-

GND

VIN

VOUT

DS9173D-07 April 2011

www.richtek.com

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RT9173D

Absolute Maximum Ratings (Note 1)

z Input Voltage, V

z Control Voltage, V

z Power Dissipation, P

---------------------------------------------------------------------------------------------------- 6V

IN

---------------------------------------------------------------------------------------------- 6V

CNTL

@ TA = 25°C

D

SOP-8 (Exposed Pad) ---------------------------------------------------------------------------------------------- 1.33W

z Package Thermal Resistance (Note 2)

SOP-8 (Exposed Pad), θJA---------------------------------------------------------------------------------------- 75°C/W

SOP-8 (Exposed Pad), θJC---------------------------------------------------------------------------------------- 28°C/W

z Junction Temperature ----------------------------------------------------------------------------------------------- 125°C

z Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------- 260°C

z Storage Temperature Range --------------------------------------------------------------------------------------- –65°C to 150°C

z ESD Susceptibility (Note 3)

HBM (Human Body Mode) ----------------------------------------------------------------------------------------- 2kV

MM (Machine Mode) ------------------------------------------------------------------------------------------------ 200V

Recommended Operating Conditions (Note 4)

z Input Voltage, V

z Control Voltage, V
z Ambient Temperature Range -------------------------------------------------------------------------------------- −40°C to 85°C

z Junction Temperature Range -------------------------------------------------------------------------------------- −40°C to 125°C

---------------------------------------------------------------------------------------------------- 2.5V to 1.5V ± 5%

IN

---------------------------------------------------------------------------------------------- 5V or 3.3V ± 5%

CNTL

Electrical Characteristics

(V

= 2.5V/1.8V/1.5V, V

IN

Parameter Symbol Test Conditions Min Typ Max Unit

Input

V

Operation Current I

CNTL

Standby Current (Note 5) I

Output (DDR / DDR II / DDR III)

Output Offset Voltage (Note 6) VOS I

Load Regulation (Note 7) ΔV

Protection

Current limit I

Thermal Shutdown Temperature TSD 3.3V ≤ V

Thermal Shutdown Hysteresis ΔTSD 3.3V ≤ V

REFEN Shutdown

Shutdown Threshold

CNTL

= 3.3V, V

= 1.25V/0.9V/0.75V, C

REFEN

I

CNTL

STB Y

LOAD

VIN = 2.5V/1.8V/1.5V -- 3.4 -- A

LIM

= 0A -- 1 2.5 mA

OUT

V

REFEN

R

LOAD

= 0A −20 -- +20 mV

OUT

I

= +2A

OUT

= −2A

I

OUT

VIH Enable 0.6 -- --

Shutdown -- -- 0.2

V

IL

= 10μF (Ceramic), T

OUT

< 0.2V (Shutdown),

= 180Ω

= 25°C, unless otherwise specified)

A

-- 50 90 μA

−20 -- +20 mV

≤ 5V 125 170 -- °C

CNTL

≤ 5V -- 35 -- °C

CNTL

V

DS9173D-07 April 2011www.richtek.com

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RT9173D

Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for

stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended

periods may remain possibility to affect device reliability.

Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective thermal conductivity test board (4 Layers,

2S2P) of JEDEC 51-7 thermal measurement standard. The case point of θ

Pad) package.

Note 3. Devices are ESD sensitive. Handling precaution recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

Note 5. Standby current is the input current drawn by a regulator when the output voltage is disabled by a shutdown signal on

Note 6. V

REFEN pin (V

offset is the voltage measurement defined as V

OS

< 0.2V). It is measured with VIN = V

IL

= 5V.

CNTL

subtracted from V

OUT

Note 7. Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load

regulation in the load range from 0A to 2A.

is on the expose pad for SOP-8 (Exposed

JC

.

REFEN

DS9173D-07 April 2011

www.richtek.com

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