
Contents
SPECIFICATIONS ���������������������������������������������������������������������������������������������������������������� 1
CIRCUIT DESCRIPTION ������������������������������������������������������������������������������������������������������ 2
BLOCK DIAGRAM ��������������������������������������������������������������������������������������������������������������� 9
SCHEMATIC ��������������������������������������������������������������������������������������������������������������������� 10
MCU Unit ����������������������������������������������������������������������������������������������������������������������������������������������� 10
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RF UNIT ������������������������������������������������������������������������������������������������������������������������������������������������� 11
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ADJUSTMENT ������������������������������������������������������������������������������������������������������������������� 14
PCB VIEW �������������������������������������������������������������������������������������������������������������������������� 16
RF BOARD TOP VIEW ������������������������������������������������������������������������������������������������������������������������� 16
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RF BOARD BOTTOM LAYER ������������������������������������������������������������������������������������������������������������� 17
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CONTROL BOARD VIEW ������������������������������������������������������������������������������������������������������������������� 18
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BILL OF MATERIALS ��������������������������������������������������������������������������������������������������������� 19

SPECIFICATIONS
Receiver: about 600mA(max.)
Double conversion superheterodyne
Intermediate Frequency (1st / 2nd)
Maximum Frequency Deviation
Audio Distortion (at 60% modulation)
Page 1

The receiver utilizes double conversion. The first IF is 38.
MHz and the second IF is 450kHz. T he
first local oscillator signal is supplied from the PLL circuit.
The PLL circuit in the transmitter generates t
he necessary frequencies. Fig. 1 shows the frequencies.
Fig. 1 Frequency configuration
The receiver is double conversion super heterodyne, designed to operate in the frequency range of
The frequency configuration is
An incoming signal from the antenna is applied to an RF
) after passing through a
are off) and a band pass filter
and varactor diodes: D207,
), the signal is filtered through a band
eliminate unwanted signals before it is passed to the first
The voltage of these diodes are controlled by tra cki
) center frequency of the band
Fig. 2 Receiver section configuration
CIRCUIT DESCRIPTION
Page 2

The signal from the RF amplifier is heterodyned with the
first local oscillator signal from the PLL
(1st IF) signal. The first IF signal is
then fed through one pair of monolithic crystal filter (MCF :
) to further remove spurious signals.
(FM processing IC). The signal is
with a second local oscillator signal within
The second IF signal is then fed
through a 450kHz ceramic filter (Wid
further eliminate unwanted signals before it is amplified
Wide/Narrow Switching Circuit
is used to switch between ceramic filters. When the
s high, the ceramic filter SW diodes (D20
CF201 to turn on to receive a Wide
, the ceramic filter SW diodes
Wide/Narrow Switching Circuit
The detection signal from IF IC (
) for characterizing the signal
It is also amplified by entering
and the resulting signal goes to the
The AFO output level is adjusted by the D/A converter. The
D/A converter is input to the audio
(U506).The AF signal from (U506)
between the internal speaker and speaker jack (J502) output.
Page 3

ion output from the FM IF IC (
through a noise amplifier (
). The CPU controls squelch according
level. The signal from the RSSI
pin of U200 is used for S
The electric field strength of
signal can be kno wn before the SQIN voltage is
input to the CPU, and the scan stop speed is improved.
PLL frequency synthesizer
The PLL circuit generates the f irst local oscillator
signal for reception and the RF signal for transmission.
The frequency step of the PLL circuit is 5 or 6.25kHz. A
MHz reference oscillator signal is divided
fixed counter to produce the 5 or 6.25kHz reference frequency.
oscillator (VCO) output signal
programmable counter. The divided signal is compared
in phase with the 5 or 6.25kHz reference signal in
phase comparator is filtered through a low
passed to the VCO to control the oscillator frequency. (See
The operating frequency is generated by Q
controlled by applying the VCO control voltage, obtained
comparator, to the varactor diodes (D
andD222in transmit mode and D
The TX/RX pin is set high in receive mode causing Q
set low in transmit mode. The outputs from Q
and sent to the RF amplifiers. (See Fig.
goes low, and Q108 turns on. Q
. During transmission, the R
Page 4

turns on and a voltage is applied to
CPU in the control unit monitors the PLL (
signal directly. When the PLL is unlocked
the PLL LD signal goes low. The CPU de tects this signal
low, no voltage is applied to 8
T, and no signal is transmitted. (See Fig.
The transmitter circuit produces and amplifies the desired
frequency directly. It FM
means of a varicap diode.
The transmit output signal f rom the VCO passes through
the transmission/reception selection diode
. The amplified signal goes to
frequency harmonic components,
and the resulting signal is transmitted through the
antenna terminal. (See Fig. 8.)
The automatic transmission power control (APC) circuit
of a final amplifier output with a
) and applies a voltage to
generated by the D/A converter
(U505) with the detection output
204generates the voltage to
andQ216and stabilizes transmission output.
The APC circuit is configured to protect over current of
due to fluctuations of the
Page 5

end and to stabilize transmission output at voltage and temperature
The CPU carries out the following tasks (See Fig. 10.):
1) Controls the WIDE, NARROW, TX/RX outputs.
) Controls the display unit.
).4) Controls the D/A converter (
modulation and transmission power.
EEPROM contains adjustment data. The CPU (
serial data lines. (See F
The CPU (IC101) controls the display LCD and LEDs. When power is on, the
to control the LCD illumination and key backlight LEDs.
The brightness function is controlled by the swit
Page 6

DCS and CTCSS data is output through 42 PIN of CPU. The signal passes t
and the signal attained goes into the D/A converter (U505). The high speed data of DTMF/2T/5T Tone is
output through 58 PIN of CPU, The signal passes through low
pass CR filter, providing TX and SP output
processed IDC after amplified by a U504(B/4). The signal then passes through a
low-pass filter (separation filter) U504 (C/4 and D/4), and filter the parts which are higher than 3kHz, and
the signal attained goes into the D/A converter (U505).
balance between the MOD and
is summed with MOD and the resulting
signal goes to the VCO. This signal is
a varicap diode in the VCO for direct FM modulation. (See Fig. 1
The signal from (AFWN) entering into AF signal and higher audio frequencies output by pin 1 of U501: A
of CPU. The input signal is compared wi
programmed tone frequency code in the CPU. The squelch will open when they match.
Page 7

) is used to adjust MO modulation,
AF volume, TV voltage, FC reference
Adjustment values are sent from the CPU as serial data.
The D/A converter has a resolution of 256 and
When the POWER switch on the display unit is pressed,
45(P32), goes low, then CPU port
(SBE) is supplied to the radio.
When the DC power supplied to the radio, the voltage
During receiving, the CPU port
) output "H" level. Q101 and Q108 turn on
is supplied by 8V power supply (8R).
During transmitting, CPU port
level. Q102 and Q104 turn on.
Page 8

MAIN INTE RFACE(0.5S-1 S-32PWB)
PED09712M-FB18A9.5-C10-200
P2_6/TRDIO C117P2_5/TRDIO B1
P2_3/TRDIO D020P2_2/TRDIO C021P2_1/TRDIO B0
P1_7/TRAIO /INT 124P1_6/CLK0
P1_5/RXD0/(T RAIO) /(IN T1)26P1_4/TXD027P8_628P8_5/TRFO1229P8_4/TRFO11
P8_3/TRFO10/TRFI31P8_2/TRFO02
333435363738394041424344454647
P1_0/KI0 /AN849P0_0/AN750P0_1/AN651P0_2/AN552P0_3/AN453P0_4/AN354P6_255P6_1
P0_5/AN2/ CLK157P0_6/AN1/ DA058VSS/AVSS59P0_7/AN0/ DA160VREF61VCC/AVCC62P3_7/SSO63P3_5/SCL/SSCK64P35
MCU Unit•
SCHEMATIC
Page 10

Page 12
MAIN I NT ERFACE(0 .5S-1-32 PB)411
411411A1 I N7A2 I N9CMPRS IN3CMUTE4EMUTE12EXP I N14PT8A1 OU T6A2 OU T10CMPRS2EXP OU T15CMPRS FILT5EXP FILT11NC13VCC16GND1CH1-OUT
FILTER5P.P6STANDB Y7CH2-IN

ADJUSTMENT
DC Power supply terminal : 13.8V
2) Adjustment HEX value : FF
CH : TX center (Wide/Narrow)
CH : TX center (Wide/Narrow)
According to the large +,
1) CH : TX center (Wide/Narrow)
Page 14

CH : TX center (Wide/Narrow)
CH : TX center (Wide/Narrow)
CH : TX center (Wide/Narrow)
: TX center (Wide/Narrow)
CH : RX low (Wide/Narrow)
CH : RX center (Wide/Narrow)
CH : RX high (Wide/Narrow)
CH : TX center (Wide/Narrow)
CH : TX center (Wide/Narrow)
Page 15

BILL OF MATERIALS
SpecificationC1-C2SMT CAPACITOR
Page 19

SMT TANTALUM CAPACITORBtype
Page 20

060312P±0.1P 50VC308-C309
Page 24

SMT TANTALUM CAPACITORBtype422uF16VE200
SMT TANTALUM CAPACITORAtype110uF10VE202
SMT TANTALUM CAPACITORAtype10.22uF±20%
SMT TANTALUM CAPACITORBtype122uF16VE204
SMT TANTALUM CAPACITORBtype133uF±20%
SMT TANTALUM CAPACITORAtype210uF±20%
SMT TANTALUM CAPACITORAtype14.7
SMT TANTALUM CAPACITORAtype1NOUSE
SMT TANTALUM CAPACITORAtype16.8
SMT TANTALUM CAPACITORAtype10.68
Page 28

SMT TANTALUM CAPACITORAtype101uF±20%
SMT TANTALUM CAPACITORAtype410uF±20%
SMT TANTALUM CAPACITORAtype1NOUSE
SMT TANTALUM CAPACITORAtype110uF±20%
SMT TANTALUM CAPACITORAtype1
SMT TANTALUM CAPACITORAtype12.2uF±20%
SMT TANTALUM CAPACITORAtype14.7uF16V
SMT TANTALUM CAPACITORBtype110uF16V
M CAPACITORAtype12.2uF±20%
SMT TANTALUM CAPACITORAtype12.2uF±20%
Page 29

0603222K±5%R228SMT RESISTOR
Page 30

SMT VARIABLE CAPACITANCE DIODE
SMT VARIABLE CAPACITANCE DIODE
SMT VARIABLE CAPACITANCE DIODE
D217SMT VARIABLE CAPACITANCE DIODE
D218SMT VARIABLE CAPACITANCE DIODE
Page 35

SMT VARIABLE CAPACITANCE DIODE
D221SMT VARIABLE CAPACITANCE DIODE
D222SMT VARIABLE CAPACITANCE DIODE
D223SMT VARIABLE CAPACITANCE DIODE
SMT VARIABLE CAPACITANCE DIODE
Page 36

SpecificationQ208SMT TRANSISTOR
Page 37

SMT AIR-CORE COIL40.31h1.6h8TL208
SMT RESISTOR060310R±5%L210
SMT AIR-CORE COIL10.4h1.6h3T
SMT AIR-CORE COIL10.35h1.0h2TL222
L230-L231SMT WIRE WOUND INDUCTOR2NOUSE
Page 38

SMT FERRITE BEAD(BLACK)06034271TL242SMT RESISTOR
SMT SMALL FIXED INDUCTOR(BLOVE)2520110uH
FLAT CABLE CONNECTOR (Erection type)
Page 39