Renesas SH7616, SH7600 Series Hardware Manual

REJ09B0292-0200

The revision list can be viewed directly by
clicking the title page.

The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.

32

SH7616

Hardware Manual

Renesas 32-Bit RISC Microcomputer

SuperH™ RISC engine Family/SH7600 Series

SH7616 HD6417616

Rev. 2.00
Revision Date: Mar 09, 2006

Keep safety first in your circuit designs!

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third­party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.

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subject to change by Renesas Technology Corp. without notice due to product improvements or
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Rev. 2.00 Mar 09, 2006 page ii of xxvi

Preface

The SH7616 is a microprocessor that integrates peripheral functions necessary for system
configuration with a 32-bit internal architecture SH2-DSP CPU as its core.

The SH7616's on-chip peripheral functions include a cache memory, an interrupt controller,
timers, an ethernet controller (EtherC), DSP, a serial communication interface with FIFO (SCIF),
a USB function module, a user break controller (UBC), a bus state controller (BSC), a direct
memory access cntroller (DMAC), and I/O ports, making it ideal for use as a microcomputer in
electronic devices that require high speed together with low power consumption.

Intended Readership: This manual is intended for users undertaking the design of an application

system using the SH7616. Readers using this manual require a basic
knowledge of electrical circuits, logic circuits, and microcomputers.

Purpose: The purpose of this manual is to give users an understanding of the hardware

functions and electrical characteristics of the SH7616. Details of execution
instructions can be found in the SH-1, SH-2, SH-DSP Programming Manual,
which should be read in conjunction with the present manual.

Using this Manual:

• For an overall understanding of the SH7616's functions

Follow the Table of Contents. This manual is broadly divided into sections on the CPU, system
control functions, peripheral functions, and electrical characteristics.

• For a detailed understanding of CPU functions

Refer to the separate publication SH-1, SH-2, SH-DSP Programming Manual.

Note on bit notation: Bits are shown in high-to-low order from left to right.

Related Material: The latest information is available at our Web Site. Please make sure that you

have the most up-to-date information available.
http://www.renesas.com/

Rev. 2.00 Mar 09, 2006 page iii of xxvi

User's Manuals on the SH7616:

Manual Title ADE No.

SH7616 Hardware Manual This manual

SH-1/ SH-2/SH-DSP Software Manual REJ09B0171-0500O

Users manuals for development tools:

Manual Title ADE No.

C/C++ Complier, Assembler, Optimized Linkage Editor User's Manual REJ10B0152-0101

Simulator Debugger Users Manual REJ10B0210-0200

High-performance Embedded Workshop Users Manual REJ10J0886-0300

Application Note:

Manual Title ADE No.

C/C++ Complier REJ05B0463-0300

Rev. 2.00 Mar 09, 2006 page iv of xxvi

Main Revisions in This Edition

Item Page Revision (See Manual for Details)

All 

2.1.4 DSP Registers 37 Description added

7.1.5 Address Map

255 Table amended

Table 7.3 Address
Map

7.2.7 Individual
Memory Control

269 to
274

Register (MCR)

Bits 1 and 15

• For synchronous

DRAM interface

Bits 7, 5, and 4

7.5.11 64 Mbit

323 Description amended

Synchronous DRAM

(2 Mword × 32-bit)

Connection

8.4.7 Associative

369 Figure amended

Purges

Figure 8.11
Associative Purge
Access

• Company name amended

Hitachi, Ltd.

→ Renesas Technology Corp.

• Amendments made due to change in package code

FP-208C

→ PRQP0208KA-A

Figure 2.4 shows the DSP registers.
are shown in table 2.2. Registers A0, X0, X1, Y0, Y1, and DSR are
handled as system registers by CPU core instructions.

Address Space Memory Size

H'1000E000–H'1000EFFF On-chip X RAM area 4 kbytes

H'1001E000–H'1001EFFF On-chip Y RAM area 4 kbytes

Description replaced

Synchronous DRAM Mode Settings: To make mode settings for
the synchronous DRAM, write to address X+H'FF
X+H'FF
Whether to use X+H'FF

FF8000 from the CPU. (X represents the setting value.)

FF0000 or X+H'FFFF8000 determines on

the synchronous DRAM used.

Associative purge:

Bit
Address

Number of bits

31 10 9 4 3 0

29 28

Tag address010

19 634

The DSR register bit functions

FF0000 or

Entry

address

—

Rev. 2.00 Mar 09, 2006 page v of xxvi

Item Page Revision (See Manual for Details)

10.2.8
Transmit/Receive
Status Copy Enable
Register (TRSCER)

437 Description amended

Bit: 31 30 29 . . .

——— ————

Initial value: 0 0 0 . . .

R/W:RRR RRRR

Bit: 15 14 13 12 11 10 9 8

————————

Initial value: 0 0 0 0 0 0 0 0

R/W:RRRRRRRR

19 18 17 16

. . .

0000

. . .

10.3.1 Descriptor
List and Data Buffers

Transmit Descriptor 0
(TD0)

Bit:76543210

Initial value: 0 0 0 0 0 0 0 0

Bits 31 to 8—Reserved These bits are always read as 0. The write value should always be 0.

Bit 7—Multicast Address Frame Receive (RMAF): Bit Copy Enable (RMAFCE)

Bit 7: RMAFCE Description

0 Enables the RMAF bit status to be indicated in the RFS7 bit in the receive

1 Disables occurrence of corresponding source to be indicated in the RFS7 bit in

Bits 6 to 0—Reserved: These bits are always read as 0. The write value should always be 0.

RMAFCE

R/W:R/WRRRRRRR

descriptor.

the receive descriptor.

450 Description amended

Bit 27—Transmit Frame Error (TFE): Indicates that one or other bit of the transmit frame status
indicated by bits 26 to 0 is set.

Bit 27: TFE Description

0 No error during transmission
1 An error of some kind occurred during transmission (see bits 26 to 0)

Bits 26 to 0—Transmit Frame Status 26 to 0 (TFS26 to TFS0): These bits indicate the error status
during frame transmission.

• TFS26 to —Reserved

• TFS8—Teransmit Abort Detect

• TFS7 to TFS5—Reserved

TFS9

Note: This bit is set to 1 wh any of Transmit Frame Status bits 4 to 0 is set. When this bit is

set, the Transmit Frame Error bit (bit 27: TFE) is set to 1.

———————

en

Rev. 2.00 Mar 09, 2006 page vi of xxvi

Item Page Revision (See Manual for Details)

10.3.1 Descriptor
List and Data Buffers

Receive Descriptor

Figure 10.3
Relationship between
Receive Descriptor
and Receive Buffer

451 Figure amended

Receive descriptor
31 30 29 28

RD0

RD1

RD2

31

31

RDLE

RACT

RFP1

2627

RFE

RFP0

RBL

Padding (4 bytes)

RFS 26 to RFS0

16 15

RBA

RDL

0

0

Rev. 2.00 Mar 09, 2006 page vii of xxvi

Item Page Revision (See Manual for Details)

f

10.3.1 Descriptor
List and Data Buffers

Receive Descriptor 0
(TD0)

453

Description amended

Bit 27—Receive Frame Error (RFE): Indicates that one or other bit o
the receive frame status indicated by bits 26 to 0 is set. Whether or

multicast address frame receive information which is part of

not the
the frame status, is copied into this bit is specified by the
transmit/receive status copy enable register.

Bit 27: RFE Description

0 No error during reception (Initial value)

1

An error of some kind occurred during reception (see bits
26 to 0)

• Bits 26 to 0—Receive Frame Status 26 to 0 (RFS26 to RFS0):

These bits indicate the error status during frame reception.

• RFS26 to RFS10—Reserved

• RFS9—Receive FIFO Overflow (corresponds to

EESR)

RFS8—Reserve Abort Detect

•

Note: This bit is set to 1 when any of Receive Frame Status

bit 9, bit 7, bits 4 to 0 is set. When this bit is set, the
Receive Frame Error bit (bit 27: RFE) is set to 1.

• RFS7— Receive Multicast Address Frame (corresponds to

RMAF bit in EESR)

1

• RFS6—Reserved

*

• RSF5— Receive Frame Discard Request Assertion

(corresponds to RFAR bit in EESR)

• RFS4—Receive Residual-Bit Frame (corresponds to RRF bit in

EESR)

• RFS3—Receive Too-Long Frame (corresponds to RTLF bit in

EESR)

• RFS2—Receive Too-Short Frame (corresponds to RTSF bit in

EESR)

• RFS1—PHY-LSI Receive Error (corresponds to PRE bit in

EESR)

• RFS0—CRC Error on Received Frame (corresponds to CERF bit

in EESR)

Note: 1. Only HD6417616 is effective. HD6417615 is Reserved

bit.

RFOF bit in

1

*

Rev. 2.00 Mar 09, 2006 page viii of xxvi

Item Page Revision (See Manual for Details)

11.3.6 DMA Transfer
Request
Acknowledge Signal

496 Figure replaced

Clock

Output Timing

Figure 11.13 Example
of DACKn Output

DACKn

(Active high)

Timing

0.5 cycles

14.3.4 Operation in
Synchronous Mode

15.4 SIOF Interrupt
Sources and DMAC

Table 15.3 SIOF
Interrupt Sources

Address bus

613 Description amended

In synchronous mode, the SCIF receives data in synchronization
with the

rise of the serial clock.

663 Description amended

Each SIOF channel has four interrupt sources: the receive-overrun­error interrupt (

TERI0) request, receive-data-full interrupt/receive-control-data-

(

RERI0) request, transmit-underrun-error interrupt

register-full interrupt (RDFI0) request, and transmit-data-empty
interrupt

/transmit-control-data-register-empty interrupt (TDEI0)
request. Table 15.3 shows the interrupt sources and their relative
priorities. The RDFI0 and TDEI0 interrupts are enabled by the RIE,
RCIE, TIE, and TCIE bits, respectively, in SICTR. The RERI0 and
TERI0 interrupts cannot be disabled.

664

Table amended

Interrupt
Source Description

RERI0 Receive overrun error (RERR) Not possible

TERI0 Transmit underrun error (TERR) Not possible

RDFI0 Receive data register full (RDRF)/

Receive Control Data Register Full (RCD)

TDEI0 Transmit data register empty (TDRE)/

Transmit Control Data Register Empty (TCD)

CPU DMAC

DMAC
Activation Priority

High
↑

*

Possible

Possible

↓

Low

*

Appendix C

Table C.1 SH7616
Product Lineup

904

Table amended

Abbreviation Voltage

SH7616 3.3 V 62.5 MHz HD6417616

Operating
Frequency Mark Code Package

Rev. 2.00 Mar 09, 2006 page ix of xxvi

SF PLQP0208KA-A

Rev. 2.00 Mar 09, 2006 page x of xxvi

Contents

Section 1 Overview............................................................................................................. 1

1.1 Features of SuperH Microcomputer with On-Chip Ethernet Controller ........................... 1

1.2 Block Diagram .................................................................................................................. 13

1.3 Pin Description.................................................................................................................. 14

1.3.1 Pin Arrangement .................................................................................................. 14

1.3.2 Pin Functions ....................................................................................................... 15

1.3.3 Pin Multiplexing .................................................................................................. 21

1.4 Processing States............................................................................................................... 27

Section 2 CPU ...................................................................................................................... 31

2.1 Register Configuration...................................................................................................... 31

2.1.1 General Registers................................................................................................. 31

2.1.2 Control Registers ................................................................................................. 33

2.1.3 System Registers.................................................................................................. 36

2.1.4 DSP Registers ...................................................................................................... 37

2.1.5 Notes on Guard Bits and Overflow Treatment..................................................... 40

2.1.6 Initial Values of Registers.................................................................................... 40

2.2 Data Formats ..................................................................................................................... 41

2.2.1 Data Format in Registers...................................................................................... 41

2.2.2 Data Formats in Memory ..................................................................................... 41

2.2.3 Immediate Data Format ....................................................................................... 42

2.2.4 DSP Type Data Formats ...................................................................................... 42

2.2.5 DSP Type Instructions and Data Formats............................................................ 44

2.3 CPU Core Instruction Features ......................................................................................... 48

2.4 Instruction Formats ........................................................................................................... 52

2.4.1 CPU Instruction Addressing Modes..................................................................... 52

2.4.2 DSP Data Addressing........................................................................................... 56

2.4.3 Instruction Formats for CPU Instructions............................................................ 62

2.4.4 Instruction Formats for DSP Instructions............................................................. 66

2.5 Instruction Set ................................................................................................................... 72

2.5.1 CPU Instruction Set ............................................................................................. 73

2.5.2 DSP Data Transfer Instruction Set....................................................................... 89

2.5.3 DSP Operation Instruction Set............................................................................. 93

2.5.4 Various Operation Instructions ............................................................................ 96

2.6 Usage Notes ...................................................................................................................... 105

2.6.1 When not using DSP instructions ........................................................................ 105

Rev. 2.00 Mar 09, 2006 page xi of xxvi

2.6.2 When executing a combination of double-precision multiplication or
double-precision product-sum operation (CPU instruction) and DSP

computing instruction .......................................................................................... 105

Section 3 Oscillator Circuits and Operating Modes.................................................. 107

3.1 Overview........................................................................................................................... 107

3.2 On-Chip Clock Pulse Generator and Operating Modes.................................................... 107

3.2.1 Clock Pulse Generator ......................................................................................... 107

3.2.2 Clock Operating Mode Settings........................................................................... 109

3.2.3 Connecting a Crystal Resonator........................................................................... 112

3.2.4 External Clock Input............................................................................................ 113

3.2.5 Operating Frequency Selection by Register......................................................... 114

3.2.6 Clock Modes and Frequency Ranges................................................................... 122

3.2.7 Notes on Board Design........................................................................................ 123

3.3 Bus Width of the CS0 Area............................................................................................... 124

Section 4 Exception Handling ......................................................................................... 125

4.1 Overview........................................................................................................................... 125

4.1.1 Types of Exception Handling and Priority Order ................................................ 125

4.1.2 Exception Handling Operations........................................................................... 127

4.1.3 Exception Vector Table ....................................................................................... 128

4.2 Resets ................................................................................................................................ 131

4.2.1 Types of Resets.................................................................................................... 131

4.2.2 Power-On Reset ................................................................................................... 131

4.2.3 Manual Reset ....................................................................................................... 132

4.3 Address Errors .................................................................................................................. 132

4.3.1 Sources of Address Errors ................................................................................... 132

4.3.2 Address Error Exception Handling...................................................................... 134

4.4 Interrupts........................................................................................................................... 135

4.4.1 Interrupt Sources.................................................................................................. 135

4.4.2 Interrupt Priority Levels....................................................................................... 136

4.4.3 Interrupt Exception Handling............................................................................... 136

4.5 Exceptions Triggered by Instructions ............................................................................... 137

4.5.1 Instruction-Triggered Exception Types ............................................................... 137

4.5.2 Trap Instructions.................................................................................................. 137

4.5.3 Illegal Slot Instructions........................................................................................ 138

4.5.4 General Illegal Instructions.................................................................................. 138

4.6 When Exception Sources Are Not Accepted .................................................................... 139

4.6.1 Immediately after a Delayed Branch Instruction ................................................. 139

4.6.2 Immediately after an Interrupt-Disabled Instruction............................................ 139

Rev. 2.00 Mar 09, 2006 page xii of xxvi

4.6.3 Instructions in Repeat Loops................................................................................ 140

4.7 Stack Status after Exception Handling.............................................................................. 141

4.8 Usage Notes ...................................................................................................................... 142

4.8.1 Value of Stack Pointer (SP) ................................................................................. 142

4.8.2 Value of Vector Base Register (VBR)................................................................. 142

4.8.3 Address Errors Caused by Stacking of Address Error Exception Handling ........ 142

4.8.4 Manual Reset during Register Access.................................................................. 142

Section 5 Interrupt Controller (INTC)........................................................................... 143

5.1 Overview........................................................................................................................... 143

5.1.1 Features................................................................................................................ 143

5.1.2 Block Diagram..................................................................................................... 143

5.1.3 Pin Configuration................................................................................................. 145

5.1.4 Register Configuration......................................................................................... 145

5.2 Interrupt Sources............................................................................................................... 146

5.2.1 NMI Interrupt....................................................................................................... 147

5.2.2 User Break Interrupt............................................................................................. 147

5.2.3 H-UDI Interrupt ................................................................................................... 147

5.2.4 IRL Interrupts....................................................................................................... 147

5.2.5 IRQ Interrupts ...................................................................................................... 148

5.2.6 On-chip Peripheral Module Interrupts ................................................................. 152

5.2.7 Interrupt Exception Vectors and Priority Order................................................... 152

5.3 Register Descriptions ........................................................................................................ 159

5.3.1 Interrupt Priority Level Setting Register A (IPRA) ............................................. 159

5.3.2 Interrupt Priority Level Setting Register B (IPRB).............................................. 160

5.3.3 Interrupt Priority Level Setting Register C (IPRC).............................................. 161

5.3.4 Interrupt Priority Level Setting Register D (IPRD) ............................................. 162

5.3.5 Interrupt Priority Level Setting Register E (IPRE) .............................................. 163

5.3.6 Vector Number Setting Register WDT (VCRWDT) ........................................... 164

5.3.7 Vector Number Setting Register A (VCRA)........................................................ 165

5.3.8 Vector Number Setting Register B (VCRB)........................................................ 166

5.3.9 Vector Number Setting Register C (VCRC)........................................................ 166

5.3.10 Vector Number Setting Register D (VCRD)........................................................ 167

5.3.11 Vector Number Setting Register E (VCRE) ........................................................ 168

5.3.12 Vector Number Setting Register F (VCRF)......................................................... 169

5.3.13 Vector Number Setting Register G (VCRG)........................................................ 170

5.3.14 Vector Number Setting Register H (VCRH)........................................................ 171

5.3.15 Vector Number Setting Register I (VCRI)........................................................... 172

5.3.16 Vector Number Setting Register J (VCRJ) .......................................................... 173

5.3.17 Vector Number Setting Register K (VCRK)........................................................ 174

Rev. 2.00 Mar 09, 2006 page xiii of xxvi

5.3.18 Vector Number Setting Register L (VCRL) ........................................................ 175

5.3.19 Vector Number Setting Register M (VCRM) ...................................................... 176

5.3.20 Vector Number Setting Register N (VCRN)........................................................ 177

5.3.21 Vector Number Setting Register O (VCRO)........................................................ 178

5.3.22 Vector Number Setting Register P (VCRP)......................................................... 179

5.3.23 Vector Number Setting Register Q (VCRQ)........................................................ 180

5.3.24 Vector Number Setting Register R (VCRR)........................................................ 181

5.3.25 Vector Number Setting Register S (VCRS)......................................................... 182

5.3.26 Vector Number Setting Register T (VCRT) ........................................................ 183

5.3.27 Vector Number Setting Register U (VCRU)........................................................ 184

5.3.28 Interrupt Control Register (ICR).......................................................................... 187

5.3.29 IRQ Control/Status Register (IRQCSR) .............................................................. 188

5.4 Interrupt Operation............................................................................................................ 190

5.4.1 Interrupt Sequence ............................................................................................... 190

5.4.2 Stack State after Interrupt Exception Handling.................................................... 192

5.5 Interrupt Response Time................................................................................................... 192

5.6 Sampling of Pins IRL3–IRL0 ........................................................................................... 194

5.7 Usage Notes ...................................................................................................................... 195

Section 6 User Break Controller (UBC) ....................................................................... 199

6.1 Overview........................................................................................................................... 199

6.1.1 Features................................................................................................................ 199

6.1.2 Block Diagram..................................................................................................... 200

6.1.3 Register Configuration......................................................................................... 201

6.2 Register Descriptions ........................................................................................................ 203

6.2.1 Break Address Register A (BARA)..................................................................... 203

6.2.2 Break Address Mask Register A (BAMRA)........................................................ 204

6.2.3 Break Bus Cycle Register A (BBRA).................................................................. 205

6.2.4 Break Address Register B (BARB) ..................................................................... 207

6.2.5 Break Address Mask Register B (BAMRB)........................................................ 208

6.2.6 Break Bus Cycle Register B (BBRB) .................................................................. 209

6.2.7 Break Address Register C (BARC)...................................................................... 211

6.2.8 Break Address Mask Register C (BAMRC)........................................................ 212

6.2.9 Break Data Register C (BDRC)........................................................................... 214

6.2.10 Break Data Mask Register C (BDMRC).............................................................. 215

6.2.11 Break Bus Cycle Register C (BBRC) .................................................................. 217

6.2.12 Break Execution Times Register C (BETRC) ..................................................... 218

6.2.13 Break Address Register D (BARD)..................................................................... 219

6.2.14 Break Address Mask Register D (BAMRD)........................................................ 220

6.2.15 Break Data Register D (BDRD)........................................................................... 222

Rev. 2.00 Mar 09, 2006 page xiv of xxvi

6.2.16 Break Data Mask Register D (BDMRD) ............................................................. 223

6.2.17 Break Bus Cycle Register D (BBRD).................................................................. 225

6.2.18 Break Execution Times Register D (BETRD) ..................................................... 226

6.2.19 Break Control Register (BRCR) .......................................................................... 227

6.2.20 Branch Flag Registers (BRFR) ............................................................................ 233

6.2.21 Branch Source Registers (BRSR) ........................................................................ 234

6.2.22 Branch Destination Registers (BRDR) ................................................................ 235

6.3 Operation........................................................................................................................... 236

6.3.1 User Break Operation Sequence .......................................................................... 236

6.3.2 Instruction Fetch Cycle Break.............................................................................. 237

6.3.3 Data Access Cycle Break..................................................................................... 238

6.3.4 Saved Program Counter (PC) Value .................................................................... 239

6.3.5 X Memory Bus or Y Memory Bus Cycle Break.................................................. 239

6.3.6 Sequential Break .................................................................................................. 240

6.3.7 PC Traces............................................................................................................. 241

6.3.8 Examples of Use .................................................................................................. 243

6.3.9 Usage Notes ......................................................................................................... 247

Section 7 Bus State Controller (BSC) ........................................................................... 249

7.1 Overview........................................................................................................................... 249

7.1.1 Features................................................................................................................ 249

7.1.2 Block Diagram..................................................................................................... 251

7.1.3 Pin Configuration................................................................................................. 252

7.1.4 Register Configuration......................................................................................... 254

7.1.5 Address Map ........................................................................................................ 255

7.2 Register Descriptions ........................................................................................................ 257

7.2.1 Bus Control Register 1 (BCR1) ........................................................................... 257

7.2.2 Bus Control Register 2 (BCR2) ........................................................................... 260

7.2.3 Bus Control Register 3 (BCR3) ........................................................................... 261

7.2.4 Wait Control Register 1 (WCR1)......................................................................... 263

7.2.5 Wait Control Register 2 (WCR2)......................................................................... 265

7.2.6 Wait Control Register 3 (WCR3)......................................................................... 267

7.2.7 Individual Memory Control Register (MCR)....................................................... 268

7.2.8 Refresh Timer Control/Status Register (RTCSR)................................................ 276

7.2.9 Refresh Timer Counter (RTCNT)........................................................................ 278

7.2.10 Refresh Time Constant Register (RTCOR) ......................................................... 278

7.3 Access Size and Data Alignment ...................................................................................... 279

7.3.1 Connection to Ordinary Devices.......................................................................... 279

7.3.2 Connection to Little-Endian Devices ................................................................... 280

7.4 Accessing Ordinary Space ................................................................................................ 282

Rev. 2.00 Mar 09, 2006 page xv of xxvi

7.4.1 Basic Timing........................................................................................................ 282

7.4.2 Wait State Control................................................................................................ 287

7.4.3 CS Assertion Period Extension............................................................................ 291

7.5 Synchronous DRAM Interface.......................................................................................... 292

7.5.1 Synchronous DRAM Direct Connection ............................................................. 292

7.5.2 Address Multiplexing........................................................................................... 294

7.5.3 Burst Reads.......................................................................................................... 296

7.5.4 Single Reads ........................................................................................................ 301

7.5.5 Single Writes........................................................................................................ 303

7.5.6 Burst Write Mode ................................................................................................ 304

7.5.7 Bank Active Function .......................................................................................... 306

7.5.8 Refreshes.............................................................................................................. 317

7.5.9 Overlap Between Auto Precharge Cycle (Tap) and Next Access ........................ 320

7.5.10 Power-On Sequence............................................................................................. 321

7.5.11 64 Mbit Synchronous DRAM (2 Mword × 32-bit) Connection........................... 323

7.6 DRAM Interface ............................................................................................................... 324

7.6.1 DRAM Direct Connection ................................................................................... 324

7.6.2 Address Multiplexing........................................................................................... 325

7.6.3 Basic Timing........................................................................................................ 326

7.6.4 Wait State Control................................................................................................ 327

7.6.5 Burst Access ........................................................................................................ 329

7.6.6 EDO Mode........................................................................................................... 332

7.6.7 DRAM Single Transfer........................................................................................ 336

7.6.8 Refreshing............................................................................................................ 337

7.6.9 Power-On Sequence............................................................................................. 339

7.7 Burst ROM Interface......................................................................................................... 339

7.8 Idles between Cycles......................................................................................................... 343

7.9 Bus Arbitration.................................................................................................................. 345

7.9.1 Master Mode........................................................................................................ 349

7.10 Additional Items................................................................................................................ 350

7.10.1 Resets................................................................................................................... 350

7.10.2 Access as Viewed from CPU, DMAC or E-DMAC ............................................ 351

7.10.3 STATS1 and STATS0 Pins ................................................................................. 352

7.10.4 BUSHiZ Specification ......................................................................................... 353

7.11 Usage Notes ...................................................................................................................... 354

7.11.1 Normal Space Access after Synchronous DRAM Write when Using DMAC..... 354

7.11.2 When Using Iφ: Eφ Clock Ratio of 1: 1, 8-Bit Bus Width,

and External Wait Input....................................................................................... 356

7.11.3 When connecting external device to synchronous DRAM .................................. 356

Rev. 2.00 Mar 09, 2006 page xvi of xxvi

Section 8 Cache.................................................................................................................... 357

8.1 Introduction....................................................................................................................... 357

8.1.1 Register Configuration......................................................................................... 358

8.2 Register Description.......................................................................................................... 358

8.2.1 Cache Control Register (CCR)............................................................................. 358

8.3 Address Space and the Cache............................................................................................ 360

8.4 Cache Operation................................................................................................................ 361

8.4.1 Cache Reads......................................................................................................... 361

8.4.2 Write Access ........................................................................................................ 363

8.4.3 Cache-Through Access ........................................................................................ 366

8.4.4 The TAS Instruction............................................................................................. 366

8.4.5 Pseudo-LRU and Cache Replacement ................................................................. 366

8.4.6 Cache Initialization .............................................................................................. 368

8.4.7 Associative Purges ............................................................................................... 368

8.4.8 Cache Flushing..................................................................................................... 369

8.4.9 Data Array Access ............................................................................................... 369

8.4.10 Address Array Access.......................................................................................... 370

8.5 Cache Use ......................................................................................................................... 371

8.5.1 Initialization ......................................................................................................... 371

8.5.2 Purge of Specific Lines........................................................................................ 372

8.5.3 Cache Data Coherency......................................................................................... 372

8.5.4 Two-Way Cache Mode ........................................................................................ 373

8.6 Usage Notes ...................................................................................................................... 374

8.6.1 Standby ................................................................................................................ 374

8.6.2 Cache Control Register........................................................................................ 374

Section 9 Ethernet Controller (EtherC)......................................................................... 375

9.1 Overview........................................................................................................................... 375

9.1.1 Features................................................................................................................ 375

9.1.2 Configuration ....................................................................................................... 376

9.1.3 Pin Configuration................................................................................................. 378

9.1.4 Ethernet Controller Register Configuration......................................................... 379

9.2 Register Descriptions ........................................................................................................ 380

9.2.1 EtherC Mode Register (ECMR)........................................................................... 380

9.2.2 EtherC Status Register (ECSR)............................................................................ 383

9.2.3 EtherC Interrupt Permission Register (ECSIPR) ................................................. 384

9.2.4 PHY Interface Register (PIR) .............................................................................. 385

9.2.5 MAC Address High Register (MAHR)................................................................ 386

9.2.6 MAC Address Low Register (MALR)................................................................. 387

9.2.7 Receive Frame Length Register (RFLR) ............................................................. 388

Rev. 2.00 Mar 09, 2006 page xvii of xxvi

9.2.8 PHY Interface Status Register (PSR)................................................................... 389

9.2.9 Transmit Retry Over Counter Register (TROCR) ............................................... 390

9.2.10 Single Collision Detect Counter Register (SCDCR)............................................ 391

9.2.11 Delay Collision Detect Counter Register (CDCR) .............................................. 392

9.2.12 Lost Carrier Counter Register (LCCR)................................................................ 393

9.2.13 Carrier Not Detect Counter Register (CNDCR) .................................................. 394

9.2.14 Illegal Frame Length Counter Register (IFLCR)................................................. 395

9.2.15 CRC Error Frame Counter Register (CEFCR)..................................................... 396

9.2.16 Frame Receive Error Counter Register (FRECR )............................................... 397

9.2.17 Too-Short Frame Receive Counter Register (TSFRCR)...................................... 398

9.2.18 Too-Long Frame Receive Counter Register (TLFRCR)...................................... 399

9.2.19 Residual-Bit Frame Counter Register (RFCR) .................................................... 400

9.2.20 Multicast Address Frame Counter Register (MAFCR)........................................ 401

9.3 Operation .......................................................................................................................... 402

9.3.1 Transmission........................................................................................................ 402

9.3.2 Reception ............................................................................................................. 404

9.3.3 MII Frame Timing ............................................................................................... 406

9.3.4 Accessing MII Registers...................................................................................... 408

9.3.5 Magic Packet Detection ....................................................................................... 411

9.3.6 CPU Operating Mode and Ethernet Controller Operation................................... 412

9.3.7 CAM Match Signal Input Function...................................................................... 413

9.4 Connection to PHY-LSI.................................................................................................... 415

Section 10 Ethernet Controller Direct Memory Access Controller

(E-DMAC) ....................................................................................................... 417

10.1 Overview........................................................................................................................... 417

10.1.1 Features................................................................................................................ 417

10.1.2 Configuration....................................................................................................... 418

10.1.3 Descriptor Management System .......................................................................... 419

10.1.4 Register Configuration......................................................................................... 419

10.2 Register Descriptions ........................................................................................................ 421

10.2.1 E-DMAC Mode Register (EDMR)...................................................................... 421

10.2.2 E-DMAC Transmit Request Register (EDTRR).................................................. 422

10.2.3 E-DMAC Receive Request Register (EDRRR)................................................... 423

10.2.4 Transmit Descriptor List Address Register (TDLAR)......................................... 424

10.2.5 Receive Descriptor List Address Register (RDLAR) .......................................... 425

10.2.6 EtherC/E-DMAC Status Register (EESR)........................................................... 426

10.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR)...................... 432

10.2.8 Transmit/Receive Status Copy Enable Register (TRSCER)................................ 437

10.2.9 Receive Missed-Frame Counter Register (RMFCR) ........................................... 438

Rev. 2.00 Mar 09, 2006 page xviii of xxvi

10.2.10 Transmit FIFO Threshold Register (TFTR)......................................................... 439

10.2.11 FIFO Depth Register (FDR)................................................................................. 441

10.2.12 Receiver Control Register (RCR) ........................................................................ 442

10.2.13 E-DMAC Operation Control Register (EDOCR) ................................................ 443

10.2.14 Receiving-Buffer Write Address Register (RBWAR) ......................................... 444

10.2.15 Receiving-Descriptor Fetch Address Register (RDFAR) .................................... 445

10.2.16 Transmission-Buffer Read Address Register (TBRAR) ...................................... 446

10.2.17 Transmission-Descriptor Fetch Address Register (TDFAR) ............................... 447

10.3 Operation........................................................................................................................... 448

10.3.1 Descriptor List and Data Buffers ......................................................................... 448

10.3.2 Transmission........................................................................................................ 455

10.3.3 Reception ............................................................................................................. 457

10.3.4 Multi-Buffer Frame Transmit/Receive Processing .............................................. 459

Section 11 Direct Memory Access Controller (DMAC).......................................... 461

11.1 Overview........................................................................................................................... 461

11.1.1 Features................................................................................................................ 461

11.1.2 Block Diagram ..................................................................................................... 463

11.1.3 Pin Configuration................................................................................................. 464

11.1.4 Register Configuration......................................................................................... 465

11.2 Register Descriptions ........................................................................................................ 466

11.2.1 DMA Source Address Registers 0 and 1 (SAR0, SAR1)..................................... 466

11.2.2 DMA Destination Address Registers 0 and 1 (DAR0, DAR1) ............................ 466

11.2.3 DMA Transfer Count Registers 0 and 1 (TCR0, TCR1) ..................................... 467

11.2.4 DMA Channel Control Registers 0 and 1 (CHCR0, CHCR1) ............................. 467

11.2.5 DMA Vector Number Registers 0 and 1 (VCRDMA0, VCRDMA1) ................. 472

11.2.6 DMA Request/Response Selection Control Registers 0 and 1

(DRCR0, DRCR1) ............................................................................................... 473

11.2.7 DMA Operation Register (DMAOR)................................................................... 475

11.3 Operation........................................................................................................................... 477

11.3.1 DMA Transfer Flow............................................................................................. 477

11.3.2 DMA Transfer Requests ...................................................................................... 479

11.3.3 Channel Priorities................................................................................................. 483

11.3.4 DMA Transfer Types........................................................................................... 486

11.3.5 Number of Bus Cycles......................................................................................... 496

11.3.6 DMA Transfer Request Acknowledge Signal Output Timing............................. 496

11.3.7 DREQn Pin Input Detection Timing.................................................................... 507

11.3.8 DMA Transfer End .............................................................................................. 513

11.3.9 BH Pin Output Timing......................................................................................... 514

11.4 Usage Examples................................................................................................................ 516

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11.4.1 Example of DMA Data Transfer Between SCIF and External Memory.............. 516

11.5 Usage Notes ...................................................................................................................... 516

Section 12 16-Bit Free-Running Timer (FRT)............................................................ 519

12.1 Overview........................................................................................................................... 519

12.1.1 Features................................................................................................................ 519

12.1.2 Block Diagram..................................................................................................... 520

12.1.3 Pin Configuration................................................................................................. 521

12.1.4 Register Configuration......................................................................................... 521

12.2 Register Descriptions ........................................................................................................ 522

12.2.1 Free-Running Counter (FRC) .............................................................................. 522

12.2.2 Output Compare Registers A and B (OCRA and OCRB).................................... 522

12.2.3 Input Capture Register (FICR)............................................................................. 523

12.2.4 Timer Interrupt Enable Register (TIER).............................................................. 523

12.2.5 Free-Running Timer Control/Status Register (FTCSR)....................................... 524

12.2.6 Timer Control Register (TCR)............................................................................. 526

12.2.7 Timer Output Compare Control Register (TOCR) .............................................. 527

12.3 CPU Interface.................................................................................................................... 528

12.4 Operation .......................................................................................................................... 531

12.4.1 FRC Count Timing .............................................................................................. 531

12.4.2 Output Timing for Output Compare .................................................................... 532

12.4.3 FRC Clear Timing................................................................................................ 532

12.4.4 Input Capture Input Timing ................................................................................. 533

12.4.5 Input Capture Flag (ICF) Setting Timing............................................................. 534

12.4.6 Output Compare Flag (OCFA, OCFB) Setting Timing ....................................... 534

12.4.7 Timer Overflow Flag (OVF) Setting Timing....................................................... 535

12.5 Interrupt Sources............................................................................................................... 536

12.6 Example of FRT Use......................................................................................................... 536

12.7 Usage Notes ...................................................................................................................... 537

12.7.1 Contention between FRC Write and Clear........................................................... 537

12.7.2 Contention between FRC Write and Increment................................................... 538

12.7.3 Contention between OCR Write and Compare Match......................................... 539

12.7.4 Internal Clock Switching and Counter Operation................................................ 540

12.7.5 Timer Output (FTOA, FTOB) ............................................................................. 541

Section 13 Watchdog Timer (WDT).............................................................................. 543

13.1 Overview........................................................................................................................... 543

13.1.1 Features................................................................................................................ 543

13.1.2 Block Diagram..................................................................................................... 544

13.1.3 Pin Configuration................................................................................................. 544

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13.1.4 Register Configuration......................................................................................... 545

13.2 Register Descriptions ........................................................................................................ 545

13.2.1 Watchdog Timer Counter (WTCNT)................................................................... 545

13.2.2 Watchdog Timer Control/Status Register (WTCSR)........................................... 546

13.2.3 Reset Control/Status Register (RSTCSR)............................................................ 547

13.2.4 Notes on Register Access..................................................................................... 549

13.3 Operation........................................................................................................................... 550

13.3.1 Operation in Watchdog Timer Mode ................................................................... 550

13.3.2 Operation in Interval Timer Mode ....................................................................... 552

13.3.3 Operation when Standby Mode is Cleared........................................................... 552

13.3.4 Timing of Overflow Flag (OVF) Setting ............................................................. 553

13.3.5 Timing of Watchdog Timer Overflow Flag (WOVF) Setting.............................. 553

13.4 Usage Notes ...................................................................................................................... 554

13.4.1 Contention between WTCNT Write and Increment............................................. 554

13.4.2 Changing CKS2 to CKS0 Bit Values................................................................... 554

13.4.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 554

13.4.4 System Reset with WDTOVF.............................................................................. 555

13.4.5 Internal Reset in Watchdog Timer Mode............................................................. 555

Section 14 Serial Communication Interface with FIFO (SCIF)............................. 557

14.1 Overview........................................................................................................................... 557

14.1.1 Features................................................................................................................ 557

14.1.2 Block Diagrams ................................................................................................... 559

14.1.3 Pin Configuration................................................................................................. 560

14.1.4 Register Configuration......................................................................................... 561

14.2 Register Descriptions ........................................................................................................ 562

14.2.1 Receive Shift Register (SCRSR).......................................................................... 562

14.2.2 Receive FIFO Data Register (SCFRDR) ............................................................. 562

14.2.3 Transmit Shift Register (SCTSR) ........................................................................ 563

14.2.4 Transmit FIFO Data Register (SCFTDR) ............................................................ 563

14.2.5 Serial Mode Register (SCSMR)........................................................................... 564

14.2.6 Serial Control Register (SCSCR)......................................................................... 567

14.2.7 Serial Status 1 Register (SC1SSR)....................................................................... 570

14.2.8 Serial Status 2 Register (SC2SSR)....................................................................... 575

14.2.9 Bit Rate Register (SCBRR).................................................................................. 578

14.2.10 FIFO Control Register (SCFCR) ......................................................................... 586

14.2.11 FIFO Data Count Register (SCFDR) ................................................................... 588

14.2.12 FIFO Error Register (SCFER) ............................................................................. 589

14.2.13 IrDA Mode Register (SCIMR)............................................................................. 589

14.3 Operation........................................................................................................................... 591

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14.3.1 Overview.............................................................................................................. 591

14.3.2 Operation in Asynchronous Mode ....................................................................... 593

14.3.3 Multiprocessor Communication Function............................................................ 605

14.3.4 Operation in Synchronous Mode ......................................................................... 613

14.3.5 Use of Transmit/Receive FIFO Buffers ............................................................... 623

14.3.6 Operation in IrDA Mode...................................................................................... 626

14.4 SCIF Interrupt Sources and the DMAC ............................................................................ 630

14.5 Usage Notes ...................................................................................................................... 631

Section 15 Serial I/O with FIFO (SIOF)....................................................................... 637

15.1 Overview........................................................................................................................... 637

15.1.1 Features................................................................................................................ 637

15.2 Register Configuration...................................................................................................... 639

15.2.1 Receive Shift Register (SIRSR)........................................................................... 639

15.2.2 Receive Data Register (SIRDR) .......................................................................... 640

15.2.3 Transmit Shift Register (SITSR).......................................................................... 641

15.2.4 Transmit Data Register (SITDR) ......................................................................... 641

15.2.5 Serial Control Register (SICTR).......................................................................... 642

15.2.6 Serial Status Register (SISTR)............................................................................. 645

15.2.7 Receive Control Data Register (SIRCDR)........................................................... 648

15.2.8 Transmit Control Data Register (SITCDR) ......................................................... 649

15.2.9 FIFO Control Register (SIFCR)........................................................................... 649

15.2.10 FIFO Data Count Register (SIFDR) .................................................................... 653

15.3 Operation .......................................................................................................................... 654

15.3.1 Input when TRMD = 0 in SIFCR......................................................................... 654

15.3.2 Output when TRMD = 0 in SIFCR...................................................................... 657

15.3.3 Output when TRMD = 1 in SIFCR...................................................................... 661

15.4 SIOF Interrupt Sources and DMAC.................................................................................. 663

Section 16 Serial I/O (SIO)............................................................................................... 665

16.1 Overview........................................................................................................................... 665

16.1.1 Features................................................................................................................ 665

16.2 Register Configuration...................................................................................................... 668

16.2.1 Receive Shift Register (SIRSR)........................................................................... 669

16.2.2 Receive Data Register (SIRDR) .......................................................................... 669

16.2.3 Transmit Shift Register (SITSR).......................................................................... 670

16.2.4 Transmit Data Register (SITDR) ......................................................................... 670

16.2.5 Serial Control Register (SICTR).......................................................................... 671

16.2.6 Serial Status Register (SISTR)............................................................................. 673

16.3 Operation .......................................................................................................................... 675

Rev. 2.00 Mar 09, 2006 page xxii of xxvi

16.3.1 Input..................................................................................................................... 675

16.3.2 Output .................................................................................................................. 676

16.4 SIO Interrupt Sources and DMAC .................................................................................... 679

Section 17 16-Bit Timer Pulse Unit (TPU).................................................................. 681

17.1 Overview........................................................................................................................... 681

17.1.1 Features................................................................................................................ 681

17.1.2 Block Diagram ..................................................................................................... 684

17.1.3 Pin Configuration................................................................................................. 685

17.1.4 Register Configuration......................................................................................... 686

17.2 Register Descriptions ........................................................................................................ 687

17.2.1 Timer Control Register (TCR)............................................................................. 687

17.2.2 Timer Mode Register (TMDR) ............................................................................ 690

17.2.3 Timer I/O Control Register (TIOR) ..................................................................... 692

17.2.4 Timer Interrupt Enable Register (TIER).............................................................. 699

17.2.5 Timer Status Register (TSR)................................................................................ 701

17.2.6 Timer Counter (TCNT)........................................................................................ 704

17.2.7 Timer General Register (TGR) ............................................................................ 705

17.2.8 Timer Start Register (TSTR)................................................................................ 705

17.2.9 Timer Synchronous Register (TSYR).................................................................. 706

17.3 Interface to Bus Master ..................................................................................................... 707

17.3.1 16-Bit Registers ................................................................................................... 707

17.3.2 8-Bit Registers ..................................................................................................... 707

17.4 Operation........................................................................................................................... 709

17.4.1 Overview.............................................................................................................. 709

17.4.2 Basic Functions.................................................................................................... 710

17.4.3 Synchronous Operation........................................................................................ 716

17.4.4 Buffer Operation .................................................................................................. 718

17.4.5 PWM Modes ........................................................................................................ 721

17.4.6 Phase Counting Mode.......................................................................................... 726

17.5 Interrupts ........................................................................................................................... 731

17.5.1 Interrupt Sources and Priorities............................................................................ 731

17.5.2 DMAC Activation................................................................................................ 732

17.6 Operation Timing.............................................................................................................. 733

17.6.1 Input/Output Timing ............................................................................................ 733

17.6.2 Interrupt Signal Timing........................................................................................ 737

17.7 Usage Notes ...................................................................................................................... 740

17.8 Usage Notes ...................................................................................................................... 750

17.8.1 Clearing Flags in TSR0 to TSR2 ......................................................................... 750

17.8.2 DMA Transfer by TPU0 ...................................................................................... 750

Rev. 2.00 Mar 09, 2006 page xxiii of xxvi

Section 18 User Debug Interface (H-UDI) .................................................................. 751

18.1 Overview........................................................................................................................... 751

18.1.1 Features................................................................................................................ 751

18.1.2 H-UDI Block Diagram......................................................................................... 752

18.1.3 Pin Configuration................................................................................................. 753

18.1.4 Register Configuration......................................................................................... 753

18.2 External Signals ................................................................................................................ 754

18.2.1 Test Clock (TCK) ................................................................................................ 754

18.2.2 Test Mode Select (TMS)...................................................................................... 754

18.2.3 Test Data Input (TDI) .......................................................................................... 754

18.2.4 Test Data Output (TDO) ...................................................................................... 755

18.2.5 Test Reset (TRST) ............................................................................................... 755

18.3 Register Descriptions ........................................................................................................ 755

18.3.1 Instruction Register (SDIR) ................................................................................. 755

18.3.2 Status Register (SDSR)........................................................................................ 757

18.3.3 Data Register (SDDR) ......................................................................................... 758

18.3.4 Bypass Register (SDBPR) ................................................................................... 758

18.3.5 Boundary scan register (SDBSR) ........................................................................ 758

18.3.6 ID code register (SDIDR) .................................................................................... 770

18.4 Operation .......................................................................................................................... 771

18.4.1 TAP Controller .................................................................................................... 771

18.4.2 H-UDI Interrupt and Serial Transfer.................................................................... 772

18.4.3 H-UDI Reset ........................................................................................................ 775

18.5 Boundary Scan .................................................................................................................. 775

18.5.1 Supported Instructions ......................................................................................... 775

18.5.2 Notes on Use........................................................................................................ 777

18.6 Usage Notes ...................................................................................................................... 777

Section 19 Pin Function Controller (PFC) ................................................................... 781

19.1 Overview........................................................................................................................... 781

19.2 Register Configuration...................................................................................................... 783

19.3 Register Descriptions ........................................................................................................ 783

19.3.1 Port A Control Register (PACR) ......................................................................... 783

19.3.2 Port A I/O Register (PAIOR)............................................................................... 786

19.3.3 Port B Control Registers (PBCR, PBCR2) .......................................................... 787

19.3.4 Port B I/O Register (PBIOR) ............................................................................... 793

Section 20 I/O Ports............................................................................................................ 795

20.1 Overview........................................................................................................................... 795

20.2 Port A................................................................................................................................ 795

Rev. 2.00 Mar 09, 2006 page xxiv of xxvi

20.2.1 Register Configuration......................................................................................... 796

20.2.2 Port A Data Register (PADR).............................................................................. 796

20.3 Port B ................................................................................................................................ 797

20.3.1 Register Configuration......................................................................................... 797

20.3.2 Port B Data Register (PBDR) .............................................................................. 798

Section 21 Power-Down Modes...................................................................................... 799

21.1 Overview........................................................................................................................... 799

21.1.1 Power-Down Modes ............................................................................................ 799

21.1.2 Register ................................................................................................................ 800

21.2 Register Descriptions ........................................................................................................ 801

21.2.1 Standby Control Register 1 (SBYCR1) ............................................................... 801

21.2.2 Standby Control Register 2 (SBYCR2) ............................................................... 803

21.3 Sleep Mode ....................................................................................................................... 805

21.3.1 Transition to Sleep Mode..................................................................................... 805

21.3.2 Canceling Sleep Mode ......................................................................................... 805

21.4 Standby Mode ................................................................................................................... 805

21.4.1 Transition to Standby Mode................................................................................. 805

21.4.2 Canceling Standby Mode..................................................................................... 807

21.4.3 Standby Mode Cancellation by NMI Interrupt..................................................... 807

21.4.4 Clock Pause Function........................................................................................... 808

21.4.5 Notes on Standby Mode....................................................................................... 811

21.5 Module Standby Function ................................................................................................. 812

21.5.1 Transition to Module Standby Function............................................................... 812

21.5.2 Clearing the Module Standby Function ............................................................... 812

Section 22 Electrical Characteristics.............................................................................. 813

22.1 Absolute Maximum Ratings.............................................................................................. 813

22.2 DC Characteristics ............................................................................................................ 814

22.3 AC Characteristics ............................................................................................................ 816

22.3.1 Clock Timing ....................................................................................................... 817

22.3.2 Control Signal Timing ......................................................................................... 821

22.3.3 Bus Timing........................................................................................................... 823

22.3.4 Direct Memory Access Controller Timing........................................................... 861

22.3.5 Free-Running Timer Timing................................................................................ 862

22.3.6 Serial Communication Interface Timing.............................................................. 864

22.3.7 Watchdog Timer Timing...................................................................................... 868

22.3.8 Serial I/O with FIFO / Serial I/O Timing............................................................. 869

22.3.9 User Debug Interface Timing............................................................................... 872

22.3.10 I/O Port Timing.................................................................................................... 873

Rev. 2.00 Mar 09, 2006 page xxv of xxvi

22.3.11 Ethernet Controller Timing.................................................................................. 875

22.3.12 STATS, BH, and BUSHiZ Signal Timing ........................................................... 878

22.4 AC Characteristic Test Conditions.................................................................................... 880

Appendix A On-Chip Peripheral Module Registers.................................................. 881

A.1 Addresses .......................................................................................................................... 881

Appendix B Pin States ....................................................................................................... 900

B.1 Pin States in Reset, Power-Down State, and Bus-Released State ..................................... 900

Appendix C Product Lineup............................................................................................. 904

Appendix D Package Dimensions .................................................................................. 905

Rev. 2.00 Mar 09, 2006 page xxvi of xxvi

Section 1 Overview

Section 1 Overview

1.1 Features of SuperH Microcomputer with On-Chip Ethernet Controller

The SH7616 is a CMOS single-chip microcontroller that integrates a high-speed CPU core using
an original Renesas architecture with supporting functions required for an Ethernet system.

The CPU has a RISC (Reduced Instruction Set Computer) type instruction set. The CPU basically
operates at a rate of one instruction per cycle, offering a great improvement in instruction
execution speed. In addition, the 32-bit internal architecture provides improved data processing
power, and DSP functions have also been enhanced with the implementation of extended Harvard
architecture DSP data bus functions. With this CPU, it has become possible to assemble low-cost,
high-performance/high-functionality systems even for applications such as realtime control, which
could not previously be handled by microcontrollers because of their high-speed processing
requirements. The SH7616 also includes a maximum 4-kbyte cache, for greater CPU processing
power when accessing external memory.

The SH7616 is equipped with a media access controller (MAC) conforming to the IEEE802.3u
standard, and an Ethernet controller that includes a media independent interface (MII) standard
unit, enabling 10/100 Mbps LAN connection. Supporting functions necessary for system
configuration are also provided, including RAM, timers, a serial communication interface with
FIFO (SCIF), interrupt controller (INTC), and I/O ports.

To improve the efficiency of frame transmission/reception, the processing power of the DMAC for
the Ethernet controller is improved and the FIFO for the DMAC has 2 kbytes. A CAM match
signal input function is provided for systems that require multiple MAC addresses. In serial I/O
with three channels, one operates with the FIFO for better data processing power when connected
to the codec.

Rev. 2.00 Mar 09, 2006 page 1 of 906

REJ09B0292-0200

Section 1 Overview

Table 1.1 Features

Item Specifications

CPU

• Original Renesas architecture

• 32-bit internal architecture

• General register machine
 Sixteen 32-bit general registers
 Six 32-bit control registers (including 3 added for DSP use)
 Ten 32-bit system registers

• RISC (Reduced Instruction Set Computer) type instruction set
 Fixed 16-bit instruction length for improved code efficiency
 Load-store architecture (basic operations are executed between

registers)

 Delayed branch instructions reduce pipeline disruption during

branches

 C-oriented instruction set

• Instruction execution time: One instruction per cycle (16.0 ns/instruction at

62.5 MHz operation)

• Address space: Architecture supports 4 Gbytes

• On-chip multiplier: Multiply operations (32 bits × 32 bits → 64 bits) and

multiply-and-accumulate operations (32 bits × 32 bits + 64 bits → 64 bits)

executed in two to four cycles

• Five-stage pipeline

Rev. 2.00 Mar 09, 2006 page 2 of 906
REJ09B0292-0200

Item Specifications

DSP

• DSP engine
 Multiplier
 Arithmetic logic unit (ALU)
 Shifter
 DSP registers

• Multiplier
 16 bits × 16 bits → 32 bits
 Single-cycle multiplier

• DSP registers
 Two 40-bit data registers
 Six 32-bit data registers
 Modulo register (MOD, 32 bits) added to control registers
 Repeat counter (RC) added to status register (SR)
 Repeat start register (RS, 32 bits) and repeat end register (RE, 32 bits)

added to control registers

• DSP data bus
 Extended Harvard architecture
 Simultaneous access to two data buses and one instruction bus

• Parallel processing
 Maximum of four parallel processes
 ALU operations, multiplication, and two loads or stores

• Address processors

Section 1 Overview

 Two address processors
 Address operations to access two memories

• DSP data addressing modes
 Increment and index
 Each with or without modulo addressing

• Repeat control: Zero-overhead repeat (loop) control

• Instruction set
 16-bit length (in case of load or store only)
 32-bit length (including ALU operations and multiplication)
 Added SuperH microcontroller instructions for accessing DSP registers

• Fifth and last pipeline stage is DSP stage

Rev. 2.00 Mar 09, 2006 page 3 of 906

REJ09B0292-0200

Section 1 Overview

Item Specifications

Cache

Interrupt controller
(INTC)

• Mixed instruction/data type cache

• Maximum of 4 kbytes

• 4-way set-associative type

• 16-byte line length

• 64 cache tag entries

• 16-byte write-back buffer

• Selection of write-through or write-back mode for data writes

• LRU replacement algorithm

• Can also be used as 2-kbyte cache and 2-kbyte RAM (2-way cache mode)

• Mixed instruction/data cache, instruction cache, or data cache mode can

be set

• 1-cycle reads, 2-cycle writes (in write-back mode)

• 16 priority levels can be set

• On-chip supporting module interrupt vector numbers can be set

• 41 internal interrupt sources

• The E-DMAC interrupt (EINT) is input to the INTC as the OR of 22 EtherC

and E-DMAC interrupt sources (max.). Thus, from the viewpoint of the
INTC, there is one EtherC/E-DMAC interrupt source.

• Five external interrupt pins (NMI, IRL0 to IRL3)

• 15 external interrupt sources (encoded input) can also be selected for pins

IRL0 to IRL3 (IRL interrupts)

• IRL interrupt vector number setting can also be selected (selection of auto

vector or external vector)

• Provision for IRQ interrupt setting (low-level, rising-edge, falling-edge,

both-edge detection)

Rev. 2.00 Mar 09, 2006 page 4 of 906
REJ09B0292-0200

Item Specifications

User break
controller (UBC),
4 channels
(A, B, C, D)

• Interrupt generation based on independent or sequential conditions for

channels A, B, C, D

 Three sequential setting patterns: A → B → C → D, B → C → D,

C → D

• Settable break conditions: Address, data (channels C and D only), bus

master (CPU/DMAC), bus cycle (instruction fetch/data access), read/write,
operand cycle (byte/word/longword)

• User break interrupt generated on occurrence of break condition

• Processing can be stopped before or after instruction execution in

instruction fetch cycle

• Break with specification of number of executions (channels C and D only)

Settable number of executions: max. 2

• PC trace function

Branch source/branch destination can be traced in branch instruction fetch
(max. 8 addresses (4 pairs))

12

– 1 (4095)

Section 1 Overview

Rev. 2.00 Mar 09, 2006 page 5 of 906

REJ09B0292-0200

Section 1 Overview

Item Specifications

Bus state controller
(BSC)

• Address space divided into five areas (CS0 to CS4, max. linear 32 Mbytes

each)

 Memory types such as DRAM, synchronous DRAM, burst ROM, can

be specified for each area

 Two synchronous DRAM spaces (CS2, CS3); CS3 also supports

DRAM

 Bus width (8, 16, 32 bits) can be selected for each area
 Wait state insertion control for each area
 Control signal output for each area
 Endian can be set for CS2 and CS4

• Cache
 Cache area/cache-through area selection by access address
 Selection of write-through or write-back mode

• Refresh functions
 CAS-before-RAS refreshing (auto refreshing) or self-refreshing
 Refresh interval settable by means of refresh counter and clock select

setting

 Concentrated refreshing according to refresh count setting

(1, 2, 4, 6, 8)

 Refresh request output possible (REFOUT)

• Direct DRAM interface
 Multiplexed row address/column address output
 Fast page mode burst transfer and continuous access when reading
 EDO mode
 TP cycle generation to secure RAS precharge time

• Direct synchronous DRAM interface
 Multiplexed row address/column address output
 Bank-active mode (valid for CS3 only)
 Selection of burst read/single write mode or burst read/burst write

mode

• Bus arbitration (BRLS, BGR)

• Refresh counter can be used as interval timer
 Interrupt request generated on compare match (CMI interrupt request

signal)

Rev. 2.00 Mar 09, 2006 page 6 of 906
REJ09B0292-0200

Item Specifications

Direct memory
access controller
(DMAC),
2 channels

On-chip RAM

Ethernet controller
direct memory
access controller
(E-DMAC),
2 channels

• 4-Gbyte address space, maximum 16M (16,777,216) transfers

• Selection of 8-bit, 16-bit, 32-bit, or 16-byte transfer data length

• Parallel execution of CPU instruction processing and DMA operation

possible in case of cache hit

• Selection of dual address or single address mode
 Single address (data transfer rate of one transfer unit in one bus cycle)
 Dual address (data transfer rate of one transfer unit in two bus cycles)
 When synchronous DRAM is connected, 16-byte continuous read →

continuous write transfer is possible (dual)

• When SDRAM is connected, clocked single-address transfer is possible at

rates up to 31.25 MHz

• Cycle stealing or burst transfer

• Relative channel priorities can be set (fixed mode/round robin mode)

• DMA transfer is possible for the following devices:
 External memory, on-chip memory, on-chip supporting modules

(excluding DMAC, BSC, UBC, cache, E-DMAC, EtherC)

• External requests, DMA transfer requests from on-chip supporting

modules, auto requests

• Interrupt request (DEIn) can be issued to CPU at end of data transfer

• DACK used for DREQ sampling (however, there is always one overrun as

there is one acceptance before first DACK)

• 4-kbyte X-RAM

• 4-kbyte Y-RAM

• Transfer possible between EtherC and external memory/on-chip memory

• 16-byte burst transfer possible

• Single address transfer

• Chain block transfer

• 32-bit transfer data width

• 4-Gbyte address space

• Data transfer possible from across byte boundaries in transmission

• Each transmit and receive FIFO includes 2 kbytes

Section 1 Overview

Rev. 2.00 Mar 09, 2006 page 7 of 906

REJ09B0292-0200

Section 1 Overview

Item Specifications

Ethernet controller
(EtherC)

Serial communi­cation interface
with FIFO (SCIF),
2 channels

Note: * Magic Packet is a registered trademark of Advanced Micro Devices, Inc.

• MAC (Media Access Control) functions
 Data frame assembly/disassembly (IEEE802.3-compliant frames)
 CSMA/CD link management (collision avoidance, processing in case

of collision)

 CRC processing
 Supports full-duplex transmission/reception
 Transmitting and receiving short and long packets

• Compatible with MII (Media Independent Interface) standard
 Converts 8-bit stream data from MAC level to MII nibble stream (4 bits)
 Station management (STA) functions
 18 TTL-level signals
 Variable transfer rate: 10/100 Mbps

• Magic Packet™

• CAM match signal input function

• Asynchronous mode
 Data length: 7 or 8 bits
 Stop bit length: 1 or 2
 Parity: Even, odd, or none
 Receive error detection: Parity errors, framing errors, overrun errors
 Break detection

• Synchronous mode
 One serial communication format (8-bit data length)
 Receive error detection: Overrun errors

• IrDA mode (conforming to IrDA 1.0)

• Simultaneous transmission/reception (full-duplex) capability
 Half-duplex communication used for IrDA communication

• Built-in dedicated baud rate generator allows selection of bit rate

• Built-in 16-stage transmit and receive FIFOs enable high-speed,

continuous communication

• Internal or external (SCK) transmit/receive clock source

*

(with WOL (Wake On LAN) output)

Rev. 2.00 Mar 09, 2006 page 8 of 906
REJ09B0292-0200

Item Specifications

Serial communi­cation interface
with FIFO (SCIF),
2 channels

Serial I/O with FIFO
(SIOF)

Serial I/O (SIO),
2 channels

• Four interrupt sources
 Transmit FIFO data empty
 Break
 Receive FIFO data full
 Receive error

• Built-in modem control functions (RTS, CTS)

• Detection of transmit and receive FIFO register data quantity and number

of receive FIFO register transmit data errors

• Timeout error (DR) can be detected during reception

• Full-duplex operation (independent transmit and receive registers, and

independent transmit and receive clocks)

• Transmit and receive FIFO for primary data/transmit and receive buffer for

control data (enabling continuous transmission/reception)

• Interval transfer mode and continuous transfer mode

• Choice of 8- or 16-bit data length

• Data transfer communication by means of polling or interrupts

• Choice of MSB- or LSB-first transfer for data I/O

• Full-duplex operation (independent transmit and receive registers, and

independent transmit and receive clocks)

• Transmit/receive ports with double-buffer structure (enabling continuous

transmission/reception)

• Interval transfer mode and continuous transfer mode

• Choice of 8- or 16-bit data length

• Data transfer communication by means of polling or interrupts

• MSB-first transfer between SIO and data I/O

Section 1 Overview

Rev. 2.00 Mar 09, 2006 page 9 of 906

REJ09B0292-0200

Section 1 Overview

Item Specifications

User debug
interface (H-UDI)

• Conforms to IEEE1149.1 standard
 Five test signals (TCK, TDI, TDO, TMS, TRST)
 TAP controller
 Instruction register
 Data register
 Bypass register

• Test mode that conforms to the IEEE1149.1 standard
 Standard instructions: BYPASS, SAMPLE/PRELOAD, and EXTEST
 Optional instructions: CLAMP, HIGHZ, and IDCODE

• H-UDI interrupt

 H-UDI interrupt request to INTC

• Reset hold

Timer pulse unit
(TPU), 3 channels

• Maximum 8-pulse input/output

• Total of eight timer general registers (TGR) (four for channel 0, two each

for channels 1 and 2)

 Waveform output by compare match: Selection of 0, 1, or toggle output
 Input capture function: Selection of rising-edge, falling-edge, or both-

edge detection

 Counter clear operation: Counter clearing possible by compare match

or input capture

 Synchronous operation: Multiple timer counters (TCNT) can be written

to simultaneously; simultaneous clearing by compare match and input
capture possible; simultaneous register input/output possible by
counter synchronous operation

 PWM mode: Any PWM output duty can be set; maximum 7-phase

PWM output possible by combination with synchronous operation

• Buffer operation settable for channel 0
 Input capture register double-buffering possible
 Automatic rewriting of output compare register possible

• Phase counting mode settable independently for channels 1 and 2
 Two-phase encoder pulse up/down-count possible

• 13 interrupt sources
 For channel 0, four compare match/input capture dual-function

interrupts and one overflow interrupt can be requested independently

 For channels 1 and 2, two compare match/input capture dual-function

interrupts, one overflow interrupt, and one underflow interrupt can be
requested independently

Rev. 2.00 Mar 09, 2006 page 10 of 906
REJ09B0292-0200

Item Specifications

16-bit free-running
timer (FRT),
1 channel

Watchdog timer
(WDT), 1 channel

Clock pulse
generator (CPG)

• Choice of four counter input clocks
 Three internal clocks (Pφ/8, Pφ/32, Pφ/128)
 External clock (enabling external event counting)

• Two independent comparators (allowing generation of two waveform

outputs)

• Input capture (choice of rising edge or falling edge)

• Counter clear specification
 Counter value can be cleared by compare match A

• Four interrupt sources
 Two compare match sources (OCIA, OCIB)
 One input capture source (ICI)
 One overflow source (OVI)

• Can be switched between watchdog timer mode and interval timer mode

• Internal reset, external signal (WDTOVF), or interrupt generated on count

overflow

• Used when standby mode is cleared or the clock frequency is changed,

and in clock pause mode

• Selection of eight counter input clocks

• Built-in clock pulse generator

• Selection of crystal or external clock as clock source

• Built-in clock-multiplication PLL circuits

• Built-in PLL circuit for phase synchronization between external clock and

internal clock

• CPU/DSP core clock (Iφ), peripheral module clock (Pφ), and external
interface clock (Eφ) frequencies can be scaled independently

Section 1 Overview

Rev. 2.00 Mar 09, 2006 page 11 of 906

REJ09B0292-0200

Section 1 Overview

Item Specifications

System controller
(SYSC)

I/O ports

• Selection of seven operating mode settings, three power-down modes

• Operating modes
 Control the method of clock generation (PLL ON/OFF) and clock

division ratio

• Power-down mode
 Sleep mode: CPU functions halted
 Standby mode: All functions halted
 Module standby function: Operation of FRT, SCIF, DMAC, UBC, DSP,

TPU, and SIO on-chip supporting modules is halted selectively

• 29 input/output ports

Rev. 2.00 Mar 09, 2006 page 12 of 906
REJ09B0292-0200

1.2 Block Diagram

Cache address bus

32-bit cache data bus

CPU

Internal address bus

Internal address bus

16-bit internal data bus

Section 1 Overview

16-bit internal data bus

Cache

address

array/data

array

Cache

controller

Direct

memory access

controller

Ethernet

controller

Ethernet

controller

direct memory

access

controller

Interrupt

controller

DSP

X-RAM

Y-RAM

User break

controller

Bus state
controller

Serial I/O
with FIFO

User debug

interface

Serial

I/O

Serial

communication

interface

with FIFO

Timer

pulse unit

Free-running

timer

Watchdog

timer

Clock pulse

generator

System

controller

I/O ports

Internal address bus

32-bit internal data bus

External bus

interface

Figure 1.1 Block Diagram of SH7616

Peripheral address bus

16-bit peripheral data bus

Rev. 2.00 Mar 09, 2006 page 13 of 906

REJ09B0292-0200

Section 1 Overview

1.3 Pin Description

1.3.1 Pin Arrangement

Figure 1.2 shows the pin arrangement.

PVCC

PB12/SRCK2/RTS/STATS1

PB13/TXD1

PB14/RXD1

PB15/SCK1

VSS

VSS

BGR

154

153

152

151

150

149

148

TIOCA1/SRXD2/PB10

TCLKC/TIOCB1/STCK2/PB9
TCLKD/TIOCB2/STXD2/PB7

TCLKA/TIOCC0/STXD1/PB1

WOL/TCLKB/TIOCD0/PB0

PVSS

TIOCA2/STS2/PB8

SCK2/SRCK1/PB6

RXD2/SRS1/PB5

TXD2/SRXD1/PB4

TIOCA0/STCK1/PB3

TIOCB0/STS1/PB2

PVCC

PVSS

SRCK0/PA13

SRS0/PA12
SRXD0/PA11
STCK0/PA10

STS0/PA9

STXD0/PA8

WDTOVF/PA7

FTCI/PA6

PVCC

FTI/PA5

PVSS

FTOA/PA4

FTOB/CKPO

LNKSTA/PA2

EXOUT/PA1

PA0/CAMSEN

RXER
RXDV

COL

CRS

PVSS

RXCLK

PVCC
ERXD0
ERXD1
ERXD2
ERXD3

MDIO

MDC

PVCC
TXCLK

PVSS

TXEN
ETXD0
ETXD1
ETXD2
ETXD3

TXER

PB11/SRS2/CTS/STATS0

156

155

157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051

VCC

147

VCC

146

BRLS

145

DACK0

DACK1

144

143

DREQ0

DREQ1BHBUSHiZ

142

141

140

CS4

CS3

CS2

CS1

CS0

RD/WR

139

138

137

136

135

134

133

PLQP0208KA-A

(Top view)

VCCBSVSS

132

131

130

REFOUTRDCKE

129

128

127

CAS0

126

CAS1

125

CAS2

124

CAS3

123

DQMLL/WE0

122

DQMLU/WE1

121

DQMUL/WE2

120

DQMUU/WE3

119

CAS/OE

RAS

VCC

WAIT

VSS

VSS

VSS

A24

VCC

VCC

A23

A22

A21

A20

118

117

116

115

114

113

112

111

110

109

108

107

106

105

A19

104

A18

103

A17

102

VSS

101

A16

100

VCC

99

A15

98

A14

97

A13

96

A12

95

A11

94

A10

93

A9

92

VSS

91

A8

90

VCC

89

A7

88

A6

87

A5

86

A4

85

A3

84

A2

83

A1

82

VCC

81

A0

80

VSS

79

VSS

78

D31

77

VCC

76

D30

75

D29

74

D28

73

D27

72

D26

71

D25

70

VSS

69

D24

68

VCC

67

VCC

66

D23

65

D22

64

D21

63

D20

62

VSS

61

VSS

60

D19

59

VCC

58

D18

57

D17

56

D16

55

D15

54

D14

53

52

D0

D1D2D3D4D5

D6

D7

D8

IRL3

IRL2

IRL1

IRL0

NMI

VSS

RES

MD4

PLLVSS

PLLVCC

PLLCAP2

PLLCAP1

ASEMODE*

MD3

MD2

MD1

MD0

VCC

VSS

EXTAL

XTAL

VCC

CKIO

CKPREQ/CKM

VSS

IVECF

CKPACK

TDO

TDI

TCK

VSS

TMS

VCC

TRST

Body size

VCC

D9

VSS

28 × 28
Height
Pin pitch

Note: * When doing debugging using the E10A emulator, this pin is used for mode switching. It should be connected to Vss
when using the E10A emulator and connected to Vcc when using a normal user system.

Figure 1.2 SH7616 Pin Arrangement (PLQP0208KA-A)

Rev. 2.00 Mar 09, 2006 page 14 of 906
REJ09B0292-0200

D10

D11

D12

D13

VSS

VCC

(mm)

1.7

(mm)

0.5

(mm)

1.3.2 Pin Functions

Table 1.2 Pin Functions

Type Symbol I/O Name Function

Power V

V

PV

PV

CC

SS

CC

SS

Clock XTAL Output Crystal input/

EXTAL Input For connection to a crystal resonator, or

CKIO I/O System clock

CKPREQ/
CKM

CKPACK Output Clock pause

CKPO Output On-chip

PLLCAP1 Input PLL capacitance

PLLCAP2 Input Connects capacitance for operation of

PLLV

CC

PLLV

SS

Input Power For connection to the power supply.

Connect all V
supply. The chip will not operate if there
are any open pins

Input Ground For connection to ground. Connect all

pins to the system ground. The chip

V

SS

will not operate if there are any open pins

Input I/O circuit power Power supply for the I/O circuits

Input I/O circuit

Ground for the I/O circuits

ground

For connection to a crystal resonator

output pin

used as external clock input pin

Used as the external clock input or

input/output

internal clock output pin

pin

Input Clock pause

request input

Used as the clock pause request pin for
changing the frequency of the clock input
from the CKIO pin, or halting the clock

Indicates that the chip is in the clock

acknowledge

pause state (standby state) internally

signal

Outputs the on-chip peripheral clock (Pφ)

peripheral clock

(Pφ) output

Connects capacitance for operation of

connection pins

PLL circuit 1

PLL circuit 2

Input PLL power PLL oscillator power supply

Input PLL ground PLL oscillator ground

Section 1 Overview

pins to the system power

CC

Rev. 2.00 Mar 09, 2006 page 15 of 906

REJ09B0292-0200

Section 1 Overview

R

Type Symbol I/O Name Function

System
control

Operating
mode

Interrupts NMI Input Nonmaskable

Bus control BS Output Bus cycle

RES Input Reset When RES = 0 and NMI = 1, the chip

enters the power-on reset state. When

ES = 0 and NMI = 0, the chip enters the

manual reset state

WDTOVF Output Watchdog

timer overflow

BGR Output Bus grant Indicates that the bus has been released

BRLS Input Bus release Driven low when an external device

MD0–MD4 Input Mode setting The operating mode is specified by the

interrupt

IRL3–IRL0 Input External

interrupt
request input
0 to 3

IVECF Output Interrupt

vector fetch
cycle

start

CS4–CS0 Output Chip select

0 to 4

WAIT Input Wait Wait state request signal
RD Output Read Strobe signal indicating a read cycle
RAS Output Row address

strobe

Counter overflow signal output in
watchdog timer mode

to an external device. The device that
output the BRLS signal recognizes that
the bus has been acquired when it
receives the BGR signal

requests release of the bus

levels at these pins

Inputs the nonmaskable interrupt request
signal

These pins input maskable interrupt
request signals

Indicates an external vector read cycle

Signal indicating the start of a bus cycle

Asserted every data cycle in burst
transfer

Chip select signals indicating the area
being accessed

DRAM/synchronous DRAM RAS signal

Rev. 2.00 Mar 09, 2006 page 16 of 906
REJ09B0292-0200

Type Symbol I/O Name Function

Bus control CAS Output Column

address strobe

OE Output Output enable EDO DRAM output enable signal

DQMUU/

WE3

DQMUL/

WE2

DQMLU/

WE1

DQMLL/

WE0
CAS3 Output Column address

CAS2 Output Column address

CAS1 Output Column address

CAS0 Output Column address

CKE Output Clock enable Synchronous DRAM clock enable signal

REFOUT Output Refresh out Signal requesting refresh execution

RD/WR Output Read/write DRAM/synchronous DRAM write signal

BUSHiZ Input Bus high

BH Output Burst hint Asserted at the start of a DMA burst,

STATS0, 1 Output Status CPU, DMAC, and E-DMAC status

Output Highest byte

access

Output Second byte

access

Output Third byte

access

Output Lowest byte

access

strobe 3

strobe 2

strobe 1

strobe 0

impedance

Synchronous DRAM CAS signal

Used in access in RAS down mode

SRAM/synchronous DRAM highest byte
select signal

SRAM/synchronous DRAM second byte
select signal

SRAM/synchronous DRAM third byte
select signal

SRAM/synchronous DRAM lowest byte
select signal

DRAM highest byte select signal

DRAM second byte select signal

DRAM third byte select signal

DRAM lowest byte select signal

when the bus is released

Signal used in combination with WAIT
signal to place bus and strobe signals in
the high-impedance state without the
ending bus cycle

negated one bus cycle before the end of
the burst

information

Section 1 Overview

Rev. 2.00 Mar 09, 2006 page 17 of 906

REJ09B0292-0200

Section 1 Overview

Type Symbol I/O Name Function

Bus control A24–A0 Output Address bus Address output

D31–D0 I/O Data bus Data input/output

H-UDI TCK Input Test clock Test clock input

TMS Input Test mode

Test mode select input signal

select

TDI Input Test data input Serial data input

TDO Output Test data output Serial data output
TRST Input Test reset Test reset input signal

ASEMODE*Input ASE mode input ASE mode/user mode select signal

Ethernet
controller
(EtherC)

TX-CLK Input Transmitter

clock

TX-EN, ETXD0–3, TX-ER timing
reference signal

RX-CLK Input Receive clock RX-DV, ERXD0–3, RX-ER timing

reference signal

TX-EN Output Transmit enable Signal indicating that transmit data on

ETXD0–3 is ready

ETXD0–3 Output Transmit data

4-bit receive data

0–3

TX-ER Output Transmit error Signal sending error status to another

port

RX-DV Input Receive data

enable

ERXD0–3 Input Receive data

Indicates that enable receive data on
ERXD0–3 exist

4-bit receive data

0–3

RX-ER Input Receive error Reports error state that occurred during

transfer of frame data

CRS Input Carrier sense Carrier detection notification signal

COL Input Collision Collision detection signal

MDC Output Management

data clock

MDIO I/O Management

data input/output

Reference clock signal for information
transfer by MDIO

Bidirectional signal for exchanging
management information between STA
and PHY

Note: * When carrying out debugging using the E10A emulator, this pin is used for mode switching.

It should be connected to V

when using the E10A emulator and connected to VCC when

SS

using a normal user system. When a boundary scan test is performed with the H-UDI, user
mode must be used. A boundary scan test cannot be performed in ASE mode.

Rev. 2.00 Mar 09, 2006 page 18 of 906
REJ09B0292-0200

Section 1 Overview

Type Symbol I/O Name Function

Ethernet LNKSTA Input Link status Link status input from PHY
controller
(EtherC)

Direct
memory
access
controller
(DMAC)

Serial com­munication
interface with
FIFO (SCIF)

Timer pulse
unit (TPU)

EXOUT Output General-purpose

external output

WOL Output Wake on LAN Signal indicating detection of a Magic

CAMSEN Input CAM sense CAM sense signal

DACK0, 1 Output DMAC

channel 0, 1
acknowledge

DREQ0, 1 Input DMAC

channel 0, 1
request

TXD1, 2 Output Transmit data

output channel
1, 2

RXD1, 2 Input Receive data

output channel
1, 2

SCK1, 2 I/O Serial clock

input/output
channel 1, 2

RTS Output Transmit

request

CTS Input Transmit enable SCIF channel 1 transmit enable input pin

TCLKA
TCLKB
TCLKC
TCLKD

TIOCA0
TIOCB0
TIOCC0
TIOCD0

TIOCA1
TIOCB1

Input TPU timer clock

input A, B, C, D

I/O TPU input

capture/output
compare
(channel 0)

I/O TPU input

capture/output
compare
(channel 1)

General-purpose external output pin

Packet

These pins output receiving a DMA
transfer request to an external device

Pins that input DMA transfer requests
from an external device

SCIF channel 1 and 2 transmit data
output pins

SCIF channel 1 and 2 receive data input
pins

SCIF clock input/output pins

SCIF channel 1 transmit request output
pin

Pins that input an external clock to the
TPU counter

Channel 0 input capture input/
output compare output/PWM output pins

Channel 1 input capture input/
output compare output/PWM output pins

Rev. 2.00 Mar 09, 2006 page 19 of 906

REJ09B0292-0200

Section 1 Overview

Type Symbol I/O Name Function

Timer pulse
unit (TPU)

TIOCA2
TIOCB2

I/O TPU input

capture/output

Channel 2 input capture input/output

compare output/PWM output pins
compare
(channel 2)

16-bit
free-running
timer (FRT)

FTCI Input Counter clock

input

FTOA Output Output compare

FRC counter clock input pin

Output compare A output pin
A output

FTOB Output Output compare

Output compare B output pin
B output

FTI Input Input capture

Input capture input pin
input

Serial I/O
with FIFO
(SIOF)

SRXD0 Input Serial receive

data input 0

SRCK0 Input Serial receive

Serial receive data input ports

Serial receive clock ports
clock input 0

SRS0 Input Serial receive

synchronization

Serial receive synchronization input

ports
clock input 0

STXD0 Output Serial transmit

Serial data output ports
data output 0

STCK0 Input Serial transmit

Serial transmit clock ports
clock input 0

Serial I/O
(SIO)

STS0 I/O Serial transmit

synchronization

input/output 0

clock

SRXD1, 2 Input Serial receive

data input 1, 2

SRCK1, 2 Input Serial receive

Serial transmit synchronization

input/output ports

Serial receive data input ports

Serial receive clock ports
clock input 1, 2

SRS1, 2 Input Serial receive

synchronization

Serial receive synchronization input

ports
input 1, 2

STXD1, 2 Output Serial transmit

Serial data output ports
data output 1, 2

STCK1, 2 Input Serial transmit

Serial transmit clock ports
clock input 1, 2

STS1, 2 I/O Serial transmit

synchronization

Serial transmit synchronization

input/output ports
input/output 1, 2

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Section 1 Overview

Type Symbol I/O Name Function

I/O ports PA0–PA13*I/O General port General input/output port pins

Input or output can be specified bit by bit

PB0–PB15 I/O General port General input/output port pins

Input or output can be specified bit by bit

Note: * PA3 cannot be used; CKPO is valid instead.

1.3.3 Pin Multiplexing

Table 1.3 Pin Multiplexing

No. Function 1 Function 2 Function 3 Function 4 Type

12 PLLV

9 PLLV

CC

SS

11 PLLCAP1

10 PLLCAP2

19 EXTAL

21 XTAL

23 CKIO
24 CKPREQ/CKM
25 CKPACK 9 pins
8 RES System control

13 MD4

14 MD3

15 MD2

16 MD1

17 MD0 6 pins

5 NMI Interrupts
1 IRL3
2 IRL2
3 IRL1
4 IRL0
27 IVECF 6 pins

Clocks

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Section 1 Overview

No. Function 1 Function 2 Function 3 Function 4 Type

131 BS Bus control
138 CS4
137 CS3
136 CS2
135 CS1
134 CS0
148 BGR
145 BRLS
115 WAIT
128 RD
117 RAS
118 CAS/OE
119 DQMUU/WE3
120 DQMUL/WE2
121 DQMLU/WE1
122 DQMLL/WE0
123 CAS3
124 CAS2
125 CAS1
126 CAS0

127 CKE

129 REFOUT
133 RD/WR
139 BUSHiZ
140 BH 25 pins

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No. Function 1 Function 2 Function 3 Function 4 Type

111 A24 Address bus

108 A23

107 A22

106 A21

105 A20

104 A19

103 A18

102 A17

100 A16

98 A15

97 A14

96 A13

95 A12

94 A11

93 A10

92 A9

90 A8

88 A7

87 A6

86 A5

85 A4

84 A3

83 A2

82 A1

80 A0 25 pins

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Section 1 Overview

No. Function 1 Function 2 Function 3 Function 4 Type

77 D31 Data bus

75 D30

74 D29

73 D28

72 D27

71 D26

70 D25

68 D24

65 D23

64 D22

63 D21

62 D20

59 D19

57 D18

56 D17

55 D16

54 D15

53 D14

51 D13

49 D12

48 D11

47 D10

46 D9

44 D8

43 D7

41 D6

40 D5

39 D4

38 D3

37 D2

36 D1

34 D0 32 pins

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Section 1 Overview

No. Function 1 Function 2 Function 3 Function 4 Type

30 TCK H-UDI

31 TMS

29 TDI

28 TDO
32 TRST

6 ASEMODE

*

6 pins

201 TX-CLK EtherC

192 RX-CLK

203 TX-EN 5 V I/O compatibility

207 ETXD3

206 ETXD2

205 ETXD1

204 ETXD0

208 TX-ER

188 RX-DV

197 ERXD3

196 ERXD2

195 ERXD1

194 ERXD0

187 RX-ER

190 CRS

189 COL

199 MDC

198 MDIO 18 pins

143 DACK1 DMAC

144 DACK0

141 DREQ1

142 DREQ0 4 pins

Note: * When carrying out debugging using the E10A emulator, this pin is used for mode switching.

It should be connected to V

when using the E10A emulator (ASE mode). When using the

SS

chip in the normal user system, and not using the E10A emulator (user mode), connect this
pin to V

. When a boundary scan test is performed with the H-UDI, user mode must be

CC

used. A boundary scan test cannot be performed in ASE mode.

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Section 1 Overview

Function 1

No.

151 PB15 SCK1 Port B

152 PB14 RXD1 SCIF, SIO, TPU

153 PB13 TXD1
154 PB12 SRCK2 RTS STATS1 5 V I/O compatibility
156 PB11 SRS2 CTS STATS0

158 PB10 SRXD2 TIOCA1

159 PB9 STCK2 TIOCB1/TCLKC

160 PB8 STS2 TIOCA2

161 PB7 STXD2 TIOCB2/TCLKD

162 PB6 SRCK1 SCK2

163 PB5 SRS1 RXD2

164 PB4 SRXD1 TXD2

165 PB3 STCK1 TIOCA0

166 PB2 STS1 TIOCB0

168 PB1 STXD1 TIOCC0/TCLKA

170 PB0 TIOCD0/TCLKB WOL 16 pins

171 PA13 SRCK0 Port A

172 PA12 SRS0 SIOF, FRT, WDT,

173 PA11 SRXD0 EtherC

174 PA10 STCK0 5 V I/O compatibility

175 PA9 STS0

176 PA8 STXD0
177 WDTOVF PA7

178 PA6 FTCI

180 PA5 FTI

182 PA4 FTOA

183 CKPO FTOB

184 PA2 LNKSTA

185 PA1 EXOUT

186 PA0 CAMSEN 14 pins

Note: * Figures in square brackets indicate the settings of the mode bits (MD0, MD1) in the PFC in

*

[00]

order to select the multiplex functions in port A [0:13] and port B [0:15].
WDTOVF: In a reset, this pin becomes an output pin.

Function 2

*

[01]

Function 3

*

[10]

Function 4

*

[11]

Type

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Section 1 Overview

When used for general input/output, attention must be paid to the polarity of
this pin.

1.4 Processing States

State Transitions: The CPU has five processing states: the reset state, exception handling state,

bus-released state, program execution state, and power-down state. Figure 1.3 shows the state
transitions.

From any state when
RES = 0 and NMI = 1

Interrupt or DMA
address error

Bus-released state

Bus request

Bus request

received

Bus request
cleared

Bus request

cleared

received

SLEEP

instruction

(SBY = 0)

RST = 0, NMI = 0

RST = 0, NMI = 1

RST = 1,

NMI = 1

Exception-handling state

Bus
request

Exception

Bus request
cleared

Program execution state

MSTP

bit

cleared

From any state when
RES = 0 and NMI = 0

Manual reset statePower-on reset state

RST = 1,
NMI = 0

End of
exception
handling

MSTP
bit set

SLEEP
instruction
(SBY = 1)

Reset states

NMI interrupt

CKPREQ = 1

SBY bit set and
CKPREQ = 0

*

*

Sleep mode

Note: * clock pause function

Figure 1.3 Processing State Transitions

Standby mode

Module standby

Power-down state

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Section 1 Overview

• Reset State

In this state, the CPU is reset. The reset state is entered when the RES pin goes low. The
power-on reset state is entered if the NMI pin is high, and the manual reset state is entered if
the NMI pin is low.

• Exception Handling State

The exception handling state is a transient state that occurs when the CPU alters the normal
programming flow dues to a reset, interrupt, or other exception handling source.

In the case of a reset, the CPU fetches the execution start address as the initial value of the
program counter (PC) from the exception vector table, and the initial value of the stack pointer
(SP), stores these values, branches to the start address, and begins program execution at that
address.

In the case of an interrupt, etc., the CPU references the SP and saves the PC and status register
(SR) in the stack area. It fetches the start address of the exception service routine from the
exception vector table, branches to that address, and begins program execution.

Subsequently, the processing state is the program execution state.

• Program Execution State

In the program execution state the CPU executes program instructions in normal sequence.

• Power-Down State

In the power-down state the CPU stops operating to conserve power. The power-down state is
entered by executing a SLEEP instruction. The power-down state includes two modes—sleep
mode and standby mode—and a module standby function.

• Bus-Released State

In the bus-released state, the CPU releases the bus to a device that has requested it.

Power-Down State: In addition to the normal program execution state, another CPU processing
state called the power-down state is provided. In this state, CPU operation is halted and power
consumption is reduced. The power-down state includes two modes—sleep mode and standby
mode—and a module standby function.

• Sleep Mode

A transition to sleep mode is made if the SLEEP instruction is executed while the standby bit
(SBY) is cleared to 0 in standby control register 1 (SBYCR1). In sleep mode CPU operations
stop but data in the CPU’s internal registers and in on-chip cache memory and on-chip RAM is
retained. The functions of the on-chip supporting modules do not stop.

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Section 1 Overview

• Standby Mode

A transition to standby mode is made if the SLEEP instruction is executed while SBY is set to
1 in SBYCR1. In standby mode the CPU, the on-chip modules, and the oscillator all stop.

When entering standby mode, the DMAC’s DMA master enable bit should be cleared to 0.
Also, the cache should be turned off before entering this mode. The contents of the cache and
on-chip RAM are not retained in this mode.

Standby mode is exited by means of a reset or an external NMI interrupt. When standby mode
is exited, the normal program execution state is entered via the exception handling state after
the elapse of the oscillation settling time.

If a transition is made to standby mode using the clock pause function, it is possible to change
the frequency of the CKIO pin input clock, or to stop the clock itself. When SBY in SBYCR1
is set to 1 and a low level is applied to the CKPREQ/CKM pin, a transition is made to standby
mode and a low level is output from the CKPACK pin. The clock can then be stopped, or its
frequency changed.

On-chip supporting module states and pin states are the same as in the normal standby mode
entered by means of the SLEEP instruction. A transition to the program execution state is
made by applying a high level to the CKPREQ/CKM pin.

In this mode the oscillator is halted, greatly reducing power consumption.

• Module Standby Function

A module standby function is provided for the following on-chip supporting modules: the
direct memory access controller (DMAC), DSP, 16-bit free-running timer (FRT), serial
communication interface with FIFO (SCIF), serial I/O with FIFO (SIOF), serial I/O (SIO), user
break controller (UBC), and timer pulse unit (TPU). A module standby function is not
supported for the Ethernet controller (EtherC) or the Ethernet direct memory access controller
(E-DMAC).

Setting one of module stop bits 11 to 3 and 1 (MSTP11 to MSTP3, MSTP1) to 1 in the standby
control register (SBYCR1/2) stops the clock supply to the corresponding on-chip supporting
module. Use of this function enables power consumption to be reduced.

The module standby function is cleared by clearing the corresponding MSTP bit to 0.

DSP instructions must not be used when the DSP has been placed in the module standby state.

When using the DMAC module standby function, the direct memory access controller’s DMA
master enable bit should be cleared to 0.

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Section 1 Overview

Table 1.4 Power-Down State

State

On-chip

Mode

Sleep
mode

Standby
mode

Module
standby
function

Entering
Conditions Clock CPU

Executing
SLEEP
instruction
while SBY bit
is cleared in
SBYCR1

Executing
SLEEP
instruction
while SBY
bit is set in
SBYCR1

Setting
MSTP bit
corresponding
to individual
module

Operating Halted Operating Held Held

Halted Halted Halted and

Operating Operating

(DSP
halted)

Notes: 1. Depends on individual supporting module or pin.

2. DMAC and DSP registers and specified module interrupt vectors retain their set values.

Supporting
Modules

1

initialized

Clock supply
to specified
module
halted,
module
initialized

*

2

*

On-Chip

Cache or
CPU
Registers

Held Undefined

Held Held

On-Chip

RAM

Exiting
Conditions

1. Interrupt

2. DMA address
error

3. Power-on reset

4. Manual reset

1. NMI interrupt

2. Power-on reset

3. Manual reset

1. Clearing MSTP
bit

2. Power-on reset

3. Manual reset

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Section 2 CPU

Section 2 CPU

2.1 Register Configuration

The register set consists of sixteen 32-bit general registers, six 32-bit control registers and ten 32­bit system registers.

This chip is upwardly compatible with the SH-1, SH-2 on the object code level. For this reason,
several registers have been added to the previous SuperH microcontroller registers. The added
registers are the three control registers: repeat start register (RS), repeat end register (RE), and
modulo register (MOD) and the six system registers: DSP status register (DSR), and A0, A1, X0,
X1, Y0 and Y1 among the DSP data registers.

The general registers are used in the same manner as the SH-1, SH-2 with regard to SuperH
microcontroller-type instructions. With regard to DSP type instructions, they are used as address
and index registers for accessing memory.

2.1.1 General Registers

There are 16 general registers (Rn) numbered R0–R15, which are 32 bits in length. General
registers are used for data processing and address calculation.

With SuperH microcomputer type instructions, R0 is also used as an index register. Several
instructions are limited to use of R0 only. R15 is used as the hardware stack pointer (SP). Saving
and recovering the status register (SR) and program counter (PC) in exception processing is
accomplished by referencing the stack using R15.

With DSP type instructions, eight of the 16 general registers are used for the addressing of X, Y
data memory and data memory (single data) using the I bus.

R4, R5 are used as an X address register (Ax) for X memory accesses, and R8 is used as an X
index register (Ix). R6, R7 are used as a Y address register (Ay) for Y memory accesses, and R9 is
used as a Y index register (Iy). R2, R3, R4, R5 are used as a single data address register (As) for
accessing single data using the I bus, and R8 is used as a single data index register (Is).

DSP type instructions can simultaneously access X and Y data memory. There are two groups of
address pointers for designating X and Y data memory addresses.

Figure 2.1 shows the general registers.

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Section 2 CPU

Notes: 1.

*1

R0
R1

031

R2, [As]
R3, [As]
R4, [As, Ax]
R5, [As, Ax]
R6, [Ay]
R7, [Ay]
R8, [Ix, Is]
R9, [Iy]

*3
*3

*3

*3
*3
*3

*3

*3

R10
R11
R12
R13
R14

R15, SP

*2

R0 also functions as an index register in the indirect indexed register
addressing mode and indirect indexed GBR addressing mode. In some
instructions, only the R0 functions as a source register or destination register.

2.

R15 functions as a hardware stack pointer (SP) during exception processing.

3.

Used as memory address registers, memory index registers with DSP type
instructions.

Figure 2.1 General Register Configuration

With the assembler, symbol names are used for R2, R3 ... R9. If it is wished to use a name that
makes clear the role of a register for DSP type instructions, a different register name (alias) can be
used. This is written in the following manner for the assembler.

Ix: .REG (R8)

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Section 2 CPU

The name Ix is an alias for R8. The other aliases are assigned as follows:

Ax0: .REG (R4)
Ax1: .REG (R5)
Ix: .REG (R8)
Ay0: .REG (R6)
Ay1: .REG (R7)
Iy: .REG (R9)
As0: .REG (R4)
As1: .REG (R5) defined when an alias is required for single data transfer
As2: .REG (R2) defined when an alias is required for single data transfer
As3: .REG (R3) defined when an alias is required for single data transfer
Is: .REG (R8) defined when an alias is required for single data transfer

defined when an alias is required for single data transfer

2.1.2 Control Registers

The six 32-bit control registers consist of the status register (SR), repeat start register (RS), repeat
end register (RE), global base register (GBR), vector base register (VBR), and modulo register
(MOD).

The SR register indicates processing states.

The GBR register functions as a base address for the indirect GBR addressing mode, and is used
for such as on-chip peripheral module register data transfers.

The VBR register functions as the base address of the exception processing vector area (including
interrupts).

The RS and RE registers are used for program repeat (loop) control. The repeat count is
designated in the SR register repeat counter (RC), the repeat start address in the RS register, and
the repeat end address in the RE register. However, note that the address values stored in the RS
and RE registers are not necessarily always the same as the physical start and end address values
of the repeat.

The MOD register is used for modulo addressing to buffer the repeat data. The modulo addressing
designation is made by DMX or DMY, the modulo end address (ME) is designated in the upper 16
bits of the MOD register, and the modulo start address (MS) is designated in the lower 16 bits.
Note that the DMX and DMY bits cannot simultaneously designate modulo addressing. Modulo
addressing is possible with X and Y data transfer instructions (MOVX, MOVY). It is not possible
with single data transfer instructions (MOVS).

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Section 2 CPU

Figure 2.2 shows the control registers. Table 2.1 indicates the SR register bits.

Status register (SR)

31 28 27 1615 12 11 10 9 8 7 4 3 2 1 0

Repeat start register (RS)

31

RS

Repeat end register (RE)

31

RE

Global base register (GBR)

31

GBR

Vector base register (VBR)

31

VBR

STI3 I2 I1 I0 RF1 RF0QMDMXDMY00000000 RC

0

0

0

0

Modulo register (MOD)

31

ME MS

ME: Modulo end address
MS: Modulo start address

Figure 2.2 Control Register Configuration

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016 15

Section 2 CPU

Table 2.1 SR Register Bits

Bit Name (Abbreviation) Function

27–16 Repeat counter (RC) Designate the repeat count (2–4095) for repeat (loop)

control

11 Y pointer usage modulo

addressing designation
(DMY)

10 X pointer usage modulo

addressing designation
(DMX)

9 M bit Used by the DIV0S/U, DIV1 instructions

8 Q bit Used by the DIV0S/U, DIV1 instructions

7–4 Interrupt request mask

(I3–I0)

3–2 Repeat flags (RF1, RF0) Used in zero overhead repeat (loop) control. Set as

1 Saturation arithmetic bit

(S)

0 T bit For MOVT, CMP/cond, TAS, TST, BT, BT/S, BF,

31–28
15–12

0 bit 0: 0 is always read out; write a 0

1: modulo addressing mode becomes valid for Y
memory address pointer, Ay (R6, R7)

1: modulo addressing mode becomes valid for X
memory address pointer, Ax (R4, R5)

Indicate the receive level of an interrupt request (0 to

15)

below for an SETRC instruction

For 1 step repeat 00 RE—RS=–4

For 2 step repeat 01 RE—RS=–2

For 3 step repeat 11 RE—RS=0

For 4 steps or more 10 RE—RS>0

Used with MAC instructions and DSP instructions

1: Designates saturation arithmetic (prevents
overflows)

BF/S, SETT, CLRT and DT instructions,

0: represents false

1: represents true

For ADDV/ADDC, SUBV/SUBC, DIV0U/DIV0S, DIV1,
NEGC, SHAR/SHAL, SHLR/SHLL, ROTR/ROTL and
ROTCR/ROTCL instructions,

1: represents occurrence of carry, borrow, overflow or
underflow

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There are dedicated load/store instructions for accessing the RS, RE and MOD registers. For
example, the RS register is accessed as follows.

LDC Rm,RS; Rm→RS
LDC.L @Rm+,RS; (Rm)→RS,Rm+4→Rm
STC RS,Rn; RS→Rn
STC.L RS,@-Rn; Rn-4→Rn,RS→(Rn)

The following instructions set addresses in the RS, RE registers for zero overhead repeat control:

LDRS @(disp,PC); disp×2 + PC→RS
LDRE @(disp,PC); disp×2 + PC→RE

The GBR register and VBR register are the same as the previous SuperH microprocessor registers.
An RC counter and four control bits (DMX bit, DMY bit, RF1 bit, RF0 bit) have been added to
the SR register. The RS, RE and MOD registers are new registers.

2.1.3 System Registers

System registers consist of four 32-bit registers: high and low multiply and accumulate registers
(MACH and MACL), the procedure register (PR), and the program counter (PC). The MACH and
MACL store the results of multiplication or multiply and accumulate operations*. The PR stores
the return address from the subroutine procedure. The PC indicates the address of the program in
execution; it controls the flow of the processing. The PC indicates the fourth byte after the
instruction currently being executed. These registers are the same as those in the SuperH
microprocessor.

Note: These are used only when executing an instruction that was supported by SH-1 and SH-2.

They are not used for newly added multiplication instructions (PMULS).

31 0

MACH

MACL

31

PR

31

PC

Multiply and accumulate
register high (MACH)
Multiply and accumulate
register low (MACL)

0

Procedure register (PR)

0

Program counter (PC)

Figure 2.3 System Register Configuration

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Section 2 CPU

In addition, among the DSP unit usage registers (DSP registers) described in 2.1.4 DSP Registers,
the DSP status register (DSR) and the five registers A0, X0, X1, Y0 and Y1 of the eight data
registers are treated as system registers. Among these, the A0 is a 40-bit register, but when data is
output from the A0 register, the guard bit section (A0G) is disregarded; when data is input to the
A0 register, the MSB of the data is copied into the guard bit section (A0G).

2.1.4 DSP Registers

The DSP unit has eight data registers and one control register as its DSP registers.

The DSP data registers are comprised of the two 40-bit registers A0 and A1, and the six 32-bit
registers M0, M1, X0, X1, Y0 and Y1. The A0 and A1 registers have the 8-bit guard bits A0G and
A1G, respectively.

The DSP data registers are used for the transfer and processing of the DSP data of DSP instruction
operands. There are three types of instructions that access DSP data registers: those for DSP data
processing, and those for X or Y data transfer processing.

The control register is the 32-bit DSP status register (DSR) that represents operation results. The
DSR register has bits that represent operation results, a signed greater than bit (GT), a zero bit (Z),
a negative value bit (N), an overflow bit (V), a DSP status bit (DC: DSP condition), and a status
selection bit (CS: condition select) for controlling DC bit setting.

The DC bit represents one status flag and is very similar to the SuperH microprocessor CPU core
T bit. For conditional DSP type instructions, DSP data processing execution is controlled in
accordance with the DC bit. This control is related to execution in the DSP unit only, and only
DSP registers are updated. It bears no relation to address calculation or such SuperH
microprocessor CPU core execution instructions as load/store instructions. The control bits CS
(bits 2 to 0) designate the status for setting the DC bit.

DSP type instructions are comprised of unconditional DSP type instructions and conditional DSP
type instructions. The status and DC bits are updated in unconditional DSP type data processing,
with the exception of the PMULS, MOVX, MOVY and MOVS instructions. Conditional DSP
type instructions are executed according to the status of the DC bit, but regardless of whether or
not they are executed, the DSR register is not updated.

Figure 2.4 shows the DSP registers. The DSR register bit functions are shown in table 2.2.
Registers A0, X0, X1, Y0, Y1, and DSR are handled as system registers by CPU core instructions.

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Section 2 CPU

39 32 31 0

A0G
A1G

A0
A1
M0
M1

X0
X1
Y0
Y1

87654321031

GT Z N V CS[2:0] DC

Figure 2.4 DSP Register Configuration

DSP data registers

DSP status register (DSR)

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Section 2 CPU

Table 2.2 DSR Register Bits

Bit Name (Abbreviation) Function

31–8 Reserved bits 0: Always read out; always use 0 as a write value

7 Signed greater than bit

(GT)

6 Zero bit (Z) Indicates that the operation result is zero (0), or that

5 Negative bit (N) Indicates that the operation result is negative, or that

4 Overflow bit (V) Indicates that the operation result has overflowed

3–1 Status selection bits (CS) Designate the mode for selecting the operation result

0 DSP status bit (DC) Sets the status of the operation result in the mode

Indicates that the operation result is positive
(excepting 0), or that operand 1 is greater than
operand 2

1: Operation result is positive, or operand 1 is greater

operand 1 is equal to operand 2

1: Operation result is zero (0), or equivalence

operand 1 is smaller than operand 2

1: Operation result is negative, or operand 1 is
smaller

1: Operation result has overflowed

status set in the DC bit

Do not set either 110 or 111

000: Carry/borrow mode

001: Negative value mode

010: Zero mode

011: Overflow mode

100: Signed greater mode

101: Signed above mode

designated by the CS bits

0: Designated mode status not realized (unrealized)

1: Designated mode status realized

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Section 2 CPU

2.1.5 Notes on Guard Bits and Overflow Treatment

DSP unit data operations are fundamentally performed as 32-bit, but these operations are always
executed with a 40-bit length including the 8-bit guard section. When the guard bit section does
not match the value of the 32-bit section MSB, the operation result is treated as an overflow. In
this case, the N bit indicates the correct status of the operation result regardless of the existence or
not of an overflow. This is so even if the destination operand is a 32-bit length register. The 8-bit
section guard bits are always presupposed and each status flag is updated.

When place overflows occur so that the correct result cannot be displayed even when the guard
bits are used, the N flag cannot indicate the correct status.

2.1.6 Initial Values of Registers

Table 2.3 lists the values of the registers after reset.

Table 2.3 Initial Values of Registers

Classification Register Initial Value

General registers R0–R14 Undefined

R15 (SP) Value of the SP in the vector address table

Control registers SR Bits I3–I0 are 1111 (H'F), the reserved bits, RC, DMY,

and DMX are 0, and other bits are undefined

RS

RE

GBR Undefined

VBR H'00000000

MOD Undefined

System registers MACH, MACL, PR Undefined

PC Value of the PC in the vector address table

DSP registers A0, A0G, A1, A1G, M0,

M1, X0, X1, Y0, Y1

DSR H'00000000

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Undefined

Undefined

Section 2 CPU

2.2 Data Formats

2.2.1 Data Format in Registers

Register operand data size is always longword (32 bits). When loading data from memory into a
register, if the memory operand is a byte (8 bits) or a word (16 bits), it is sign-extended into a
longword, then loaded into the register.

31 0

Longword

Figure 2.5 Register Data Format

2.2.2 Data Formats in Memory

These formats are classified into bytes, words, and longwords.

Place byte data in any address, word data from 2n addresses, and longword data from 4n
addresses. An address error will occur if accesses are made from any other boundary. In such
cases, the access results cannot be guaranteed. In particular, the stack area referred to by the
hardware stack pointer (SP, R15) stores the program counter (PC) and status register (SR) as
longwords, so establish the hardware stack pointer so that a 4n value will always result.

To enable sharing of the processor accessing memory in little-endian mode and memory, the CS2,
4 space (area 2, 4) has a function that allows access in little-endian mode. The order of byte data
differs between little-endian mode and normal big-endian mode.

Address m + 1

23 7

WordWord

Longword

Little endian

Address 2n
Address 4n

Address 2n
Address 4n

Address m + 1 Address m + 3

Address m Address m + 2

31 015

23 7

Byte Byte Byte Byte

WordWord

Longword

Big endian

Address m + 3

Address m + 2 Address m

31 015

Byte Byte Byte Byte

Figure 2.6 Data Formats in Memory

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2.2.3 Immediate Data Format

Byte immediate data is placed in an instruction code.

With the MOV, ADD, and CMP/EQ instructions, immediate data is sign-extended and operated in
registers as longword data. Immediate data accessed by the TST, AND, OR, and XOR instructions
is zero-extended and handled as longword data. Consequently, AND instructions with immediate
data always clear the upper 24 bits of the destination register.

Word or longword immediate data is not located in the instruction code; it should be placed in a
memory table. Use an immediate data transfer instruction (MOV) to refer the memory table using
the PC relative addressing mode with displacement.

2.2.4 DSP Type Data Formats

This chip has three different types of data format that correspond to various instructions. These are
the fixed-point data format, the integer data format, and the logical data format.

The DSP type fixed-point data format has a binary point fixed between bits 31 and 30. There are
three types: with guard bits, without guard bits, and multiplication input; each with different valid
bit lengths and value ranges.

The DSP type integer data format has a binary point fixed between bits 16 and 15. There are three
types: with guard bits, without guard bits, and shift amount; each with different valid bit lengths
and value ranges. The shift amount of the arithmetic shift (PSHA) has a 7 bit range and can
express values from –64 to +63, but the actual valid values are from –32 to +32. In the same
manner, the shift amount of the logical shift has a 6 bit range, but the actual valid values are from
–16 to +16.

The DSP type logical data format does not have a decimal point.

The data format and valid data length are determined by the instructions and DSP registers.

Figure 2.7 shows the three DSP type data formats and binary point positions. The SuperH type
data format is also shown for reference.

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DSP fixed decimal

point data

With guard bits

No guard bits

39

Section 2 CPU

30

323231

S

30

31

S

0

8

to +28 – 2

–2

0

–1 to +1 – 2

–31

–31

Multiplication input

DSP integer data

With guard bits

No guard bits

Arithmetic shift (PSHA)

Logical shift (PSHL)

SuperH integer (word)

(Reference)

39

39

39

30

31

16 15

S

31

16

15

S

31

16

15

S

31

22

16

15

S

31

21

16

15

S

31

16

15

0

–1 to +1 – 2

0

–223 to +2

0

15

–2

0

–32 to +32

0

–16 to +16

0

to +2

23

15

–15

–1

–1

(16 bits)DSP logical data

31

S

0

31

31

–2

to +2

–1

: Sign bitS
: Binary decimal point

: Unrelated to processing (ignored)

Figure 2.7 DSP Type Data Formats

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Section 2 CPU

2.2.5 DSP Type Instructions and Data Formats

The DSP data format and valid data length are determined by DSP type instructions and DSP
registers. There are three types of instructions that access DSP data registers, DSP data processing,
X, Y data transfer processing, and single data transfer processing instructions.

DSP Data Processing: The guard bits (bits 39–32) are valid when the A0 and A1 registers are
used as source registers in DSP fixed-point data processing. When any registers other than A0, A1
(e.i., M0, M1, X0, X1, Y0, Y1 registers) are used as source registers, the sign-extended part of that
register data becomes the bits 39 to 32 data. When the A0 and A1 registers are used as destination
registers, the guard bits (bits 39–32) are valid. When any registers other than A0, A1 are used as
destination registers, bits 39 to 32 of the result data are disregarded.

Processing for DSP integer data is the same as the DSP fixed-point data processing. However, the
lower word (the lower 16 bits, bits 15–0) of the source register is disregarded. The lower word of
the destination register is cleared to 0.

In DSP logical data processing, the upper word (the upper 16 bits, bits 31–16) of the source
register is valid. The lower word and the guard bits of the A0, A1 registers are disregarded. The
upper word of the destination register is valid. The lower word and the guard bits of the A0, A1
registers are cleared to 0.

X, Y Data Transfers: The MOVX.W and MOVY.W instructions access X, Y memory via the
16-bit X, Y data buses. The data loaded into registers and data stored from registers is always the
upper word (the upper 16 bits, bits 31–16).

When loading, the MOVX.W instruction loads X memory, with the X0 and X1 registers as the
destination registers. The MOVY.W instruction loads Y memory, with the Y0 and Y1 registers as
the destination registers. Data is stored in the upper word of the register; the lower word is cleared
to 0.

The upper word data of the A0, A1 registers can be stored in X or Y memory with these data
transfer instructions, but storing is not possible from any other registers. The guard bits and the
lower word of the A0, A1 registers are disregarded.

Single Data Transfers: The MOVS.W and MOVS.L instructions can access any memory via the
data bus (CDB). All DSP registers are connected to the CDB bus, and they can become source or
destination registers during data transfers. The two data transfer modes are word and longword.

In word mode, data is loaded to and stored in the upper word of the DSP register, with the
exception of the A0G, A1G registers. In longword mode, data is loaded to and stored in the 32 bits
of the DSP register, with the exception of the A0G, A1G registers. The A0G, A1G registers can be

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Section 2 CPU

treated as independent registers during single data transfers. The load/store data length for the
A0G, A1G registers is 8 bits.

If DSP registers are used as source registers in word mode, when data is stored from any registers
other than A0G, A1G, the data in the upper word of the register is transferred. In the case of the
A0, A1 registers, the guard bits are disregarded. When the A0G, A1G registers are the source
registers in word mode, only 8 bits of the data are stored from the registers; the upper bits are sign­extended.

If the DSP registers are used as destination registers in word mode, the load is to the upper word of
the register, with the exception of A0G, A1G. When data is loaded to any register other than A0G,
A1G, the lower word of the register is cleared to 0. In the case of the A0, A1 registers, the data
sign is extended and stored in the guard bits; the lower word is cleared to 0. When the A0G, A1G
registers are the destination registers in word mode, the least significant 8 bits of the data are
loaded into the registers; the A0, A1 registers are not zero cleared but retain their previous values.

If the DSP registers are used as source registers in longword mode, when data is stored from any
registers other than A0G, A1G, the 32 bits (data) of the register are transferred. When the A0, A1
registers are used as the source registers the guard bits are disregarded. When the A0G, A1G
registers are the source registers in longword mode, only 8 bits of the data are stored from the
registers; the upper bits are sign-extended.

If the DSP registers are used as destination registers in longword mode, the load is to the 32 bits of
the register, with the exception of A0G, A1G. In the case of the A0, A1 registers, the data sign is
extended and stored in the guard bits. When the A0G, A1G registers are the destination registers in
longword mode, the least significant 8 bits of the data are loaded into the registers; the A0, A1
registers are not zero cleared but retain their previous values.

Tables 2.4 and 2.5 indicate the register data formats for DSP instructions. Some registers cannot
be accessed by certain instructions. For example, the PMULS instruction can designate the A1
register as a source register but cannot designate A0 as such. Refer to the instruction explanations
for details.

Figure 2.8 shows the relationship between the buses and the DSP registers during transfers.

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Table 2.4 Source Register Data Formats for DSP Instructions

Guard Bits

Register Instruction 39–32 31–16 15–0

A0, A1 DSP

operation

Data
transfer

A0G, A1G Data MOVS.W Data — —

transfer

X0, X1, Y0,
Y1, M0, M1

Note: * The sign is extended and stored in the ALU’s guard bits.

DSP
operation

Data MOVS.W
transfer

Fixed decimal,
PDMSB,
PSHA

Integer 24-bit data —

Logic, PSHL,
PMULS

MOVX.W,
MOVY.W,
MOVS.W

MOVS.L 32-bit data

MOVS.L

Fixed decimal,
PDMSB,
PSHA

Integer 16-bit data —

Logic, PSHL,
PMULS

MOVS.L 32-bit data

40-bit data

— 16-bit data

*

Sign

—

32-bit data

Register Bits

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Table 2.5 Destination Register Data Formats for DSP Instructions

Section 2 CPU

Guard Bits

Register Instruction 39–32 31–16 15–0

A0, A1 DSP

operation

Data transfer MOVS.W Sign extend

A0G, A1G Data transfer MOVS.W Data Not updated Not updated

X0, X1, Y0,
Y1, M0, M1

DSP
operation

Data transfer MOVX.W,

Fixed
decimal,
PSHA,
PMULS

Integer,
PDMSB

Logic, PSHL Clear to 0 16-bit result

MOVS.L 32-bit data

MOVS.L

Fixed
decimal,
PSHA,
PMULS

Integer, logic,
PDMSB,
PSHL

MOVY.W,
MOVS.W

MOVS.L 32-bit data

(Sign extend) 40-bit result

24-bit result Clear to 0

— 32-bit result

16-bit result Clear to 0

Register Bits

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32 bits
16 bits
16 bits

8 bits

[7:0]

MOVS.W,
MOVS.L

39 32

A0G
A1G

DSR

70

16 bits

MOVX.W,
MOVY.W

31

16

A0
A1
M0

M1
X0

X1
Y0

Y1

Figure 2.8 DSP Register-Bus Relationship during Data Transfers

2.3 CPU Core Instruction Features

The CPU core instructions are RISC type. The characteristics are as follows.

CDB
XDB
YDB

32 bits

MOVS.W,
MOVS.L

0

16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency.

One Instruction per Cycle: The microprocessor can execute basic instructions in one cycle using

the pipeline system. One state equals 16.0 ns when operating at 62.5 MHz.

Data Length: Longword is the basic data length for all operations. Memory can be accessed in
bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and
handled as longword data. Immediate data is sign-extended for arithmetic operations or zero­extended for logic operations. It also is handled as longword data.

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Table 2.6 Sign Extension of Word Data

SH7616 CPU Description Example of Conventional CPU

MOV.W @(disp,PC),R1

ADD R1,R0

........

.DATA.W H'1234

Note: @(disp, PC) accesses the immediate data.

Data is sign-extended to 32
bits, and R1 becomes
H'00001234. It is next operated
upon by an ADD instruction

ADD.W #H'1234,R0

Load-Store Architecture: Basic operations are executed between registers. For operations that
involve memory access, data is loaded to the registers and executed (load-store architecture).
However, Instructions such as AND manipulating bits, are executed directly in memory.

Delayed Branches: Such instructions as unconditional branches are delayed branch instructions.
In the case of delayed branch instructions, the branch occurs after execution of the instruction
immediately following the delayed branch instruction (slot instruction). This reduces pipeline
disruption during branching.

The branching operation of the delayed branch occurs after execution of the slot instruction.
However, with the exception of such branch operations as register updating, execution of
instructions is performed with the order of delayed branch instruction, then delayed slot
instruction.

For example, even if the contents of a register storing a branch destination address are modified by
a delayed slot, the branch destination address will still be the contents of the register before the
modification.

Table 2.7 Delayed Branch Instructions

SH7616 CPU Description Example of Conventional CPU

BRA TRGET

ADD R1,R0

Executes an ADD before
branching to TRGET

ADD.W R1,R0

BRA TRGET

Multiplication/Multiply-Accumulate Operation: 16 × 16 → 32 multiplications execute in one
to three cycles, and 16 × 16 + 64 → 64 multiply-accumulate operations execute in two to three
cycles. 32 × 32 → 64 multiplications and 32 × 32 + 64 → 64 multiply-accumulate operations

execute in two to four cycles.

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T Bit: The T bit in the status register (SR) changes according to the result of a comparison, and
conditional branches occur in accordance with its true or false status. The number of instructions
modifying the T bit is kept to a minimum to improve the processing speed.

Table 2.8 T Bit

SH7616 CPU Description Example of Conventional CPU

CMP/GE R1,R0

BT TRGET0

BF TRGET1

ADD #–1,R0

CMP/EQ #0,R0

BT TRGET

T bit is set when R0 ≥ R1.

The program branches to TRGET0

when R0 ≥ R1.

The program branches to TRGET1
when R0 < R1

T bit is not changed by ADD. T bit
is set when R0 = 0. The program
branches when R0 = 0

CMP.W R1,R0

BGE TRGET0

BLT TRGET1

SUB.W #1,R0

BEQ TRGET

Immediate Data: Byte immediate data resides in instruction code. Word or longword immediate
data is not input in instruction codes but is stored in a memory table. An immediate data transfer
instruction (MOV) accesses the memory table using the PC relative addressing mode with
displacement.

Table 2.9 Immediate Data Accessing

Classification SH7616 CPU Example of Conventional CPU

8-bit immediate MOV #H'12,R0 MOV.B #H'12,R0

16-bit immediate MOV.W @(disp,PC),R0

........

.DATA.W H'1234

32-bit immediate MOV.L @(disp,PC),R0

........

.DATA.L H'12345678

Note: @(disp, PC) accesses the immediate data.

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MOV.W #H'1234,R0

MOV.L #H'12345678,R0

Section 2 CPU

Absolute Address: When data is accessed by absolute address, the value already in the absolute
address is placed in the memory table. Loading the immediate data when the instruction is
executed transfers that value to the register and the data is accessed in the indirect register
addressing mode.

Table 2.10 Absolute Address Accessing

Classification SH7616 CPU Example of Conventional CPU

Absolute address MOV.L @(disp,PC),R1

MOV.B @R1,R0

........

.DATA.L H'12345678

MOV.B @H'12345678,R0

16-Bit/32-Bit Displacement: When data is accessed by 16-bit or 32-bit displacement, the pre­existing displacement value is placed in the memory table. Loading the immediate data when the
instruction is executed transfers that value to the register and the data is accessed in the indirect
indexed register addressing mode.

Table 2.11 Displacement Accessing

Classification SH7616 CPU Example of Conventional CPU

16-bit displacement MOV.W @(disp,PC),R0

MOV.W @(R0,R1),R2

........

.DATA.W H'1234

MOV.W @(H'1234,R1),R2

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2.4 Instruction Formats

2.4.1 CPU Instruction Addressing Modes

The addressing modes and effective address calculation for instructions executed by the CPU core
are listed in table 2.12.

Table 2.12 CPU Instruction Addressing Modes and Effective Addresses

Addressing
Mode

Direct register
addressing

Indirect register
addressing

Post-increment
indirect register
addressing

Pre-decrement
indirect register
addressing

Instruction
Format Effective Addresses Calculation Equation

Rn The effective address is register Rn

(The operand is the contents of register Rn)

@Rn The effective address is the content of register

Rn

Rn Rn

@Rn+ The effective address is the content of register

Rn. A constant is added to the content of Rn after
the instruction is executed. 1 is added for a byte
operation, 2 for a word operation, and 4 for a
longword operation

Rn

Rn + 1/2/4

1/2/4

@–Rn The effective address is the value obtained by

subtracting a constant from Rn. 1 is subtracted
for a byte operation, 2 for a word operation, and
4 for a longword operation

Rn

Rn – 1/2/4

1/2/4

+

–

Rn

Rn – 1/2/4

—

Rn

Rn

(After the
instruction
executes)

Byte: Rn + 1 → Rn
Word: Rn + 2 → Rn

Longword: Rn + 4

→ Rn

Byte: Rn – 1 → Rn

Word: Rn – 2
Rn

Longword: Rn – 4

→ Rn (Instruction

executed with Rn
after calculation)

→

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Addressing
Mode

Indirect register
addressing
with
displacement

Indirect indexed
register
addressing

Indirect GBR
addressing with
displacement

Instruction
Format Effective Addresses Calculation Equation

@(disp:4,
Rn)

The effective address is Rn plus a 4-bit
displacement (disp). The value of disp is zero­extended, and remains the same for a byte
operation, is doubled for a word operation, and is
quadrupled for a longword operation

Byte: Rn + disp

Word: Rn + disp ×

2

Longword: Rn +

disp × 4

Rn

disp

(zero-extended)

1/2/4

+

×

@(R0, Rn) The effective address is the Rn value plus R0

Rn

+

R0

@(disp:8,
GBR)

The effective address is the GBR value plus an
8-bit displacement (disp). The value of disp is
zero-extended, and remains the same for a byte
operation, is doubled for a word operation, and
is quadrupled for a longword operation

GBR
disp

(zero-extended)

+

×

Rn

+ disp × 1/2/4

Rn + R0

Rn + R0

Byte: GBR + disp

Word: GBR + disp

× 2

Longword: GBR +

disp × 4

GBR

+ disp × 1/2/4

1/2/4

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Section 2 CPU

Addressing
Mode

Indirect
indexed GBR
addressing

PC relative
addressing
with
displacement

Instruction
Format Effective Addresses Calculation Equation

@(R0,
GBR)

The effective address is the GBR value plus the R0

GBR

+

GBR + R0

GBR + R0

R0

@(disp:8,
PC)

The effective address is the PC value plus an
8-bit displacement (disp). The value of disp is zero­extended, is doubled for a word operation, and is
quadrupled for a longword operation. For a
longword operation, the lowest two bits of the PC
value are masked

PC

(for longword)

&

H'FFFFFFFC

+

disp

(zero-extended)

×

PC + disp × 2

or

PC&H'FFFFFFFC

+ disp × 4

Word: PC + disp

× 2

Longword: PC &
H'FFFFFFFC +

disp × 4

2/4

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PC relative
addressing

disp:8 The effective address is the PC value sign-extended

with an 8-bit displacement (disp), doubled, and
added to the PC value

PC

disp

(sign-extended)

2

+

PC + disp × 2

×

disp:12 The effective address is the PC value sign-extended

with a 12-bit displacement (disp), doubled, and
added to the PC value

PC
disp

(sign-extended)

2

+

PC + disp × 2

×

Rn The effective address is the register PC value plus

Rn

PC

PC + disp × 2

PC + disp × 2

PC + Rn

Immediate
addressing

+

Rn

PC + Rn

#imm:8 The 8-bit immediate data (imm) for the TST, AND,

OR, and XOR instructions are zero-extended

#imm:8 The 8-bit immediate data (imm) for the MOV, ADD,

and CMP/EQ instructions are sign-extended

#imm:8 The 8-bit immediate data (imm) for the TRAPA

instruction is zero-extended and is quadrupled

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—

—

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Section 2 CPU

2.4.2 DSP Data Addressing

There are two different kinds of memory accesses with DSP instructions. One type is with the X,
Y data transfer instructions (MOVX.W, MOVY.W), and the other is with the single data transfer
instructions (MOVS.W, MOVS.L). The data addressing differs between these two types of
instructions. Table 2.13 shows a summary of the data transfer instructions.

Table 2.13 Overview of Data Transfer Instructions

X, Y Data Transfer Processing

Classification

Address registers Ax: R4, R5; Ay: R6, R7 As: R2, R3, R4, R5

Index registers Ix: R8, Iy: R9 Is: R8

Addressing Nop/Inc(+2)/index addition: post-

Modulo addressing Possible Not possible

Data bus XDB, YDB CDB

Data length 16 bit (word) 16 bit/32 bit (word/longword)

Bus contention None Yes

Memory X, Y data memory All memory spaces

Source registers Dx, Dy: A0, A1 Ds: A0/A1, M0/M1, X0/X1, Y0/Y1,

Destination registers Dx: X0/X1; Dy: Y0/Y1 Ds: A0/A1, M0/M1, X0/X1, Y0/Y1,

(MOVX.W, MOVY.W)

update

— Dec(–2,–4): pre-update

Single Data Transfer Processing
(MOVS.W, MOVS.L)

Nop/Inc(+2,+4)/index addition: post­update

A0G, A1G

A0G, A1G

X, Y Data Addressing: Among the DSP instructions, the MOVX.W and MOVY.W instructions
can be used to simultaneously access X, Y data memory. The DSP instructions have two address
pointers for simultaneous accessing of X, Y data memory. Only pointer addressing is possible with
DSP instructions; there is no immediate addressing. The address registers are divided into two; the
R4, R5 registers become the X memory address register (Ax), and the R6, R7 registers become the
Y memory address register (Ay). The following three types of addressing exist with X, Y data
transfer instructions.

1. Non-updated address registers: The Ax, Ay registers are address pointers. They are not
updated.

2. Add index registers: The Ax, Ay registers are address pointers. The Ix, Iy register values are
added to them, respectively, after the data transfer (post-update).

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3. Increment address registers: The Ax, Ay registers are address pointers. The value +2 is added
to each of them after the data transfer (post-update).

Each of the address pointers has an index register. The R8 register becomes the index register (Ix)
of the X memory address register (Ax), and the R9 register becomes the index register (Iy) of the
Y memory address register (Ay).

The X, Y data transfer instructions are processed in word lengths. X, Y data memory is accessed
in 16 bit lengths. This is why the increment processing adds 2 to the address registers. In order to
decrement, set –2 in the index register and designate add index register addressing. During X, Y
data addressing, only bits 1 to 15 of the address pointer are valid. Always write a 0 to bit 0 of the
address pointer and the index register during X, Y data addressing.

Figure 2.9 shows the X, Y data transfer addressing. When X memory and Y memory are accessed
using the X, Y bus, the upper word of Ax (R4 or R5) and Ay (R6 or R7) is ignored. The result of
@Ay+ and @Ay+Iy is stored in the lower word of Ay, and the upper word retains its original
value.

R8[Ix] R4[Ax]

+2 (INC) +2 (INC)
+0 (No update)

ALU AU*

Notes:

All three addressing methods (increment, index register addition (Ix, Iy), and
no update) are post-updating methods. To decrement the address pointer, set
the index register to –2 or –4.
* Adder added for DSP addressing.

R5[Ax]

+0 (No update)

Figure 2.9 X, Y Data Transfer Addressing

R9[Iy] R6[Ay]

R7[Ay]

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Single Data Addressing: Among the DSP instructions, the single data transfer instructions
(MOVS.W and MOVS.L) are used to either load data into DSP registers or to store it from them.
With these instructions, the registers R2 to R5 are used as address registers (As) for the single data
transfers.

The four following data addressing instructions exist for single data transfer instructions.

1. Non-updated address registers: The As registers are address pointers. They are not updated.

2. Add index registers: The As registers are address pointers. The Is register values are added to
them after the data transfer (post-update).

3. Increment address registers: The As registers are address pointers. The value +2 or +4 is added
after the data transfer (post-update).

4. Decrement address registers: The As registers are address pointers. The value –2 or –4 is added
(+2 or +4 is subtracted) before the data transfer (pre-update).

The address pointer (As) uses the R8 register as an index register (Is).

Figure 2.10 shows the single data transfer addressing.

31 0

R8[Is]

–2/–4 (DEC)
+2/+4 (INC)
+0 (No update)

Note: There are four addressing methods (no update, index register addition (Is),
increment, and decrement). Index register addition and increment are
post-updating methods. Decrement is a pre-updating method.

Figure 2.10 Single Data Transfer Addressing

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ALU

31

0

R2[As]
R3[As]

R4[As]
R5[As]

31

MAB

CAB

0

Section 2 CPU

Modulo Addressing: The chip has a modulo addressing mode, just as other DSPs do. Address
registers are updated in the same manner as with other modes. When the address pointer value
becomes the same as a previously established modulo end address, the address pointer becomes
the modulo start address.

Modulo addressing is valid only with X, Y data transfer instructions (MOVX.W, MOVY.W).
When the DMX bit of the SR register is set, the X address register enters modulo addressing
mode; when the DMY bit of the SR register is set, the Y address register does so. Modulo
addressing is valid only for either the X or the Y address register; it is not possible to make them
both modulo addressing mode at the same time. Therefore, do not simultaneously set the DMX
and DMY. If they happen to be set at the same time, only the DMY side is valid.

The MOD register is used to designate the start and end addresses of the modulo address area; it
stores the MS (modulo start) and ME (modulo end). An example of MOD register (MS, ME)
usage is indicated below.

MOV.L ModAddr,Rn; Rn=ModEnd, ModStart
LDC Rn,MOD; ME=ModEnd, MS=ModStart

ModAddr: .DATA.W mEnd; ModEnd

.DATA.W mStart; ModStart

ModStart: .DATA

:

ModEnd: .DATA

Designate the start and end addresses in MS and ME, and then set the DMX or DMY bit to 1. The
contents of the address register are compared with ME. If they match ME, the start address MS is
stored in the address register. The lower 16 bits of the address register are compared with ME. The
maximum modulo size is 64 kbytes. This is sufficient for X, Y data memory accesses. Figure 2.11
shows a block diagram of modulo addressing.

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Section 2 CPU

31 0

R8[Ix]

+2

+0

31

16

R4[Ax]
R5[Ax]

Instruction (MOVX/MOVY)

DMY

15

DMX

0

CONT

15

1

MS

31

15

16
R6[Ay]
R7[Ay]

0

31

R9[Iy]

0

+2
+0

ALU

CMP

ABx ABy

15

XAB

1

15

ME

1

15

YAB

Figure 2.11 Modulo Addressing

An example of modulo addressing is indicated below:

MS=H'E008; ME=H'E00C; R4=H'1000E008;
DMX=1; DMY=0; (sets modulo addressing for address register Ax (R4, R5))

The R4 register changes as follows due to the above settings.

R4: H'1000E008
Inc. R4: H'1000E00A
Inc. R4: H'1000E00C
Inc. R4: H'1000E008

(becomes the modulo start address because the modulo end
address occurred)

AU

1

Data is placed so that the upper 16 bits of the modulo start and end addresses become identical.
This is so because the modulo start address replaces only the lower 15 bits of the address register,
excepting bit 0.

Note: When using add index with DSP data addressing, there are cases where the value is

exceeded without the address pointer matching the ME. In such cases, the address pointer
does not return to the modulo start address. Bit 0 is disregarded not only for modulo
addressing, but also during X, Y data addressing, so always write 0 to the 0 bits of the
address pointer, index register, MS, and ME.

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Section 2 CPU

DSP Addressing Operation: The DSP addressing operation in the item stage (EX) of the
pipeline, including modulo addressing, is indicated below.

if ( Operation is MOVX.W MOVY.W ) {

ABx=Ax; ABy=Ay;
/* memory access cycle uses ABx and ABy. The addresses to be used

have not been updated */

/* Ax is one of R4,5 */
if ( DMX==0 || DMX==1 && DMY==1 )} Ax=Ax+(+2 or R8[Ix} or +0);
/* Inc,Index,Not-Update */
else if (!not-update) Ax=modulo( Ax, (+2 or R8[Ix]) );

/* Ay is one of R6,7 */
if ( DMY==0 ) Ay=Ay+(+2 or R9[Iy] or +0; /* Inc,Index,Not-Update */

else if (! not-update) Ay=modulo( Ay, (+2 or R9[Iy]) );
}
else if ( Operation is MOVS.W or MOVS.L ) {

if ( Addressing is Nop, Inc, Add-index-reg ) {

MAB=As;
/* memory access cycle uses MAB. The address to be used has not

been updated */

/* As is one of R2–5 */

As=As+(+2 or +4 or R8[Is] or +0); /* Inc.Index,Not-Update */
else { /* Decrement, Pre-update */
/* As is one of R2–5 */
As=As+(–2 or –4);
MAB=As;
/* memory access cycle uses MAB. The address to be used has been

updated */
}

/* The value to be added to the address register depends on addressing
operations.

For example, (+2 or R8[Ix] or +0) means that

+2: if operation is increment

R8[Ix}: if operation is add-index-reg

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Section 2 CPU

+0: if operation is not-update

*/

function modulo ( AddrReg, Index ) {

if ( AdrReg[15:0]==ME ) AdrReg[15:0]=MS;
else AdrReg=AdrReg+Index;
return AddrReg;

}

2.4.3 Instruction Formats for CPU Instructions

The instruction format of instructions executed by the CPU core and the meanings of the source
and destination operands are indicated below. The meaning of the operand depends on the
instruction code. The symbols are used as follows:

• xxxx: Instruction code

• mmmm: Source register

• nnnn: Destination register

• iiii: Immediate data

• dddd: Displacement

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Table 2.14 Instruction Formats for CPU Instructions

Instruction Formats Source Operand

0 format

15 0

xxxx xxxx xxxxxxxx

——NOP

Section 2 CPU

Destination
Operand Example

n format

15 0

xxxx xxxx xxxxnnnn

m format

15 0

mmmm

xxxx xxxx

xxxx

— nnnn: Direct

register

Control register or
system register

Control register or
system register

mmmm: Direct
register

mmmm: Indirect post­increment register

mmmm: Indirect

nnnn: Direct

register
nnnn: Indirect pre-

decrement register

Control register or
system register

Control register or
system register

— JMP @Rm

register
mmmm: PC relative

— BRAF Rm

using Rm

MOVT Rn

STS MACH,Rn

STC.L SR,@-Rn

LDC Rm,SR

LDC.L @Rm+,SR

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Section 2 CPU

Instruction Formats Source Operand

nm format mmmm: Direct

register

15 0

xxxx xxxx

nnnn

mmmm

mmmm: Direct
register

Destination
Operand Example

nnnn: Direct

ADD Rm,Rn

register
nnnn: Indirect

MOV.L Rm,@Rn

register

md format

15 0

xxxx dddd

xxxx

mmmm

nd4 format

15 0

xxxx

xxxx

nnnn

dddd

nmd format

15 0

xxxx dddd

nnnn

mmmm

mmmm: Indirect post-

MACH, MACL MAC.W
increment register
(multiply/
accumulate)

nnnn: Indirect post­increment register
(multiply/
accumulate)

mmmm: Indirect post­increment register

mmmm: Direct
register

mmmm: Direct
register

mmmmdddd: indirect

*

nnnn: Direct

register

nnnn: Indirect pre-

decrement register

nnnn: Indirect

indexed register

R0 (Direct register) MOV.B
register with
displacement

R0 (Direct register) nnnndddd: Indirect

register with

displacement

mmmm: Direct
register

nnnndddd: Indirect

register with

displacement

@Rm+,@Rn+

MOV.L @Rm+,Rn

MOV.L Rm,@-Rn

MOV.L
Rm,@(R0,Rn)

@(disp,Rm),R0

MOV.B
R0,@(disp,Rn)

MOV.L
Rm,@(disp,Rn)

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mmmmdddd: Indirect
register
with displacement

nnnn: Direct

register

MOV.L
@(disp,Rm),Rn

Instruction Formats Source Operand

d format

15 0

xxxx

xxxx

dddd

dddd

dddddddd: Indirect
GBR with
displacement

Section 2 CPU

Destination
Operand Example

R0 (Direct register) MOV.L

@(disp,GBR),R0

R0(Direct register) dddddddd: Indirect

dddddddd: PC
relative with
displacement

dddddddd: PC
relative

d12 format

15 0

xxxx

dddd

dddd dddd

nd8 format

15 0

xxxx

nnnn

dddd

dddd

dddddddddddd:
PC relative

dddddddd: PC
relative with
displacement

i format iiiiiiii:

Immediate

15 0

xxxx

xxxx

i i i i

i i i i

iiiiiiii:
Immediate

iiiiiiii:

Immediate

ni format

15 0

xxxx

nnnn

i i i i

i i i i

iiiiiiii:
Immediate

MOV.L

GBR with

R0,@(disp,GBR)

displacement

R0 (Direct register) MOVA

@(disp,PC),R0

— BF label

— BRA label

(label=disp+PC)

nnnn: Direct
register

Indirect indexed
GBR

MOV.L
@(disp,PC),Rn

AND.B
#imm,@(R0,GBR)

R0 (Direct register) AND #imm,R0

— TRAPA #imm

nnnn: Direct

ADD #imm,Rn

register

Note: * In multiply/accumulate instructions, nnnn is the source register.

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Section 2 CPU

2.4.4 Instruction Formats for DSP Instructions

New instructions have been added for digital signal processing. The new instructions are divided
into the two following types.

1. Memory and DSP register double, single data transfer instructions (16 bit length)

2. Parallel processing instructions processed by the DSP unit (32 bit length)

Figure 2.12 shows each of the instruction formats.

CPU core

instructions

Double data

transfer instructions

Single data

transfer instructions

Parallel processing

instructions

15

0 0 0 0

to

1 1 1 0

15

1 1 1 1 0 0

15

1 1 1 1 0 1

1 1 1 1 1 0

10109

A field

9

A field

A field

0

0

0

15

1626 25

B field

031

Figure 2.12 Instruction Formats for DSP Instructions

Double, Single Data Transfer Instructions: Table 2.15 indicates the data formats for double data

transfer instructions, and table 2.16 indicates the data formats for single data transfer instructions.

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Section 2 CPU

Table 2.15 Instruction Formats for Double Data Transfers

Category Mnemonic 15 14 13 12 11 10 9 8

X memory NOPX 11110 0 0
data transfers

Y memory NOPY 11110 0 0
data transfers

Category Mnemonic 7 6 5 4 3 2 1 0

X memory NOPX 0000
data transfers

Y memory NOPY 00 00
data transfers

Ax: 0=R4, 1=R5 Ay: 0=R6, 1=R7 Dx: 0=X0, 1=X1 Dy: 0=Y0, 1=Y1 Da: 0=A0, 1=A1

MOVX.W @Ax,Dx
MOVX.W @Ax+,Dx
MOVX.W @Ax+Ix,Dx

MOVX.W Da,@Ax
MOVX.W Da,@Ax+
MOVX.W Da,@Ax+Ix

MOVY.W @Ay,Dy
MOVY.W @Ay+,Dy
MOVY.W @Ay+Iy,Dy

MOVY.W Da,@Ay
MOVY.W Da,@Ay+
MOVY.W Da,@Ay+Iy

MOVX.W @Ax,Dx
MOVX.W @Ax+,Dx
MOVX.W @Ax+Ix,Dx

MOVX.W Da,@Ax
MOVX.W Da,@Ax+
MOVX.W Da,@Ax+Ix

MOVY.W @Ay,Dy
MOVY.W @Ay+,Dy
MOVY.W @Ay+Iy,Dy

MOVY.W Da,@Ay
MOVY.W Da,@Ay+
MOVY.W Da,@Ay+Iy

Dx 0 0

Da 1 0

Dy 0 0

Da 1 0

Ax

Ay

1

1

0

1

1

1

1

0

1

1

1

1

0

1

1

1

1

0

1

1

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Section 2 CPU

Table 2.16 Instruction Formats for Single Data Transfers

Category Mnemonic 1514131211109 8

Single data
transfer

Category Mnemonic 76543210

Single data
transfer

Note: * System reserved code

MOVS.W @–As,Ds
MOVS.W @As,Ds
MOVS.W @As+,Ds
MOVS.W @As+Is,Ds

MOVS.W Ds,@-As
MOVS.W Ds,@As
MOVS.W Ds,@As+
MOVS.W Ds,@As+Is

MOVS.L @–As,Ds
MOVS.L @As,Ds
MOVS.L @As+,Ds
MOVS.L @As+Is,Ds

MOVS.L Ds,@-As
MOVS.L Ds,@As
MOVS.L Ds,@As+
MOVS.L Ds,@As+Is

MOVS.W @–As,Ds
MOVS.W @As,Ds
MOVS.W @As+,Ds
MOVS.W @As+Is,Ds

MOVS.W Ds,@-As
MOVS.W Ds,@As
MOVS.W Ds,@As+
MOVS.W Ds,@As+Is

MOVS.L @–As,Ds
MOVS.L @As,Ds
MOVS.L @As+,Ds
MOVS.L @As+Is,Ds

MOVS.L Ds,@-As
MOVS.L Ds,@As
MOVS.L Ds,@As+
MOVS.L Ds,@As+Is

111101 As

0: R4
1: R5
2: R2

3: R3

Ds 0: (*)

1: (*)
2: (*)
3: (*)

4: (*)
5: A1
6: (*)
7: A0

8: X0
9: X1
A: Y0
B: Y1

C: M0
D: A1G
E: M1
F: A0G

0

0

00

0

1

1

0

1

1

0

0

0

1

1

0

1

1

0

0

0

1

1

0

1

1

0

0

0

1

1

0

1

1

1

10

1

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Section 2 CPU

Parallel Processing Instructions: The parallel processing instructions allow for more efficient
execution of digital signal processing using the DSP unit. They are 32 bit length, allowing
simultaneously in parallel four processes, ALU operations, multiplications or 2 data transfers.

The parallel processing instructions are divided into A fields and B fields. The A field defines data
transfer instructions; the B field defines ALU operation instructions and multiplication
instructions. These instructions can be defined independently, the processes can be independent,
and furthermore, they can be executed simultaneously in parallel. Table 2.17 indicates the A field
parallel data transfer instructions, and table 2.18 indicates the B field ALU operation instructions
and multiplication instructions. A fields instruction is the same as double data transfers in table

2.15.

Table 2.17 A Field Parallel Data Transfer Instructions

Category Mnemonic 313029282726252423

X memory NOPX 1111100 0
data
transfers

Y memory NOPY 0
data
transfers

MOVX.W @Ax,Dx
MOVX.W @Ax+,Dx
MOVX.W @Ax+Ix,Dx

MOVX.W Da,@Ax
MOVX.W Da,@Ax+
MOVX.W Da,@Ax+Ix

MOVY.W @Ay,Dy
MOVY.W @Ay+,Dy
MOVY.W @Ay+Iy,Dy

MOVY.W Da,@Ay
MOVY.W Da,@Ay+
MOVY.W Da,@Ay+Iy

Ax Dx

Da

Ay

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Section 2 CPU

Category Mnemonic 22 21 20 19 18 17 16 15–0

X memory NOPX 0 0 0 B field
data

transfers

Y memory NOPY 00 00
data

transfers

Ax: 0 = R4, 1 = R5 Ay: 0 = R6, 1 = R7 Dx: 0 = X0, 1 = X1 Dy: 0 = Y0, 1 = Y1 Da: 0 = A0, 1 = A1

MOVX.W @Ax,Dx
MOVX.W @Ax+,Dx
MOVX.W @Ax+Ix,Dx

MOVX.W Da,@Ax
MOVX.W Da,@Ax+
MOVX.W Da,@Ax+Ix

MOVY.W @Ay,Dy
MOVY.W @Ay+,Dy
MOVY.W @Ay+Iy,Dy

MOVY.W Da,@Ay
MOVY.W Da,@Ay+
MOVY.W Da,@Ay+Iy

00

10

Dy 0 0

Da 1 0

1

1

0

1

1

1

1

0

1

1

1

1

0

1

1

1

1

0

1

1

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Table 2.18 B Field ALU Operation Instructions, Multiplication Instructions

Section 2 CPU

Category

Imm. shift

Six

operand

parallel

instruction

Three

operand

instructions

Mnemonic 14 13 12 10 9 8 7 6 5 4 3 2 1 015

PSHL #lmm, Dz

31–27 25–1626

10

PSHA #lmm, Dz

Reserved

PMULS Se, Sf, Dg

Reserved

PSUB Sx, Sy, Du

PMULS Se, Sf, Dg

PADD Sx, Sy, Du

PMULS Se, Sf, Dg

Reserved

PSUBC Sx, Sy, Dz
PADDC Sx, Sy, Dz

PCMP Sx, Sy

Reserved
Reserved
Reserved

PABS Sx, Dz
PRND Sx, Dz
PABS Sy, Dz
PRND Sy, Dz

Reserved

A field

000
000

001
010
010

11

0

–16 ≤ lmm ≤ +16

0

0

– 32 ≤ lmm ≤ +32

1

Dz000

1

0Se Sf Sx SyDgDu
1 0:X0

1:X1
2:Y0

0011

3:A1

1:Y1
2:X0

3:A1

0:X0
1:X1

2:A0
3:A1

0:Y0 0:M0

0:X00:Y0
1:Y01:Y1 1:M1

2:A02:M0 2:A0
3:A13:M1 3:A1

1011

010 0 000
10

01
11
0010
10
01
11
0001

10
01
11

0011
10
01
11

0

Dz

0: (*
1: (*1)

2: (*

1

)

1

)

3: (*1)

1

)

4: (*
5: A1

1

6: (*

)

7: A0
8: X0

9: X1
A: Y0

B: Y1
C: M0

1

D: (*

)

E: M1

1

F: (*

)

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Section 2 CPU

Category

Conditional

three

operand

instructions

Mnemonic 14 13 12 10 9 8 7 6 5 4 3 2 1 015

(if cc) PSHL Sx, Sy, Dz

(if cc) PSHA Sx, Sy, Dz
(if cc) PSUB Sx, Sy, Dz
(if cc) PADD Sx, Sy, Dz

Reserved
(if cc) PAND Sx, Sy, Dz
(if cc) PXOR Sx, Sy, Dz

(if cc) POR Sx, Sy, Dz

(if cc) PDEC Sx, Dz

(if cc) PINC Sx, Dz

(if cc) PDEC Sy, Dz

(if cc) PINC Sy, Dz

(if cc) PCLR Dz

(if cc) PDMSB Sx, Dz

Reserved

(if cc) PDMSB Sy, Dz

(if cc) PNEG Sx, Dz

(if cc) PCOPY Sx, Dz

(if cc) PNEG Sy, Dz

(if cc) PCOPY Sy, Dz

Reserved
(if cc) PSTS MACH, Dz

(if cc) PSTS MACL, Dz

(if cc) PLDS Dz, MACH

(if cc) PLDS Dz, MACL

2

Reserved

Reserved

*

31–27 25–1626

1 0 A field

1

11

11

1

if cc

01:

Uncon-

dition

10:DCT

11:DCF

00

if cc

00

0000
10

01
11

0010
10
01

11
0001

10
01
11
0011
10
01
11
0001
10
01
11

001
10

01
11

0 *

* : Don't care

Notes: 1. System reserved code

2. (if cc): DCT (DC bit true), DCF (DC bit false), or none (unconditional instruction)

2.5 Instruction Set

The instructions are divided into three groups: CPU instructions executed by the CPU core, DSP
data transfer instructions executed by the DSP unit, and DSP operation instructions. There are a
number of CPU instructions for supporting the DSP functions. The instruction set is explained
below in terms of each of the three groups.

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2.5.1 CPU Instruction Set

Table 2.19 lists the CPU instructions by classification.

Table 2.19 Classification of CPU Instructions

Section 2 CPU

Operation

Classification Types

Data transfer 5 MOV Data transfer, immediate data transfer, peripheral

Arithmetic 21 ADD Binary addition 33
operations

Code Function

module data transfer, structure data transfer

MOVA Effective address transfer

MOVT T bit transfer

SWAP Swap of upper and lower bytes

XTRCT Extraction of the middle of registers connected

ADDC Binary addition with carry

ADDV Binary addition with overflow

CMP/cond Comparison

DIV1 Division

DIV0S Initialization of signed division

DIV0U Initialization of unsigned division

DMULS Signed double-length multiplication

DMULU Unsigned double-length multiplication

DT Decrement and test

EXTS Sign extension

EXTU Zero extension

MAC Multiply/accumulate, double-length

multiply/accumulate operation

MUL Double-length multiply operation

MULS Signed multiplication

MULU Unsigned multiplication

NEG Negation

NEGC Negation with borrow

SUB Binary subtraction

SUBC Binary subtraction with borrow

SUBV Binary subtraction with underflow

No. of
Instructions

39

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Section 2 CPU

Operation

Classification Types

Logic 6 AND Logical AND 14
operations

Shift 10 ROTCL One-bit left rotation with T bit 14

Branch 9 BF Conditional branch, conditional branch with delay

Code Function

NOT Bit inversion

OR Logical OR

TAS Memory test and bit set

TST Logical AND and T bit set

XOR Exclusive OR

ROTCR One-bit right rotation with T bit

ROTL One-bit left rotation

ROTR One-bit right rotation

SHAL One-bit arithmetic left shift

SHAR One-bit arithmetic right shift

SHLL One-bit logical left shift

SHLLn n-bit logical left shift

SHLR One-bit logical right shift

SHLRn n-bit logical right shift

(Branch when T = 0)

BT Conditional branch, conditional branch with delay

(Branch when T = 1)

BRA Unconditional branch

BRAF Unconditional branch

BSR Branch to subroutine procedure

BSRF Branch to subroutine procedure

JMP Unconditional branch

JSR Branch to subroutine procedure

RTS Return from subroutine procedure

No. of
Instructions

11

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