Renesas SH7263, REJ06B0734-0100 User Manual

APPLICATION NOTE

SH7263/SH7203 Group

Data Transfer to On-chip Peripheral Modules with DMAC

Introduction

This application note provides an example of transferring data to on-chip peripheral modules with the direct memory access controller (DMAC) of the SH7263/SH7203.

Target Device

SH7263/SH7203

Contents

1. Introduction ....................................................................................................................................... 2

2. Description of Sample Application.................................................................................................... 3

3. Sample Program............................................................................................................................... 9

4. Documents for Reference............................................................................................................... 15

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SH7263/SH7203 Group

Data Transfer to On-chip Peripheral Modules with DMAC

1. Introduction

1.1 Specification

• DMAC channel 1 is used to transfer data from external memory to the transmit FIFO data register (SCFTDR) in the

serial communication interface with FIFO (SCIF channel 0) in order to transmit character string data.

• SCIF transmit FIFO data empty transfer requests (on-chip peripheral module request) are used to request DMA

transfer.

1.2 Modules Used

• Direct memory access controller (DMAC channel 1)

• Serial communication interface with FIFO (SCIF channel 0)

1.3 Applicable Conditions

• Microcontroller: SH7263/SH7203

• Operating Frequency: Internal clock 200 MHz

Bus clock 66.67 MHz Peripheral clock 33.33 MHz

• C Compiler: SuperH RISC engine family C/C++ compiler package Ver.9.01, from Renesas

Technology

• Compile Option: -cpu = sh2afpu -fpu = single -include = "$(WORKSPDIR)\inc"

-object = "$(CONFIGDIR)\$(FILELEAF).obj" -debug -gbr = auto -chgincpath

-errorpath -global_volatile = 0 -opt_range = all -infinite_loop = 0 -del_vacant_loop = 0

-struct_alloc = 1 -nologo

1.4 Related Application Notes

• The operation of the reference program for this document was confirmed with the setting conditions described in

the application note: SH7263/SH7203 Initialization Example. Please refer to the application note in combination with this one.

• Details on SCIF UART transmission are described in the application: SH7263/SH7203 Example Settings for UART

Transmission by the SCIF.

Please refer to the above application notes in combination with this one.

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Data Transfer to On-chip Peripheral Modules with DMAC

2. Description of Sample Application

In this sample application, the DMAC and on-chip peripheral module requests are used to transfer data from external memory to the SCIF.

2.1 Operational Overview of Modules Used

When a DMA transfer request is made, the DMAC starts to transfer data in accordance with the priority order of channels, and continues the transfer operation until the transfer end condition is met. Transfer requests for the DMAC are of three kinds: auto requests, external requests, and on-chip peripheral module requests. The bus mode is selectable as burst mode or cycle-stealing mode.

An overview of the DMAC is given in table 1. Also, a block diagram of the DMAC is shown in figure 1.

Table 1 Overview of DMAC

Item Description

Number of channels

Address space 4 Gbytes Length of transfer data Byte, word (2 bytes), longword (4 bytes), and 16 bytes (longword × 4) Maximum transfer

count Address mode Single address mode and dual address mode Transfer request Auto request, external request, and on-chip peripheral module request

Bus mode Cycle-stealing mode and burst mode Priority level Channel priority fixed mode and round-robin mode Interrupt request

External request detection

Transfer request acknowledge signal/transfer end signal

Note: For details on the DMAC, refer to the section on the direct memory access controller in the

SH7263/SH7203 Group Hardware Manual.

8 (CH0 to CH7) Only 4 (CH0 to CH3) can receive external requests.

16,777,216 (24 bits) transfers

• SH7203/SH7263 (SCIF: 8 sources, I

sources, USB: 2 sources, FLCTL: 2 sources, RCAN-TL1: 2 sources, SSI: 4 sources, SSU: 4 sources)

• SH7263 (SRC: 2 sources, ROM-DEC: 1 sou rce, SDHI: 2 sources)

An interrupt request to the CPU is made when half or all of a transfer process is completed.

DREQ input low/high level detection, rising/falling edge detection

Active levels for DACK and TEND can be set independently

C3: 8 sources, ADC: 1 source, MTU2: 5 sources, CMT: 2

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On-chip memory

On-chip

peripheral

module

SH7263/SH7203 Group

Data Transfer to On-chip Peripheral Modules with DMAC

DMAC module

RDMATCR_n

Iteration

control

DMATCR_n

RSAR_n

SAR_n

DMA transfer acknowledge signal

Interrupt controller

External ROM

External RAM

External device

(memory mapped)

External device

(with acknowledge)

DREQ0 to DREQ3

DACK0 to DACK3, TEND0, TEND1

DMA transfer

request signal

Internal bus

Peripheral bus

Bus state controller

HEIn

DEIn

Start-up

control

Request

priority control

Bus

interface

RDAR_n

DAR_n

CHCR_n

DMAOR

DMARS0 to DMARS3

[Legend]

RDMATCR: DMA reload transfer count register CHCR: DMA channel control register DMATCR: DMA transfer count register DMAOR: DMA operation register RSAR: DMA reload source address register DMARS0 to DMARS3: DMA extension resource selectors 0 to 3 SAR: DMA source address register HEIn: DMA transfer half-end interrupt request to the CPU RDAR: DMA reload destination address register DEIn: DMA transfer end interrupt request to the CPU DAR: DMA destination address register n: 0, 1, 2, 3, 4, 5, 6, 7

Figure 1 Block Diagram of DMAC

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SH7263/SH7203 Group

Data Transfer to On-chip Peripheral Modules with DMAC

2.2 Procedure for Setting Used Modules

This section describes the procedure for making initial settings when the DMAC is to be used to transfer data from memory to on-chip peripheral modules. On-chip peripheral module requests are used for transfer requests. A flowchart of DMAC initialization is shown in figure 2. For details on registers, refer to the SH7263/SH7203 Group Hardware Manual.

• Enabling clock supply to the DMAC (STBCR2)

[1]

START

Set standby control register 2

(STBCR2)

Set DMA channel control register

(CHCRn)

Set DMA source address control

Set DMA reload source

address register (RSARn)

Set DMA destination address

Set DMA reload destination

address register (RDARn)

Set DMA transfer count register

(DMATCRn)

Set DMA reload transfer

count register (RDMATCRn)

Set DMA channel control register

(CHCRn)

Set DMA extension resource selector

registers (DMARS0 to DMARS3)

Set DMA operation register

(DMAORn)

Set DMA channel control register

(CHCRn)

END

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

[11]

[12]

Clear the MSTP8 (module stop 8) bit to 0 [Function] Clock supply to the DMAC

• Disabling DMA transfer (CHCRn)

[2]

Clear the DE (DMA enable) bit to 0 [Function] Disable DMA transfer

• Setting DMA transfer source address (SARn)

[3]

[Function] Specify DMA transfer source address

• Setting DMA transfer source reload address (RSARn)

[4]

[Function] Specify DMA transfer source address to be reloaded

• Setting DMA transfer destination address (DARn)

[5]

[Function] Specify DMA transfer destination address

• Setting DMA transfer destination reload address (RDARn)

[6]

[Function] Specify DMA transfer destination address to be reloaded

• Setting the DMA transfer count (DMATCRn)

[7]

[Function] Set the DMA transfer count

• Setting the DMA transfer reload count (RDMATCRn)

[8]

[Function] Set the DMA transfer count to be reloaded

• Setting the DMA transfer mode (CHCRn)

[9]

Set the TC (transfer count mode) bit [Function] "0": Transfer data once for each transfer request (When the SCIF or IIC3 is selected as the transfer

"1": Transfer data for the count specified in DMATCRn for

Set the RLDSAR (SAR reload function enable/disable) bit [Function] Enables/disables reload function to SAR and DMATCR Set the RLDDAR (DAR reload function enable/disable) bit

[Function] Enables/disables reload function to DAR and DMATCR Set the DM (destination address mode) bits [Function] Select whether the DMA transfer destination address is

Fix/increment/decrement the DMA transfer destination address Set the SM (source address mode) bits [Function] Select whether the DMA transfer source address is

Fix/increment/decrement the DMA transfer source address Set the RS (resource select) bits to B'1000. [Function] Select DMA extension resource selector (DMA transfer

Set the TB (transfer bus mode) bit [Function] Select a DMA transfer bus mode. Cycle-stealing mode/burst mode Note: When TC is set to 0, select cycle-stealing mode Set the TS (transfer size) bits [Function] Specify the DMA transfer size Set the IE (interrupt enable) bit [Function] Enable/disable interrupt requests

• Specifying settings for DMA transfer requests from on-chip peripheral

[10]

modules (DMARS0 to DMARS3) [Function] Select the DMA transfer request source SCIF, IIC3, A/D converter, MTU2, or CMT

• Setting the DMA operation register (DMAOR)

[11]

Read from the AE (address error flag) bit and then clear it to 0 [Function] Clear the address error flag Read from the NMIF (NMI flag) bit and then clear it to 0 [Function] Clear the NMI flag Set the DME (DMA master enable) bit to 1 [Function] Enable DMA transfer on all the channels

• Enablling DMA transfer (CHCRn)

[12]

Set the DE (DMA enable) bit to 1 [Function] Start DMA transfer

request source)

each transfer requests

incremented or decremented

request source)

Figure 2 Flowchart of Initializing DMAC

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SH7263/SH7203 Group

Data Transfer to On-chip Peripheral Modules with DMAC

2.3 Operation of Sample Program

In this sample program, SCIF transmit FIFO data empty transfer requests are made to activate DMAC channel 1, and to transfer data from external memory to the transmit FIFO data register (SCFTDR) on SCIF channel 0. The data written to SCFTDR on SCIF channel 0 are transmitted in UART mode. An operation timing of the sample program is shown in figure 3.

DMA transfer using SCIF transmit FIFO data empty transfer requests (Timing of requesting data transfer from external memory to the SCIF transmit FIFO data register: a transfer request is made when the number of data in transmit FIFO becomes 0)

DMAC1

Bus

mastership

CPU

Internal bus

External bus

DMA transfer request

(When the DMA master

enable bit is 1)

DMA transfer count

Transfer end flag (TE)

One data

transfer

Read Read Read Read

Write Write Write Write

Write to SCIF transmit FIFO data register (SCFTDR)

Write Write Write Write

Read Read Read Read

SCIF transmit FIFO data empty transfer request (on-chip peripheral request)

H'28H'29

One data

transfer

Internal signal Internal signal Internal signal

One data

transfer

One data

transfer

H'27 H'00

[Legend]

: DMA request acknowledge

Figure 3 Operation Timing of Sample Application

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Renesas SH7263, REJ06B0734-0100 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1. Introduction

1.1 Specification

1.2 Modules Used

1.3 Applicable Conditions

1.4 Related Application Notes

2. Description of Sample Application

2.1 Operational Overview of Modules Used

2.2 Procedure for Setting Used Modules

2.3 Operation of Sample Program