REJ11J0002-0100Z
A
32
SH7206 CPU Board
M3
-HS60
User's Manual
Renesas32-Bit RISC Microcomputers
SuperHTM RISC Engine Family/SH7200 Series/SH7206 Group
Rev. 1.00
Issued:June 1,2005
f
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r
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prevent device malfunction.
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Revision History SH7206 CPU Board M3A-HS60User's Manual
Rev. Date of Issue Content of Revision
Page Points
1.00 June 1.2005 - First edition issued.
Table of Contents
Chapter1 Overview..............................................................................................................................1-1
1.1 Overview ....................................................................................................................................................................1-2
1.2 Configuration.............................................................................................................................................................. 1-2
1.3 External Specifications............................................................................................................................................... 1-3
1.4 External View .............................................................................................................................................................1-4
1.5 M3A-HS60 Block Diagram.......................................................................................................................................... 1-5
1.6 M3A-HS60 Board Overview .......................................................................................................................................1-6
1.7 M3A-HS60 Memory Mapping.....................................................................................................................................1-8
1.8 Absolute Maximum Ratings........................................................................................................................................ 1-9
1.9 Recommended Operating Conditions ........................................................................................................................ 1-9
Chapter2 Functional Overview ............................................................................................................2-1
2.1 Functional Overview................................................................................................................................................... 2-2
2.2 CPU............................................................................................................................................................................ 2-3
2.2.1 SH7206.............................................................................................................................................................2-3
2.3 Memory ...................................................................................................................................................................... 2-4
2.3.1 SH7206's Internal RAM.....................................................................................................................................2-4
2.3.2 Flash Memory M5M29KT331AVP (included as standard equipment)...............................................................2-4
2.3.3 External SDRAM............................................................................................................................................... 2-6
2.4 Serial Port Interface.................................................................................................................................................... 2-9
2.5 I/O Ports...................................................................................................................................................................2-10
2.6 Power Supply Circuit................................................................................................................................................ 2-12
2.7 Clock Module............................................................................................................................................................ 2-13
2.8 Reset Module........................................................................................................................................................... 2-14
2.9 Interrupt Switches..................................................................................................................................................... 2-14
2.10 E10A-USB Interface...............................................................................................................................................2-15
Chapter3 Operational Specifications...................................................................................................3-1
3.1 M3A-HS60 Connectors Outline.................................................................................................................................. 3-2
3.1.1 H-UDI Connector (J1) ....................................................................................................................................... 3-3
3.1.2 Serial Port Connector (J2)................................................................................................................................. 3-4
3.1.3 External Power Supply Connectors(J3 and J5)................................................................................................. 3-5
3.1.4 Power Supply Connector (J4) ........................................................................................................................... 3-6
3.1.5 User I/O Connectors (J6-J8) ............................................................................................................................. 3-7
3.1.6 Extension Connectors (J9-J13)......................................................................................................................... 3-9
3.2 Outline of Switches and LEDs.................................................................................................................................. 3-13
3.2.1 Power Supply Select Jumpers (JP1 and JP2)................................................................................................. 3-14
3.2.2 Switch and LED Functions.............................................................................................................................. 3-15
3.3 Outline Dimensions of M3A-HS60............................................................................................................................ 3-17
Appendix .............................................................................................................................................A-1
M3A-HS60 Schematics
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Chapter1Overview
Chapter1
Overview
1-1
Overview
1
1.1 Overview
1.1 Overview
The M3A-HS60 is the CPU board designed for users to evaluate the function and perform ance of original microcomputers of
Renesas Technology the SH7206 series. With the board, you can develop and evaluate the application software for the
SH7206 series. The SH7206's data bus, address bus, and pins of various internal periph eral circuit func tion are conne cted to
the extension bus connector of the M3A-HS60. Thus, you can evaluate the timing relationshi ps with peripheral devices by
using measurement instruments. You can also develop extension boards depend ing on developm ent purpos es.
Furthermore, the E10A-USB, the on-chip emulator made by Renesas Technology, can be connected to the M3A-HS60.
1.2 Configuration
Figure1.2.1 shows an example system configuration using M3A-HS60.
SH7206 CPU Board
M3A-HS60
Power supply
(5V/1.5A or more)
*1
Application
Board
* Created according to
the intended application
High-performance
Embeded Workshop(HEW)
SuperH RISC engine
C/C++ compiler package
*1: Option Items:
It is necessary to prepare separately for software development.
SH7206
Extension
connector
HEW
*1
*1
Figure1.2.1 Example System Configuration of M3A-HS60
debugger
Host
Computer
Serial port connector
USB
*1
H-UDI/AUD
E10A-USB
*1
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1.3 External Specifications
Table1.3.1 lists external specifications of M3A-HS60
Table1.3.1 External Specifications of M3A-HS60
No. Item Content
SH7206（R5S72060）
1 CPU
2 Memory
3 Connectors
4 LED
z Input(XIN)clock: 16.67MHz
z Bus clock: 66.67MHz,max
z CPU clock: 200MHz,max
Following items of memory are included.
zSDRAM: 32 Mbytes, max.
Following memory selectable by a DIP switch.
• When 16-bit bus width is selected
EDS1216AATA-75E x 1: 16 Mbytes
• When 32-bit bus width is selected
EDS1216AATA-75E x 2: 32 Mbytes
z Flash memory
• M5M29KT331AVP x 1: 4Mbytes
• Data bus width fixed to 16 bits
z Extension connector (bus, I/O, VCC, GND: 100 pins)
z User I/O connector (SH7206's MTU2 and A/D function pins: 32 pins)
z Serial port connector (D-sub 9 pins)
z H-UDI connector (36 pins)
z POWER LED (1 pc.)
z User LED（7 pcs.）
Overview
1.3 External Specifications
5 Switches
6 Package Dimensions
z Reset switch (1 pc.)
z MRES switch (1 pc.)
z NMI switch (1 pc.)
z User DIP switch (1 pc., 4 poles)
z System setup DIP switch (1 pc., 5 poles)
z Dimensions: 100 mm x 100 mm
z Mounting form: 4-layer, double-side mounted
z Board configuration: 1 board
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1.4 External View
Figure1.4.1 shows the external view of M3A-HS60.
Overview
1.4 External View
Figure1.4.1 External View of M3A-HS60
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1.5 M3A-HS60 Block Diagram
Figure1.5.1 shows the system block diagram of M3A-HS60.
Overview
1.5 M3A-HS60 Block Diagram
Flash memory
4MB
16 16 or 32
SH7206 CPU Board
M3A-HS60
H-UDI
Extension connector
Figure1.5.1 System Block Diagram of M3A-HS60
Serial port
connector
SH7206
200MHz
16 or 32
External:66.67MHz
Enables to connect extension boards, or
enables to monitor all of bus and peripheral
I/O signals.
User I/O Connector
SDRAM
16MB x 2
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or
J4
1.6 M3A-HS60 Board Overview
Figure1.6.1 shows the M3A-HS60 board overview.
SW1
Power
Switch
Top view of the
Component side
LED6-8
User LED
U5
JP1,JP2
Power Supply
Select Jumper
SDRAM
(16MB)
Power
Supply
Connector
Overview
1.6 M3A-HS60 Board Overview
LED1
Power LED
SW4
System setup
DIP switch
J1
H-UDI Connect
(36-pin)
SW2
Reset
Switch
Top view of the
Solder side
U10
3.3V Power
Regulator
U12
1.25V Power
Regulator
LED2-5
User
LED
J6 J7
U3
SW5
NMI
Switch
U8
SDRAM
(16MB)
Flash
Memory
SW3
User
DIP Switch
U2
Clock
Buffer
(not mounted)
J12
J13
U1
SH7206
X1
Oscillator
16.67MHz
J3 J5
U9
RS-232C
Driver
U4
SW6
MRES
Switch
J2
Serial Port
Connector
J6
U7
Address Shift
Buffer
J11
J9
U6
Logic IC(LVC14)
U11
Reset IC
J10
:Extension connector(not mounted)
Figure1.6.1 M3A-HS60 Board Overview
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Table1.6.1 lists main components mounted in M3A-HS60.
Table1.6.1 Main Components Mounted in M3A-HS60
Symbol Component name
U1 CPU SH7206 (by Renesas)
U2 Clock Buffer Not mounted CY2305SC-1 (by Cypress)
U3 Flash Memory M5M29KT331AVP
(by Renesas)
U4,U7 Address Shift Buffer
U5,U8 SDRAM EDS1216AATA-75
U6 Logic IC
U9 RS-232C Driver
U10 3.3V Power Regulator
U11 Reset IC M51957BFP (by Renesas)
U12 1.25V Power Regulator
X1 16.67MHz Oscillator 16.67MHz
X2 Ceramic Resonators Not mounted, 16.67MHz CSTCE-G16M67
J1 H-UDI Connector
J2 Serial port Connector
J3,J5 External Power Supply Connector Not mounted A2-2PA-2.54DSA
J4 Power Supply Connector
J6 Extension connector Not mounted,
26pin MIL Standard Connector
J7, J8 Extension connector Not mounted,
3pin MIL Standard Connector
J9, J11, J13 Extension connector Not mounted,
20pin MIL Standard Connector
J10, J12 Extension connector Not mounted,
40pin MIL Standard Connector
LED1 Power LED Red
LED2-8 User LED Green
SW1 Power Switch
SW2 Reset Switch
SW5 NMI Switch
SW6 MRES Switch
SW3 User DIP Switch
SW4 System setup DIP Switch
Note
1.6 M3A-HS60 Board Overview
Recommended parts’
number for not mounted
components (Makers)
(by Murata)
(by Hirose)
XG4C-2634 Right angle
A2-3PA-2.54DSA
XG4C-2031
XG4C-4031
Overview
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1.7 M3A-HS60 Memory Mapping
Figure1.7.1 shows the memory mapping example of SH7206 in the M3A-HS60.
Logical address Logical space of theSH7206 Memory Mapping of theM3A-HS60
H'0000 0000
H'003F FFFF
H'0400 0000
H'0800 0000
H'0C00 0000
H'0CFF FFFF
H'0DFF FFFF
CS0 space:64MB
CS1 space:64MB User area
CS2 space:64MB User area
CS3 space:64MB
Flash Memory(4MB)
16-bit bus
User area
SDRAM(32MB)
32-bit bus
Overview
1.7 M3A-HS60 Memory Mapping
SDRAM(16MB)
16-bit bus
User area
H'1000 0000
H'1400 0000
H'1800 0000
H'1C00 0000
H'2000 0000
H'4000 0000
H'8000 0000
H'FFF8 0000
H'FFFA 0000
H'FFFC 0000
H'FFFF FFFF
Note: There is the cacheable area from H’0000 0000~H’1FFF FFFF.
CS4 space:64MB User area
CS5 space:64MB User area
CS6 space:64MB
CS7 space:64MB
CS0-CS7 spaces
(non-cacheable area)
CS8 space:1GB User area
Internal RAM(128KB) Internal RAM(128KB)
Internal RAM, Reserved Internal RAM, Reserved
Internal peripheral module Internal peripheral module
User area
Reserved area
(Disabled)
Reserved area
(Disabled)
Reserved area
(Disabled)
CS0-CS7 spaces
(non-cacheable area)
Reserved area
(Disabled)
Figure1.7.1 Memory Mapping Example of SH7206
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1.8 Absolute Maximum Ratings
Table1.8.1 lists the absolute maximum ratings of M3A-HS60.
Table1.8.1 Absolute Maximum Ratings of M3A-HS60
Symbol Parameter Rated Value Remarks
VCC 5V System Power Supply Voltage -0.3V to 6.0V Relative to VSS
3VCC 3.3V System Power Supply Voltage -0.3V to 4.6V Relative to VSS
1.2VCC 1.25V System Power Supply Voltage -0.3V to 1.7V Relative to VSS
Topr Operating Ambient Temperature -5°C to 55°C No dewdrops allowed.
Use in corrosive gas environment prohibited.
Tstr Storage Ambient Temperature -10°C to 60°C No dewdrops allowed.
Use in corrosive gas environment prohibited.
Note: The ambient temperature refers to the air temperature in the closest place from the board.
1.9 Recommended Operating Conditions
Overview
1.8 Absolute Maximum Ratings
Table1.9.1 lists the recommended operating conditions of the M3A-HS60.
Table1.9.1 Recommended Operating Conditions of M3A-HS60
Symbol Parameter Rated Value Remarks
VCC 5V System Power Supply Voltage 4.75V to 5.25V Relative to VSS
3VCC 3.3V System Power Supply Voltage 3.0V to 3.6V Relative to VSS
(Normally supplied from regulator)
1.2VCC 1.25V System Power Supply Voltage 1.15V to 1.35V Relative to VSS
(Normally supplied from regulator)
– Maximum Power Consumption in the Board Within 1A
Topr Operating Ambient Temperature 5°C to 50°C No dewdrops allowed.
Use in corrosive gas environment prohibited.
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Overview
1.8 Absolute Maximum Ratings
This is a blank page
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Chapter2Functional Overview
Chapter2
Functional Overview
2-1
2
2.1 Functional Overview
Table2.1.1 lists the functional modules of M3A-HS60.
Table2.1.1 Functional Modules of M3A-HS60
Sections Function Content
Functional Overview
2.1 Functional Overview
2.2 CPU
2.3 Memory
2.4 Serial port interface
2.5 I/O ports
2.6 Power Supply Circuit
2.7 Clock Module
2.8 Reset Module
2.9
2.10 E10A-USB Interface
–
Interrupt switches
Operational specifications
SH7206
zInput(XIN)clock : 16.67MHz
zBus clock : 66.67MHz,max
zCPU clock : 200MHz,max
Following items of memory are included
z SDRAM: 32 Mbytes, max
By switching a DIP switch, the following memories can be selected.
• When 16-bit bus width is selected
EDS1216AATA-75E x 1: 16 Mbytes
• When 32-bit bus width is selected
EDS1216AATA-75E x 2: 32 Mbytes
z Flash memory
• M5M29KT331AVP x 1: 4 Mbytes
• Data bus width fixed to 16 bits
Connects SCIF0 of the SH7206 to the Serial port connector.
Connects to the I/O ports of the SH7206
Controls the system power supply of the M3A-HS60
Controls the clock
Controls device reset mounted on the M3A-HS60
Connects to NMI and MRES pins
SH7206 H-UDI/AUD interface
Connectors, switches and LEDs
z SH7206 extension connector
z Switches and LEDs
z H-UDI connector
Detailed in Chapter 3.
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Functional Overview
SH7206
A
er
er
2
2.2 CPU
2.2.1 SH7206
The M3A-HS60 contains SH7206, the 32-bit RISC microcomputer, which operates with a maximum 200MHz of CPU
clock frequency. The SH7206 includes 128-Kbyte RAM, 8-Kbyte instruction cache and 8-Kbyte data cache, and it can
deal with a wide range of applications from data processing to equipment control.
The M3A-HS60 can be operated with a maximum 200MHz of CPU clock frequency (external bus 66.67MHz, max.)
using a 16.67MHz input clock.
Figure2.2.1 shows the block diagram of SH7206 in the M3A-HS60.
2.2 CPU
Clock
3.3V
Mode
System
Control
ddress bus
Data bus
Bus control
GND
GND
EXTAL
XTAL
CKIO
CS0 space
MD2
Fixed 16-bit bus
MD0
MD_CLK2
MD_CLK0
RES#
MRES#/TIOC4B/PE13
WDTOVF#
BREQ#/TEND0/PINT2/PA18
BACK#/TEND1/PINT3/PA19
A25/DREQ0/IRQ0/SCK0/PA2
A24/RXD1/PA3
23
A23-A1
A0/PC0
D31/TIOC3AS/ADTRG#/PD31
D30/TIOC3CS/IRQOUT#PD30
D29/CS3#/TIOC3BS/PD29
D28/CS2#/TIOC3DS/PD28
D27/DACK1/TIOCS4AS/PD27
D26/DACK0/TIOC4BS/PD26
D25/DREQ1/TIOC4CS/PD25
D24/DREQ0/TIOC4DS/PD24
D23/IRQ7/PD23
D22/IRQ6/TIC5US/PD22
D21/IRQ5/TIC5VS/PD21
D20/IRQ4/TIC5WS/PD20
D19/IRQ3/POE7#/PD19
D18/IRQ2/POE6#/PD18
D17/IRQ1/POE5#/PD17
D16/IRQ0/POE4#/PD16
16
D15-0
CS0#
CS1#/POE5#/PA11
CS2#/TCLKA/PA6
CS3#/TCLKB/PA7
CS4#/RASU#/PINT4/PA20
CS5#/CE1A#/CASU#/PINT5/TIC5U/PA21
CS8#/PE16
CE2A#/DREQ3/PINT6/PA24
CE2B#/DACK3/PINT7/POE8#/PA25
Mode 2
WE1#/WE#/DQMLU#/POE7#/PA13
WE2#/ICIORD#/DQMUL#/TIC5V/PA22
WE3#/ICIOWR#/AH#/DQMUU#/TIC5W/PA23
FRAME#/CKE/TCLKD/IRQ3/PA9
BS#/RXD2/TIOC2B/UBCTRG/PE7
DACK1//CKE/TIOC4D/IRQOUT#/PE15
WE3#/ICIOWR#/AH#/DACK0/TIOC4C/PE14
WAIT#/DACK2/PA17
WE0#/DQMLL/#POE6/PA12
RD_WR#/IRQ2/TCLKC/PA8
RASL#IRQ2/#POE2/PB4
CASL#/IRQ3/POE3#PB5
SCK2/TIOC3A/PE8
IRQ1/POE1/SDA/PB3
IRQ0/POE0#/SCL/PB2
TXD2/TIOC3C/PE10
TEND0/TIOC0B/PE1
DREQ1/TIOC0C/PE2
SCK3/TIOC3B/RTS3#/PE9
TXD3/TIOC4A/PE12
RXD3/TIOC3D/CTS3#
AUDATA0-3
ASEBRKAK#/ASEBRK#
AUDSYNC#
ASEMD#
ASEBCK
ASEBRK#
AN0-AN5/PF0-PF5
AN6/DA0/PF6
AN7/DA1/PF7
RD#
NMI#
TCK
TMS
TDI
TDO
TRST#
AUDCK
TXD0
RXD0
Bus control
IRQ/SCI/IIC
DMAC/GPIO
MTU2
4
6
NMI
E10A-USB
Interface
Serial port
Interface
A/D Convert
D/A Convert
Figure2.2.1 Block Diagram of SH7206
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Functional Overview
M5M29KT331AVP
2
2.3 Memory
2.3 Memory
The M3A-HS60 includes the internal RAM of the SH7206 (128 Kbytes), external Flash memory, and external SDRAM.
These memory chips are detailed below.
2.3.1 SH7206's Internal RAM
The SH7206 contains an internal 128-Kbyte RAM.
2.3.2 Flash Memory M5M29KT331AVP (included as standard equipment)
The M3A-HS60 includes the Flash memory shown in Table2.3.1 as standard equipment. The memory can be used as
the storage in which to save the user program. The Flash memory to boot is fixed to 16-bit mode of external bus and
operates with a single 3.3 V power supply voltage. The write-protect of Flash memory can be enabled or disabled by
using a DIP switch.
Figure2.3.1 shows a block diagram of Flash memory.
Table2.3.2 lists bus state controller settings (write/read) for operation with the SH7206 bus clock at 66.67MHz.
Table2.3.1 Outline of the Flash Memory
Part Number Bus Size Capacity Access Time
M5M29KT331AVP 16-bit mode 4 Mbytes(16 bits × 2 Mword × 1pc.） 70ns
SH7206
A21
A20-A1
D15-D0
RD#
WE0#
CS0#
DIP SW
RES#
3.3V
20
16
A20
A19-A0
DQ15-DQ0
3.3V
NC
BYTE#
OE#
WE#
CE#
RP#
RY/BY#
WP#
(2 M Word x16 bit)
Figure2.3.1 Block Diagram of Flash Memory
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2.3.2 Flash Memory M5M29KT331AVP (included as standard equipment)
Table2.3.2 Examples for Bus State Controller Settings (Flash Memory Write/Read)
User Area Applicable Device Bus State Controller Settings
CS0 M5M29KT331AVP CS0 Space Bus Control Register : CS0BCR
Initial value : H'36DB 0600(when MD2= H and MD0=L）
Recommended set value : H'1000 0400
• Specify idle state in write to read and write to write intervals
IWW[2:0] = B'001: 1 idle cycles inserted
• Specify data bus
BSZ[1:0] = B'10 : 16-bit bus width
CS0 Space Wait Control Register (CS0WCR)
Initial value: H'0000 0500
Recommended set value : H'0000 0AC1
• Address, CS0# assert -> RD#, WEn# assert delay cycle
SW[1:0] = B'01 : 1.5 cycles
• Specify access wait cycles
WR[3:0] = B'0110 : 5 cycles
• RD#, WEn# negate -> Address, CS0 negate delay cycle
HW[1:0] = B'01 : 1.5 cycles
<Write and Read Timing>
Write1 Write2 Read1
T1T2Tw4T1 Tw1 Tw2 Tw1 Tw2 T2 T1 Tw1 Tw2 Tw3 T2Tf Tf Taw1Taw1Th Th Th TfTw4Tw3 Tw3 Tw4 Tw5Tw5 Tw5
CKIO
A21-A1
CS0#
RD#
WE0#
D15-D0
tWDD1
tWCtWC
tWPtCS tWP
tAS
tDS
DATA DATA DATA
tCH
tDH
tAD1tAD1
tCSD1tCSD1
tWPH
tWPH
tWDH1
tAD1
tCSD1
tWDD1
tDS
tAD1
tCSD1
tWED1tWED1tWED1tWED1
tOEH
tWPtAH
tCHtWP
tAHtAS
tWDH1
Figure2.3.2 Flash Memory Read and Write Access Timing
tCSD1
ta(AD)
Functional Overview
tRCtRC
tRSDtRSD
ta(OE)
tRDS1tDH
tRDH1
tDF(OE)ta(CE1)
tAD1tAD1
tCSD
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Functional Overview
6
3.3V
2
2.3.3 External SDRAM
The M3A-HS60 includes two pcs. of 16-Mbyte SDRAM (for an external SDRAM) as standard equipment.
The SH7206's internal bus state controller can be used to control the SDRAM.
Note that the SDRAM can be switched between 32-bit bus access and 16-bit bus access. (For 16-bit bus access, only
one pc. of 16-Mbyte SDRAM can be used.)
Table2.3.3 lists SDRAM specifications used in M3A-HS60. Figure2.3.3 shows a block diagram of SDRAM.
Table2.3.3 SDRAM Specifications Used in M3A-HS60
Specification Content
Part number EDS1216AATA-75E
Configuration 16 Mbytes (16-bit bus width) x 2pcs.
Capacity 32 Mbytes
Access time 5.4ns
CAS latency 2 (At 66MHz bus clock)
Refresh interval 4,096 refresh cycles every 64ms
Row address A11- A0
Column address A8 - A0
Number of banks 4-bank operation controlled by BA0 and BA1
2.3.3 External SDRAM
SH7206
A15-1
CS3#
DQMUU
DQMUL
CKIO
CKE
RD/WR#
RASL#
CASL#
SDRAM
bus size setting
SDRAM_SZ
14
SDRAM_SZ=Low:16-bit access using SDRAMx1
SDRAM_SZ=High:32-bit access using SDRAMx2
32-bit Access
A[13:2], A15-14
1OE#
2OE#
16-bit Access
A[12:1], A14-13
1OE#
2OE#
3.3V
14
MA11-0,BA1-0
CS#
DQMU
DQML
CLK
CKE
WE#
RAS#
CAS#
14
MA11-0,BA1-0
CS#
EDS1216AATA
(8Mx16 bits)
DQ15-DQ0
EDS1216AATA
(8Mx16 bits)
DQ15-DQ0
16
16
SH72060 D31-D1
SH72060 D15-D0
DQMLU
DQMLL
DQMU
DQML
CLK
CKE
WE#
RAS#
CAS#
Figure2.3.3 Block Diagram of External SDRAM
Rev.1.00 June 1,2005 2-6
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2
Table2.3.4 lists bus state controller settings for operation with the SH7206 Bus clock at 66.67MHz.
Table2.3.4 Examples for Bus State Controller Settings (SDRAM Read/ Write)
User Area Application Device Bus State Controller Settings
CS3 EDS1216AATA-75E
CS3 Space Bus Control Register (CS3BCR)
Initial value: H'36DB 0600
Recommended set value: H'0000 4400 (for 16-bit bus) or H'0000 4600
(for 32-bit bus)
• Specify memory
TYPE[2:0] B'100; SDRAM
• Specify data bus
BSZ[1:0] = B'10; 16-bit bus width
BSZ[1:0] = B'11; 32-bit bus width
CS3 Space Wait Control Register (CS3WCR)
Initial value: H'0000 0500, Recommended set value: H'0000 2892
• Precharge completion wait cycles
WTRP[1:0] = B'01; 1 cycles
•
Wait cycles between ACTV command -> READ(A)/WRITE(A)command
WTRCD[1:0] =
• Area 3 CAS latency
A3CL[1:0] = B'01; 2 cycles
• Precharge start wait cycles
TRWL[1:0] = B'10; 2 cycles
• Idle cycles between REF command/self-refresh deactivation
-> ACTV/REF /MRS command
WTRC[1:0] = B'10; 5 cycles
SDRAM Control Register (SDCR)
Initial value: H'0000 0000, Recommended set value: H'0000 0809
• Refresh control
RFSH = B'1; Refresh enabled
• Refresh control
RMODE = B'0; Auto refresh
• Bank active mode
BACTV = 0; Auto precharge mode
• Area 3 row address bits
A3ROW[1:0] = B'01; 12 bits
• Area 3 column address bits
A3COL[1:0] = B'01; 9 bits
Refresh Timer Control/Status Register (RTCSR)
Initial value: H'0000 0000, Recommended set value: H'A55A 0010
• Clock select
CKS[2:0] = B'010; B-φ/16
• Refresh times
RRC[2:0] = B'000; 1 time
Refresh Time Constant Register (RTCOR)
Initial value: H'0000 0000, Recommended set value: H'A55A 0041
* The following shows refresh request intervals in cases when clock
select is set to B- φ/16.
1 cycle: 240ns (66MHz/16 = 4.125MHz)
Refresh request intervals for the SDRAM: every 15.625µs
15.625µs/240ns = 64 (0x41) cycles per refresh
AC Characteristics Switching Register (ACSWR)
Initial value:
• AC Characteristics Switch
ACOSW[3:0] = B'1001;
B'10; 2 cycles
H'0000 0000,
Recommended set value:
Switches characteristics and extends the
delay time
Functional Overview
2.3.3 External SDRAM
H'0000 0009
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A
CKIO
CKE
CS3#
RASL#
CASL#
RD/WR#
DQMUU-LL
A11-A2(A9-A0)
A12(A10/AP)
15,A14(BA1,0)
D0-31
Functional Overview
2.3.3 External SDRAM
SDRAM SINGLE READ SDRAM SINGLE WRITE
tRAS tRP
tRAS
ACT READA ACT WRITEA ACT
Tr Trw1 Tc1 Tcw Td1 Tde Tr Trw1 Tc1 Trw11 Trw12 TrTap TapTrw2 Trw2
tSI
tRASD1
tHI
tSI
tRASD1
tHI
tSI
tCASD1
tRC
tRC
tCASD1
tLZ
tAC
Data
tRP tRAS
tHI
tRDS2
tOH
tOHZ
tSI
tRASD1
tRCD
tRASD1
Figure2.3.4 Typical SDRAM Single Read/Write Timing
tRC
tRC
tHI
tCASD1
tRWD1
tAD1tAD1tAD1tAD1tAD1tAD1
tAD1tAD1tAD1tAD1tAD1tAD1
tAD1tAD1tAD1tAD1tAD1tAD1
tHI
tSItRDH2
tWDD2
tWDH2
tDPL
tDPLtRCD
tCSD1tCSD1tCSD1tCSD1
tCASD1
tRWD1
tDQMD1tDQMD1tDQMD1tDQMD1
tDAL
tDAL
tRP
tRPtRAS
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Functional Overview
Serial port
2
2.4 Serial Port Interface
2.4 Serial Port Interface
The SH7206 included in the M3A-HS60 contains a UART module. As for the M3A-HS60, SCIF channel 0 is connected
to serial port connector.
Figure2.4.1 shows a block diagram of serial port interface in the M3A-HS60.
1
2
3
4
5
6
7
8
9
connector
DCD#
RxD
TxD
DTR#
GND
DSR#
RTS#
CTS#
RI#
RS-232C
SH7206
RXD0
TXD0
Figure2.4.1 Block Diagram of Serial Port Interface
driver
NC
GND
NC
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Functional Overview
3.3V
2
2.5 I/O Ports
2.5 I/O Ports
As for the M3A-HS60, the SH7206's I/O ports are connected to the extension bus connector of the M3A-HS60 board.
Some I/O ports are connected to DIP switches and LEDs of the M3A-HS60 board. Users are free to use these ports.
Figure2.5.1 shows a block diagram of SH7206 I/O ports.
Table2.5.1 shows the functions of SH7206 I/O ports.
LED8
GREEN
LED7
GREEN
LED6
GREEN
SW3-1
SW3-2
SW3-3
SW3-4
DIP Switch
LED5
GREEN
LED4
GREEN
LED3
GREEN
3.3V
LED2
GREEN
SH7206
PE1
PE2
PE8
PE10
PE11
PE14
PE15
PA18
PA19
PA24
PA25
Figure2.5.1 Block Diagram of SH7206 I/O Ports
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Functional Overview
2.5 I/O Ports
Table2.5.1 Functions of SH7206 I/O Ports
SH7206 Port Name Connection in the M3A-HS60
PA0-PA1
PA2
PA3,PA6,PA11,PA17,
PA20,PA21
PA4-PA5
PA7-PA9,PA13,PA22,PA23
PA12
PA13
PA18
PA19
PA24
PA25
PB2,PB3
PB4,PB5
PB9
PC0
PC1
PD8-PD15
PD16-PD31
PE1
PE2
PE7,PE9,PE12,PE13,PE16
PE8
PE10
PE1 1
PE14
PE15
PF0-7
Serial port connector.
Extension connector, SDRAM_SZ signal input.
Extension connector.
Flash memory and extension connector.
SDRAM and extension connector.
Flash memory, SDRAM and extension connector.
SDRAM and extension connector.
SW1-1 and extension connector.
SW1-2 and extension connector.
SW1-3 and extension connector.
SW1-4 and extension connector.
Extension connector.
SDRAM and extension connector.
Flash memory and extension connector.
Extension connector.
Flash memory, SDRAM and extension connector.
Flash memory, SDRAM and extension connector.
SDRAM (when 32-bit bus selected) and extension connector.
LED2 and extension connector.
LED3 and extension connector.
Extension connector.
LED4 and extension connector.
LED5 and extension connector.
LED6 and extension connector.
LED7 and extension connector.
LED8 and extension connector.
Extension connector.
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Functional Overview
Extension connector
3
Extension connector
5
2
2.6 Power Supply Circuit
2.6 Power Supply Circuit
The M3A-HS60 accepts a 5V power supply as its input, and generates 3.3V and 1.25V by using a regulator.
The regulator used here is an output voltage variable type, so that any desired voltage can be generated by changing
the resistance value.
Figure2.6.1 shows a block diagram of power supply circuit in the M3A-HS60.
Flash
memory
External
power supply J
1
3
5V
SW1
SDRAM
5V ->
3.3V
JP1
2
SH7206
2
JP2
5V ->
1.25V
Figure2.6.1 Block Diagram of Power Supply Circuit
1
External
power supply J
3
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Functional Overview
R14
r)
O
2
2.7 Clock Module
2.7 Clock Module
The clock module in the M3A-HS60 consists of the following two blocks:
• Output from a oscillator connected to EXTAL of the SH7206
• Ceramic resonator connected to EXTAL and XTAL
The M3A-HS60 has a 16.67MHz oscillator connected. Furthermore, the bus clock output from the SH7206 is connected
to the SDRAM via a damping resistor. To connect an extension board to the extension connector, we recommend
including a clock buffer that contains a PLL to ensure that the board will be supplied with a stable clock signal.
Figure2.7.1 shows a block diagram of clock module.
scillator
CLK
*1:To mount ceramic resonator, remove the resistor 18
*2:To mount a clock buffer, remove the resistor 14
R18
Not mounted
:Not mounted parts
R82
Ceramic
Resonator
SH7206
EXTAL
XTAL
*1
CSTCE-G16M67(Murata)
Figure2.7.1 Block Diagram of Clock Module
CKIO
Clock Buffer
Not mounted
*2
CY2305SC-1H(Cypress)
CLKIH(SDRAM upper bytes)
CLKIL(SDRAM lower bytes)
EXCLK(Extension connecto
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Functional Overview
R
R
or
H-UDI connector
3.3V
M
2
2.8 Reset Module
2.8 Reset Module
This module controls the reset signals connected to both the SH7206 and Flash memory mounted in the M3A-HS60.
Figure2.8.1 shows a block diagram of the reset module in M3A-HS60.
RES#
esetIC output delay time,td=0.34 x Cd(pF)µsec = 34ms
3.3V
Ra+Rb
)
esetIC output detection voltage,Vs = 1.25 x = 2.5V
3.3V
Rb
)
Flash memory
RP#
Extension connect
RESET#
Ra
10KW
Rb
10KW
*
Open-collector output
Reset IC
M51957BFP
Input
Delay capacitance
Output
Cd
*
0.1µF
Reset switch
SW 2
SH7206
RES#
Figure2.8.1 Block Diagram of Reset Module
2.9 Interrupt Switches
As for the M3A-HS60, both the SH7206's NMI interrupt pin and MRES pin have a push switch connected. MRES switch
can be used for controlling manual reset for SH7206. When manual reset is done, the internal condition of CPU will be
formatted, but each register of on-chip peripheral module.
Figure2.9.1 shows a block diagram of interrupt switches.
SH7206
SW 5
NMI switch
3.3V
SW 6
RES switch
NMI#
MRES#/PE13
Figure2.9.1 Block Diagram of Interrupt Switches
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3.3V
2.10 E10A-USB Interface
As for the M3A-HS60, a 36-pin H-UDI connector to connect it with the E10A-USB is mounted.
Figure2.10.1 shows a block diagram of the E10A-USB interface.
3.3V
H-UDI connector
(36-pin type)
10
12
14
16
18
20
22
24
26
28
30
32
34
36
2
GND
4
GND
6
GND
8
GND
GND
GND
GND
GND
GND
GND
(GND)
GND
GND
GND
ASEBRKAK#/ASEBRK#
GND
GND
GND
GND
AUDCK
AUDATA0
AUDATA1
AUDATA2
AUDATA3
AUDSYNC#
TRST#
UVCC
N.C.
N.C.
TCK
TMS
TDI
TDO
RES#
GND
N.C.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
Functional Overview
2.10 E10A-USB
SH7206
AUDCK
AUDATA0
AUDATA1
AUDATA2
AUDATA3
AUDSYNC#
TCK
TMS
TRST#
TDI
TDO
ASEBRKAK#/ASEBRK#
ASEMD#
RES#
Reset signal
Figure2.10.1 Block Diagram of the E10A-USB Interface
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Functional Overview
2.10 E10A-USB
This is a blank page
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Chapter3 Operational Specifications
Chapter3
Operational Specifications
3-1
3
3.1 M3A-HS60 Connectors Outline
Figure3.1.1 shows the M3A-HS60 connectors assignments.
<Top view of the component side>
Operational Specifications
3.1 M3A-HS60 Connectors Outline
J4
J1
J7, J8
<Top view of the solder side>
J13
J1 1
J2
J3, J5
J12
J6
J9
J10
Figure3.1.1 M3A-HS60 Connector Assignment
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3
3.1.1 H-UDI Connector (J1)
The M3A-HS60 includes an H-UDI (J1) connector for connection to the E10A-USB emulator.
Figure3.1.2 shows a pin arrangement of the H-UDI connector.
35
36
1
2
Operational Specifications
3.1.1 H-UDI Connector (J1)
Board edge
Board edge
Figure3.1.2 Pin Arrangements of the H-UDI Connector
Table3.1.1 lists pin assignments of H-UDI connector.
Table3.1.1 Pin Assignments of H-UDI Connector (J1)
Pin Signal Name Pin Signal Name
1
AUDCK(PE0)
2
GND
3
AUDATA0(PE6)
4
GND
5
AUDATA1(PE5)
6
GND
7
AUDATA2(PE4)
8
GND
9
AUDATA3(PE3)
10
12
13
14
15
16
17
18
GND
11
AUDSYNC#(PA16)
GND
NC
GND
NC
GND
TCK
GND
J1
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Top view of the
Component side
Side view
TMS
GND
TRST#
GND
TDI
GND
TDO
GND
ASEBRKAK#/ASEBRK#
GND
+3.3V
GND
RES#
GND
GND
GND
NC
GND
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3.1.2 Serial Port Connector (J2)
The M3A-HS60 includes a serial port connector for serial communication (J2).
Figure3.1.3 shows a pin assignment of serial port connector.
5
9
Operational Specifications
3.1.2 Serial Port Connector (J2)
1
6
Board edge
5
9
Board edge
Figure3.1.3 Pin Arrangement of Serial Port Connector (J2)
Table3.1.2 lists pin assignments of serial port connector.
Table3.1.2 Pin Assignments of Serial Port Connector (J2)
Pin Signal Name Pin Signal Name
1 NC 6 DSR#
2 RXD(PA0/RxD0) 7 RTS#
3 TXD(PA1/TxD0) 8 CTS#
4 DTR# 9 NC
5 GND
J2
Top view of the
Component side
1
6
Side view
Pins 4-8 are loopback-connected.
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Operational Specifications
3
3.1.3 External Power Supply Connectors(J3 and J5)
The M3A-HS60 has the through-hole for two external power supply connectors (J3 for 3.3 V and J5 for 1.25 V) for the
SH7206.
Figure3.1.4 shows a pin assignment of external power supply connectors.
J3
12
Figure3.1.4 Pin Arrangement of External Power Supply Connectors (J3 and J5)
Table3.1.3, and Table3.1.4 list pin assignments of external power supply connectors.
Table3.1.3 Pin Assignments of External Power Supply Connector (J3)
Pin Signal Name Pin Signal Name
J5
12
3.1.3 External Power Supply Connectors(J3 and J5)
Top view of the
Component side
Board edge
1 +3.3V 2 GND
Table3.1.4 Pin Assignments of External Power Supply Connector (J5)
Pin Signal Name Pin Signal Name
1 +1.25V 2 GND
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3.1.4 Power Supply Connector (J4)
The M3A-HS60 includes a power supply connector for the board itself.
Figure3.1.5 shows a pin assignment of power supply connector.
Operational Specifications
3.1.4 Power Supply Connector (J4)
1
Board edge
J4
1
Board edge
Figure3.1.5 Pin Arrangement of Power Supply Connector (J4)
Table3.1.5 lists pin assignments of power supply connector for the M3A-HS60.
Table3.1.5 Pin Assignments of Power Supply Connector (J4)
Pin Signal Name Pin Signal Name
1 +5V 2 GND
2
Top view of the
Component side
2
Side view
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Operational Specifications
3
3.1.5 User I/O Connectors (J6-J8)
The through-hole for the extension connector pin connecting the pins of the on-chip peripheral functions (such as MTU2
and AD), which is suitable for the motor control of SH7206, is mounted on M3A-HS60.
Figure3.1.6 shows a pin arrangement of extension connector.
Note: The J6 connects the pins multiplexed to data bus (D31-D16) of SH7206. Therefore, the data bus D31–D16
becomes unusable when the J6 is used. Please set the SDRAM bus width to 16-bit wide (D15-D0) when the J6 is being
used.
Board edge
12
Top view of the
Solder side
Board edge
1
2
3
J7 J8
1
2
3
3.1.5 User I/O Connectors (J6-J8)
Top view of the
Component side
2526
Figure3.1.6 Pin Assignment of Extension Connectors (J6-J8)
Table3.1.6 and Table3.1.7 list pin assignments of the extension connectors.
Table3.1.6 Pin Assignments of Extension Connector (J6)
Pin Signal Name Pin Signal Name
+5V
1
3
5
7
9
11
13
15
17
19
21
23
25
NC (AN3/PF3 when R66 is mounted)
D26/DACK0/TIOC4BS/PD26
SCK3/TIOC3B/RTS3#/PE9
MRES#/TIOC4B/PE13
DACK1/CKE/TIOC4D/IRQOUT#/PE15
D20/IRQ4/TIC5WS/PD20
D22/IRQ6/TIC5US/AUDCK/PD22
AN2/PF2
AN4/PF4
D28/CS2#/TIOC3DS/PD28
D30/TIOC3CS/IRQOUT#/PD30
AN0/PF0
2
4
6
8
10
12
14
16
18
20
22
24
26
GND
D27/DACK1/TIOC4AS/PD27
D25/DREQ1/TIOC4CS/PD25
TXD3/TIOC4A/PE12
RXD3/TIOC3D/CTS3#/PE11
WE3#/ICIOWR#/AH#/DACK0/TIOC4C/PE14
D21/IRQ5/TIC5VS/PD21
D19/IRQ3/POE7#/AUDATA3/PD19
AN3/PF3
NC（AN4/PF4 when R67 is mounted）
D29/CS3#/TIOC3BS/PD29
D31/TIOC3AS/ADTRG#/PD31
AN1/PF1
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3
Operational Specifications
3.1.5 User I/O Connectors (J6-J8)
Table3.1.7 Pin Assignments of Extension Connectors (J7 and J8)
J7 J8
Pin Signal Name Pin Signal Name
D16/IRQ0/POE4#/AUDATA0/PD16
1
D17/IRQ1/POE5#/AUDATA1/PD17
2
D18/IRQ2/POE6#/AUDATA2/PD18
3
1
2
3
AN5/PF5
AN6/DA0/PF6
AN7/DA1/PF7
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Operational Specifications
3
3.1.6 Extension Connectors (J9-J13)
The M3A-HS60 has the trough-hole for extension bus connectors to which the I/O pins of the SH7206 are connected.
MIL Standard connectors can be mounted to J9–J13, and it is available for the connection to extension boards, or
monitoring the SH7206 bus signals. The bus signals of SH7206 are connected with J10 (J12) of the terminal connector
via J9 (J13).
J9 and J13 are connected to the terminal connector J10 (J12) via J9 (J13). J9 and J13 are mounted for the monitoring
signals by the measuring instrument. When the extension boards are made, J10 and J12 of the terminal connector are
recommended to be used to prevent the waveform distortion because of the reflection of the signal.
Figure3.1.7 shows a pin assignment of extension bus connector.
Board edge
19
20
40
39
20
19
J13
J12
2
1
3.1.5 User I/O Connectors (J6-J8)
2
1
J11
J9
20
1
Board edge
Figure3.1.7 Pin Assignment of Extension Connectors (J9-J13)
19
2
40
39
2
1
2
1
J10
Top view of the
Solder side
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3
Table 3.1.8 to 3.1.12 list pin assignments of extension connector.
Table3.1.8 Pin Assignment of Extension connector(J9)
Pin Signal name Pin Signal name
Operational Specifications
3.1.5 User I/O Connectors (J6-J8)
1
3
5
7
9
11
13
15
17
19
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
NC
EXCLK
A8
A6
A4
A2
A0/PC0
CS1#/POE5/PA11
RASU#/PINT4/CS4#/PA20
RESET#
Table3.1.9 Pin Assignment of Extension connector(J10)
Signal name
+3.3V
WDTOVF#
A24/RXD1/PA3
A22/DREQ1/IRQ1/SCK1/PA5
A20
A18
A16
A14
A12
A10
NC
EXCLK
A8
A6
A4
A2
A0/PC0
CS1#/POE5/PA11
RASU#/PINT4/CS4#/PA20
RESET#
2
NC
4
A9
6
A7
8
A5
10
A3
12
A1/PC1
14
CS0#
16
CS2#/TCLKA/PA6
18
CASU#/PINT5/CS5#/CE1A#/TIC5U/PA21
20
GND
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
+3.3V
A25/DREQ0/IRQ0/SCK0/PA2
A23/TXD1/PA4
A21/IRQ7/ADTRG#/POE8#/PB9
A19
A17
A15
A13
A11
GND
NC
A9
A7
A5
A3
A1/PC1
CS0#
CS2#/TCLKA/PA6
CASU#/PINT5/CS5#/CE1A#/TIC5U/PA21
GND
Signal name
Rev.1.00 June 1,2005 3-10
REJ1 1J0002-0100Z
3
Operational Specifications
3.1.5 User I/O Connectors (J6-J8)
Table3.1.10 Pin Assignments of Extension Connector(J13)
Pin Signal Name Pin Signal Name
1
NC
3
RD#
5
D14/TIOC4CS/PD14
7
D12/TIOC4AS/PD12
9
D10/TIOC3CS/PD10
11
D8/TIOC3AS/PD8
13
D6
15
D4
17
D2
19
D0
2
NC
4
D15/TIOC4DS/PD15
6
D13/TIOC4BS/PD13
8
D11/TIOC3DS/PD11
10
D9/TIOC3BS/PD9
12
D7
14
D5
16
D3
18
D1
20
GND
Table3.1.11 Pin Assignments of Extension Connector (J12)
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
Signal Name
+5V
WAIT#/DACK2/PA17
D30/TIOC3CS/IRQOUT#/PD30
D28/CS2#/TIOC3DS/PD28
D26/DACK0/TIOC4BS/PD26
D24/DREQ0/TIOC4DS/PD24
D22/IRQ6/TIC5US/AUDCK/PD22
D20/IRQ4/TIC5WS/PD20
D18/IRQ2/POE6#/AUDATA2/PD18
D16/IRQ0/POE4#/AUDATA0/PD16
TEND0/TIOC0B/PE1
RD#
D14/TIOC4CS/PD14
D12/TIOC4AS/PD12
D10/TIOC3CS/PD10
D8/TIOC3AS/PD8
D6
D4
D2
D0
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
Signal Name
+5V
D31/TIOC3AS/ADTRG#/PD31
D29/CS3#/TIOC3BS/PD29
D27/DACK1/TIOC4AS/PD27
D25/DREQ1/TIOC4CS/PD25
D23/IRQ7/AUDSYNC#/PD23
D21/IRQ5/TIC5VS/PD21
D19/IRQ3/POE7#/AUDATA3/PD19
D17/IRQ1/POE5#/AUDATA1/PD17
GND
DREQ1/TIOC0C/PE2
D15/TIOC4DS/PD15
D13/TIOC4BS/PD13
D11/TIOC3DS/PD11
D9/TIOC3BS/PD9
D7
D5
D3
D1
GND
Rev.1.00 June 1,2005 3-1 1
REJ1 1J0002-0100Z
3
Operational Specifications
3.1.5 User I/O Connectors (J6-J8)
Table3.1.12 Pin Assignment of Extension connector (J11)
Pin Signal Name Pin Signal Name
1
IRQ1/POE1#/SDA/PB3
3
CS3#/TCLKB/PA7
WE0#/DQMLL#/POE6#/PA12
5
WE2#/ICIORD#/DQMUL#/TIC5V/PA22
7
9
FRAME#/CKE/TCLKD/IRQ3/PA9
11
CASL#/IRQ3/POE3#/PB5
13
SCK2/TIOC3A/PE8
15
BS#/RXD2/TIOC2B/UBCTRG#/PE7
CE2B#/DACK3/PINT7/POE8#/PA25
17
BACK#/TEND1/PINT3/PA19
19
IRQ0/POE0#/SCL/PB2
2
RD_WR#/IRQ2/TCLKC/PA8
4
WE1#/WE#/DQMLU#/POE7#/PA13
6
8
WE3#/ICIOWR#/AH#/DQMUU#/TIC5W/PA23
RASL#/IRQ2/POE2#/PB4
10
12
CS8#/PE16
14
TXD2/TIOC3C/PE10
CE2A#/DREQ3/PINT6/PA24
16
BREQ#/TEND0/PINT2/PA18
18
GND
20
Rev.1.00 June 1,2005 3-12
REJ1 1J0002-0100Z
3
3.2 Outline of Switches and LEDs
The M3A-HS60 includes switches and LEDs as its operational components.
Figure3.2.1 shows the M3A-HS60 Operational Component Assignment.
<Top view of the component side>
JP1
JP2
Operational Specifications
3.2 Outline of Switches and LEDs
SW1
LED
6-8
LED
2-5
LED1
SW4
SW5 SW3 SW2
Figure3.2.1 M3A-HS60 Operational Component Assignment
Rev.1.00 June 1,2005 3-13
REJ1 1J0002-0100Z
SW6
Operational Specifications
J
J
3
3.2.1 Power Supply Select Jumpers (JP1 and JP2)
The SH7206 uses 3.3V and 1.25V power supply voltages. The JP1 and JP2 allow the sources for the SH7206
power supply voltages (3.3V and 1.25V) to be selected.
Figure3.2.2 shows the SH7206 Power Supply Voltage Select Jumpers Assignment (JP1 and JP2).
Table3.2.1 and Table3.2.2 list jumper settings for selecting SH7206 power supply voltage.
: Initial Setting
Board edge
3
P2 1.2V
P1
2
1
PWRSEL
3
3.3V
2
PWRSEL
1
Top view of the
component side
3.2.1 Power Supply Select Jumpers (JP1 and JP2)
Figure3.2.2 SH7206 Power Supply Voltage Select Jumper Assignment (JP1 and JP2)
Table3.2.1 Jumper Settings for Selecting SH7206 Power Supply Voltage (JP1)
Jumper Setting Function
JP1
3.3V PWRSEL
Jumper Setting Function
JP2.
1.2V PWRSEL
Note: Do not change jumper settings while the M3A-HS60 is being operated. Be sure to turn off the power of the
M3A-HS60 before changing jumper settings for all the time.
1-2
2-3
Table3.2.2 Jumper Settings for Selecting SH7206 Power Supply Voltage (JP2)
1-2
2-3
3.3 V fixed power supply voltage (supplied from regulator)
External power supply voltage (supplied from J3)
1.25 V fixed power supply voltage (supplied from regulator)
External power supply voltage (supplied from J5)
Rev.1.00 June 1,2005 3-14
REJ1 1J0002-0100Z
3
3.2.2 Switch and LED Functions
The M3A-HS60 includes six switches and eight LEDs.
Figure3.2.3 shows the M3A-HS60 Switch and LED Pin Assignment.
Table3.2.3 lists the switches mounted on M3A-HS60.
ON OFF
SW1
LED1
Operational Specifications
3.2.2 Switch and LED Functions
Top view of the
component side
PE1
PE2
PE8
PE10
SW2 SW5
RST
PE11
PE14
PE15
LED2
LED3
LED4
LED5
NMI
LED6
LED7
LED8
PA18
O N
1234
PA19
PA24
PA25
4321
SW4
SW3
54321
O N
Figure3.2.3 M3A-HS60 Switch and LED Pin Assignment
SW6
MRES
Table3.2.3 Switches Mounted on M3A-HS60
No. Function Remarks
SW1 System power on/off switch SW2 System reset input switch Refer to section 2.8 for details
SW3 User DIP switch (4-pole)
SW3-1 OFF:PA18=H,ON:PA18=L
PA18, PA19, PA24, and PA25 are pull-upped.
Refer to section 2.5 for details
SW3-2 OFF:PA19=H,ON:PA19=L
SW3-3 OFF:PA24=H,ON:PA24=L
SW3-4 OFF:PA25=H,ON:PA25=L
SW4
SW5
SW6
*1
System setup DIP switch (5-pole) Refer to Table 3.2.4 for function lists
NMI interrupt switch
Manual reset switch
Refer to section 2.9 for details
*1
Refer to section 2.9 for details
Although an internal state of CPU is initialized in manual reset, each register of the on-chip peripheral module is
not initialized
.
Rev.1.00 June 1,2005 3-15
REJ1 1J0002-0100Z
Operational Specifications
3
Table3.2.4 lists the functions of the switch SW4.
: Initial Setting
Table3.2.4 Functions of the Switch SW4
No. Setting Function
OFF SDRAM_SZ=H (32-bit access) SW4-1 *
SDRAM_SZ
MD_CLK2
Reserved
Reserved
FLASH _WP#
*
When using the J6 connector, make sure the SDRAM bus width is set to 16-bit access (SW4-1 OFF).
Table3.2.5 lists the functions of the LEDs mounted in M3A-HS60.
ON SDRAM_SZ=L (16-bit access)
OFF MD_CLK2 pin state “H” (Disable setting) SW4-2
ON MD_CLK2 pin state “L” (clock mode 2)
OFF Disable setting SW4-3
ON This setting should always be "ON"
OFF Disable setting SW4-4
ON This setting should always be "ON"
OFF Releases write protect for the flash memory(WP0# pin state “H”） SW4-5
ON Write protects the flash memory(WP0# pin state “L”)
3.2.2 Switch and LED Functions
Sets SDRAM bus width
Sets clock mode
Reserved
(Disable setting)
No. Color
LED1 Red
LED2 Green
LED3 Green
LED4 Green
LED5 Green
LED6 Green
LED7 Green
LED8 Green
Table3.2.5 Functions of the LEDs Mounted in M3A-HS60
Functions/Remarks
Power-on LED (LED1 lights when 3.3 V power is supplied)
"L"
"L"
"L"
"L"
"L"
"L"
"L"
)
)
)
)
)
)
)
Open to the user (LED2 lights when PE1 outputs
Open to the user (LED3 lights when PE2 outputs
Open to the user (LED4 lights when PE8 outputs
Open to the user (LED5 lights when PE10 outputs
Open to the user (LED6 lights when PE11 outputs
Open to the user (LED7 lights when PE14 outputs
Open to the user (LED8 lights when PE15 outputs
Rev.1.00 June 1,2005 3-16
REJ1 1J0002-0100Z
Operational Specifications
3
3.3 Outline Dimensions of M3A-HS60
3.3 Outline Dimensions of M3A-HS60
Figure3.3.1 shows the outline dimensions of M3A-HS60. Connectors can be mounted on J6-J13 so that it is easy to
connect extension boards.
<Top view of the component side> Unit :mm
<Perspective view of the component side>
Figure3.3.1 Outline Dimensions of M3A-HS60
Rev.1.00 June 1,2005 3-17
REJ1 1J0002-0100Z
3
Operational Specifications
3.3 Outline Dimensions of M3A-HS60
This is a blank page
Rev.1.00 June 1,2005 3-18
REJ1 1J0002-0100Z
Appendix
M3A-HS60 Schematics
A-1
This is a blank page
A-2
1
2
3
4
5
SH-2A SH7206 CPU BOARD M3A-HS60 SCHEMATICS
A A
TITLE
INDEX
CPU SH7206
FLASH
SDRAM
B B
UDI/RESET/UART/POWER
BUS CONNECTORS/PUSH SW
OTHERS
PAGE
1
2
3
4
5
6
7
Note:
C C
VCC = 5V
3VCC = 3.3V
1.2VCC = 1.25V
R = Fixed Resistors
RA = Resistor Array
C = Ceramic Caps
CE = Tantalum Electrolytic Caps
CP = Decoupling Caps
D D
[Note] :not mounted
CHANGE
CHANGE
CHANGE
Ver. 1.0
Ver. 1.0
Ver. 1.0
1
RENESAS SOLUTIONS CORPORATION
RENESAS SOLUTIONS CORPORATION
RENESAS SOLUTIONS CORPORATION
APPROVED
APPROVED
CHECKEDDRAWN
CHECKEDDRAWN
SCALE
SCALE
SCALE
DATE
DATE
DATE
05-06-01
05-06-01
05-06-01
2
3
CHECKEDDRAWN
DESIGNED
DESIGNED
DESIGNED
4
APPROVED
M3A-HS60
M3A-HS60
M3A-HS60
INDEX
INDEX
INDEX
DK30477-A
DK30477-A
DK30477-A
5
(
/)
17
(
/)
17
(
/)
17
1
MD0
BUS SizeMD2
32bit Bus
R60ΩR6
0Ω
R80ΩR8
0Ω
OUT3VCC
1
X2
X2
CSTCE16M6
CSTCE16M6
2
R14 0ΩR14 0Ω
CLK0
CLK1
CLK2
CLK3
CLK4
R70ΩR7
0Ω
R90ΩR9
0Ω
8
3
2
5
7
"1"
"0"
"1"
R10 18ΩR10 18Ω
13
16.66MHz
CERALOCK
R15 0ΩR15 0Ω
MODE2
MODE0
16bit Bus
8bit Bus
Reserve"0"
XIN
EXCLK [6]
_BS/RXD2/TIOC2B/_UBCTRG/PE7[6]
_CASU/PINT5/_CS5/_CE1A/TIC5U/PA21[6]
SerialUser Port
_BREQ/TEND0/PINT2/PA18[5,6]
_BACK/TEND1/PINT3/PA19[5,6]
DACK3/PINT7/_POE8/PA25[5,6]
"1"
"0"
A A
MD2 pin is fixed to "H"
MD0 pin is fixed to "L"
_CS0 = 16bit
3VCC
3VCC3VCC
X1
B B
CP1
CP1
0.1µF
0.1µF
X1
4
GND2OE
SG8002CA_16.66MHz
SG8002CA_16.66MHz
16.66MHz
XOUT
3VCC
C C
CP2
CP2
0.1µF
0.1µF
CKIO
R82 1MΩR82 1MΩ
U2
U2
1
REF
CY2305SC-1H
CY2305SC-1H
For SH7206 Bus Connector CLK
Extention Connector
D D
2
U1
U1
SH7206
SH7206
MODE2
MODE0
MD_CLK2[5]
RSVD1[5]
RSVD2[5]
CKIOH[4]
CKIOL[4]
_RESET[3,5,6]
NMI[6]
_WDTOVF[6]
_CS0[3,6]
_CS1/POE5/PA11[6]
_CS2/TCLKA/PA6[6]
_CS3[4,6]
_CS8/PE16[6]
_RD[3,6]
_WE0/_DQMLL[3,4,6]
_WE1/_DQMLU[4,6]
_WE2/_DQMUL[4,6]
_WE3/_DQMUU[4,6]
_WAIT/DACK2/PA17[6]
CKE[4,6]
RD_WR[4,6]
_RASL[4,6]
_RASU/PINT4/_CS4/PA20[6]
_CASL[4,6]
IRQ1/_POE1/SDA/PB3[6]
IRQ0/_POE0/SCL/PB2[6]
TXD0[5]
RXD0[5]
TXD2/TIOC3C/PE10[5,6]
SCK2/TIOC3A/PE8[5,6]
TEND0/TIOC0B/PE1[5,6]
DREQ1/TIOC0C/PE2[5,6]
DREQ3/PINT6/PA24[5,6]
TIOC4D/PE15[6]
_MRES/TIOC4B[6]
TIOC4C/PE14[6]
TIOC4A/PE12[6]
TIOC3D/PE11[6]
TIOC3B/PE9[6]
AN0[6]
AN1[6]
AN2[6]
AN3[6]
AN4[6]
AN5[6]
AN6[6]
AN7[6]
IRQ0/PD16[4,6]
IRQ1/PD17[4,6]
IRQ2/PD18[4,6]
IRQ3/PD19[4,6]
IRQ4/PD20[4,6]
IRQ5/PD21[4,6]
IRQ6/PD22[4,6]
PD28[4,6]
PD29[4,6]
PD30[4,6]
PD31[4,6]
TIOC4CS[4,6]
TIOC4BS[4,6]
TIOC4AS[4,6]
XOUT
XIN
CKIO
AVREF
R11 0ΩR11 0Ω
R4 22ΩR4 22Ω
R5 22ΩR5 22Ω
R12 22ΩR12 22Ω
PE7
PB3
PB2
PE10
PE8
PE1
PE2
PE12
PE9
R16 0ΩR16 0Ω
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
IRQ0/PD16
IRQ1/PD17
IRQ2/PD18
IRQ3/PD19
IRQ4/PD20
IRQ5/PD21
IRQ6/PD22
PD28
PD29
PD30
PD31
TIOC4CS
TIOC4BS
TIOC4AS
58
MD2
59
MD0
54
MD_CLK2
55
MD_CLK0
44
RSV1(PVSS)
45
RSV2(PVSS)
39
XTAL
40
EXTAL
32
CKIO
37
_RES
43
NMI
106
_WDTOVF
67
_CS0
68
_CS1/_POE5/PA11
168
_CS2/TCLKA/PA6
169
_CS3/TCLKB/PA7
52
_CS8/PE16
1
_RD
173
_WE0/_DQMLL/_POE6/PA12
172
_WE1/_WE/_DQMLU/_POE7/PA13
171
_WE2/_ICIORD/_DQMUL/TIC5V/PA22
170
_WE3/_ICIOWR/_AH/_DQMUU/TIC5W/PA23
62
_WAIT/DACK2/PA17
74
_BS/RXD2/TIOC2B/_UBCTRG/PE7
60
_FRAME/CKE/TCLKD/IRQ3/PA9
2
RD_WR/IRQ2/TCLKC/PA8
174
_RASL/IRQ2/_POE2/PB4
175
_RASU/PINT4/_CS4/PA20
166
_CASL/IRQ3/_POE3/PB5
165
_CASU/PINT5/_CS5/_CE1A/TIC5U/PA21
72
IRQ1/_POE1/SDA/PB3
73
IRQ0/_POE0/SCL/PB2
81
_CS5/_CE1A/PINT1/TXD0/PA1
85
_CS4/PINT0/RXD0/PA0
100
TXD2/TIOC3C/PE10
69
SCK2/TIOC3A/PE8
83
TEND0/TIOC0B/PE1
87
DREQ1/TIOC0C/PE2
30
_BREQ/TEND0/PINT2/PA18
109
_BACK/TEND1/PINT3/PA19
70
_CE2A/DREQ3/PINT6/PA24
71
_CE2B/DACK3/PINT7/_POE8/PA25
53
DACK1/CKE/TIOC4D/_IRQOUT/PE15
66
_MRES/TIOC4B/PE13
88
_WE3/_ICIOWR/_AH/DACK0/TIOC4C/PE14
105
TXD3/TIOC4A/PE12
103
RXD3/TIOC3D/_CTS3/PE11
61
SCK3/TIOC3B/_RTS3/PE9
98
AVREF
90
AN0/PF0
91
AN1/PF1
92
AN2/PF2
93
AN3/PF3
94
AN4/PF4
95
AN5/PF5
96
AN6/DA0/PF6
97
AN7/DA1/PF7
AVSS
89
3
3AVCC 1.2VCC
16
31
36
99
AVCC
VCCQ
VCCQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ64MD1 (VSSQ)
3
15
33
38
41
77
VCCQ
VSSQ
42
118
VCCQ
VSSQ
3VCCQ
63
76
117
125
131
149
163
176
13
24
57
79
101
VDD
VDD
VDD
VDD
SH7206
SH7206
_WE3/_ICIOWR/_AH/_DQMUU/DREQ2/CKE/_AUDSYNC/PA16
_CS6/_CE1B/TXD3/TIOC1B/AUDATA1/PE5
VSS
VSS
VSS
VSS
14
25
56
78
102
126
VCCQ
VSSQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
TESTMD (VSSQ)
VSSQ
VSSQ
VSSQ
65
113
133
147
162
115
145
159
VDD
VDD
VDD
_CS7/SCK3/TIOC2A/AUDATA0/PE6
_IOIS16/RXD3/TIOC1A/AUDATA2/PE4
VSS
VSS
VSS
114
144
158
VDD
A21/IRQ7/_ADTRG/_POE8/PB9
A22/DREQ1/IRQ1/SCK1/PA5
A25/DREQ0/IRQ0/SCK0/PA2
D16/IRQ0/_POE4/AUDATA0/PD16
D17/IRQ1/_POE5/AUDATA1/PD17
D18/IRQ2/_POE6/AUDATA2/PD18
D19/IRQ3/_POE7/AUDATA3/PD19
D22/IRQ6/TIC5US/AUDCK/PD22
D23/IRQ7/_AUDSYNC/PD23
D24/DREQ0/TIOC4DS/PD24
D25/DREQ1/TIOC4CS/PD25
D26/DACK0/TIOC4BS/PD26
D27/DACK1/TIOC4AS/PD27
D30/TIOC3CS/_IRQOUT/PD30
D31/TIOC3AS/_ADTRG/PD31
DREQ0/TIOC0A/AUDCK/PE0
TEND1/TIOC0D/AUDATA3/PE3
VSS
A0/PC0
A1/PC1
A23/TXD1/PA4
A24/RXD1/PA3
D8/TIOC3AS/PD8
D9/TIOC3BS/PD9
D10/TIOC3CS/PD10
D11/TIOC3DS/PD11
D12/TIOC4AS/PD12
D13/TIOC4BS/PD13
D14/TIOC4CS/PD14
D15/TIOC4DS/PD15
D20/IRQ4/TIC5WS/PD20
D21/IRQ5/TIC5VS/PD21
D28/_CS2/TIOC3DS/PD28
D29/_CS3/TIOC3BS/PD29
_TRST
_ASEMD
_ASEBRKAK/_ASEBRK
ASEBCK
RSV3(PVCC)
PLLVCC
PLLVSS
4
51
4
5
A2
6
A3
7
A4
8
A5
9
A6
10
A7
11
A8
12
A9
17
A10
18
A11
19
A12
20
A13
21
A14
22
A15
23
A16
26
A17
27
A18
28
A19
29
A20
46
47
48
49
50
164
D0
161
D1
160
D2
157
D3
156
D4
155
D5
154
D6
153
D7
152
151
150
148
146
143
142
141
140
139
138
137
136
135
134
132
130
129
128
127
124
123
122
121
110
TCK
116
TMS
112
TDI
120
TDO
111
119
104
107
108
75
167
84
82
86
80
35
34
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25 PA2a
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16 IRQ0/PD16
D17 IRQ1/PD17
D18 IRQ2/PD18
D19 IRQ3/PD19
D20 IRQ4/PD20
D21 IRQ5/PD21
D22 IRQ6/PD22
D23
D24
D25 TIOC4CS
D26 TIOC4BS
D27 TIOC4AS
D28 PD28
D29 PD29
D30 PD30
D31 PD31
TCK [5]
TMS [5]
TDI [5]
TDO [5]
_TRST [5]
_ASEMD [5]
_ASEBRAK/_ASEBRK [5]
RSV3
AUDCK [5]
AUDATA0
AUDATA1
AUDATA2
AUDATA3
1.2VCC
CP3
CP3
0.1µF
0.1µF
_AUDSYNC [5]
AUDATA0 [5]
AUDATA1 [5]
AUDATA2 [5]
AUDATA3 [5]
Decoupling Caps
1.2VCC
CP4
CP4
22nF
22nF
Decoupling Caps
3VCCQ
CP13
CP13
22nF
22nF
CP5
CP5
22nF
22nF
CP14
CP14
22nF
22nF
CP6
CP6
22nF
22nF
CP15
CP15
22nF
22nF
A[0:25] [3,4,6]
D[0:31] [3,4,6]
CP7
CP7
22nF
22nF
CP16
CP16
22nF
22nF
CP8
CP8
22nF
22nF
CP17
CP17
22nF
22nF
PA2a
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
3VCC_CPU
R13 0ΩR13 0Ω
PF5
PF2
PF4
PF3
PF1
PF0
PF7
PF6
CP9
CP9
22nF
22nF
CP18
CP18
22nF
22nF
5
R1 0ΩR1 0Ω
R2 0ΩR2 0Ω
R3 0ΩR3 0Ω
PE9
RSV3
PE12
PE7
CP10
CP10
22nF
22nF
CP19
CP19
22nF
22nF
3VCCQ
3AVCC
AVREF
1 5
9
2
8
3
7
4
6
6 5
4
7
3
8
2
9
1
1 5
9
2
8
3
7
4
6
6 5
4
7
3
8
2
9
1
1 5
2
3
4
6
7
8
9
1 5
2
3
4
6
7
8
9
CP11
CP11
22nF
22nF
CP20
CP20
22nF
22nF
1
1
1
PA2 [4,5]
10
RA1
RA1
A4.7KΩ
A4.7KΩ
10
RA2
RA2
A4.7KΩ
A4.7KΩ
10
RA3
RA3
A4.7KΩ
A4.7KΩ
10
RA4
RA4
A4.7KΩ
A4.7KΩ
10
RA5
RA5
A4.7KΩ
A4.7KΩ
10
RA12
RA12
A4.7KΩ
A4.7KΩ
CP12
CP12
0.1µF
0.1µF
CP21
CP21
0.1µF
0.1µF
H1
3VCCQH13VCCQ
H2
AVCCH2AVCC
H3
AVREFH3AVREF
3VCC
+
+
CE1
CE1
4.7µF
4.7µF
CHANGE
CHANGE
CHANGE
Ver. 1.0
Ver. 1.0
Ver. 1.0
RENESAS SOLUTIONS CORPORATION
RENESAS SOLUTIONS CORPORATION
RENESAS SOLUTIONS CORPORATION
4
APPROVED
APPROVED
APPROVED
DESIGNEDCHECKED
DESIGNEDCHECKED
DRAWN
DRAWN
SCALE
SCALE
SCALE
DATE
DATE
DATE
05-06-01
05-06-01
1
2
05-06-01
3
DRAWN
DESIGNEDCHECKED
M3A-HS60
M3A-HS60
M3A-HS60
CPU SH7206
CPU SH7206
CPU SH7206
DK30477-A
DK30477-A
DK30477-A
5
( / )27
( / )27
( / )27
1
D[0:31][2,4,6]
A[0:25][2,4,6]
A A
A23
A22
A21
R20
R20
4.7KΩ
4.7KΩ
B B
_RESET[2,5,6]
_CS0[2,6]
_RD[2,6]
_WE0/_DQMLL[2,4,6]
C C
FLASH_WP#[5]
R21
R21
4.7KΩ
4.7KΩ
R19
R19
4.7KΩ
4.7KΩ
3VCC
R22
R22
4.7KΩ
4.7KΩ
2
3VCC
R18 0ΩR18 0Ω
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
FVDD
R17 0ΩR17 0Ω
U3
U3
15
RY/BY
13
NC
10
A20
9
A19
16
A18
17
A17
48
A16
1
A15
2
A14
3
A13
4
A12
5
A11
6
A10
7
A9
8
A8
18
A7
19
A6
20
A5
21
A4
22
A3
23
A2
24
A1
25
A0
47
BYTE
12
RP
26
CE
28
OE
11
WE
14
WP
M5M29KT331AVP
M5M29KT331AVP
3
FVDD
H4
H4
1
FVDD
FVDD
37
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
45
43
41
39
36
34
32
30
44
42
40
38
35
33
31
29
DQ15/A-1
3VCC
M5M29KT331AVP
GND
GND
27
46
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
4
5
FLASH CSC CHANNEL 0
16bit access = 4MB
Decoupling Caps
FVDD
CP22
CP22
0.1µF
0.1µF
D D
RENESAS SOLUTIONS CORPORATION
RENESAS SOLUTIONS CORPORATION
CHANGE
CHANGE
CHANGE
Ver. 1.0
Ver. 1.0
Ver. 1.0
RENESAS SOLUTIONS CORPORATION
APPROVED
APPROVED
CHECKEDDRAWN
CHECKEDDRAWN
SCALE
SCALE
SCALE
DATE
DATE
DATE
05-06-01
05-06-01
05-06-01
1
2
3
CHECKEDDRAWN
DESIGNED
DESIGNED
DESIGNED
4
APPROVED
M3A-HS60
M3A-HS60
M3A-HS60
FLASH MEMORY
FLASH MEMORY
FLASH MEMORY
DK30477-A
DK30477-A
DK30477-A
5
(
/)
37
(
/)
37
(
/)
37
1
D[0:31][2,3,6]
A A
A[0:25][2,3,6]
SDRAM_SZ = "H" 32bit MODE
A2
A3
A4
A5
A6
A7
A8
A9
R24
R24
4.7KΩ
4.7KΩ
_CS3L
A10
A11
A12
A13
A14
A15
3VCC
B B
_CS3[2,6]
R27 0ΩR27 0Ω
1 2
U6A
U6A
HD74LVC14T
HD74LVC14T
U4
2
1A1
3
1A2
4
1A3
5
1A4
6
1A5
7
1A6
9
1A7
10
1A8
11
1A9
12
1A10
13
2A1
14
2A2
16
2A3
18
2A4
19
2A5
20
2A6
21
2A7
22
2A8
23
2A9
2A10242B10
48
1OE#
47
2OE#
PI3C16210AU4PI3C16210A
1B10
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
1B9
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
2B9
SDRAM_SZ = "L" 16bit MODE
A1
A2
A3
A4
A5
A6
C C
SDRAM_SZ[2,5]
A7
A8
A9
A10
A11
A12
A13
A14
U7
2
1A1
3
1A2
4
1A3
5
1A4
6
1A5
7
1A6
9
1A7
10
1A8
11
1A9
12
1A10
13
2A1
14
2A2
16
2A3
18
2A4
19
2A5
20
2A6
21
2A7
22
2A8
23
2A9
2A10242B10
48
1OE#
47
2OE#
PI3C16210AU7PI3C16210A
1B10
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
1B9
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
2B9
2
SA[1:15]A[0:25]
3
SVDD0
H5
1
SVDD0H5SVDD0
3VCC 3VCC
R23 0ΩR23 0Ω
SVDDQ0
4
H6
1
SVDDQ0H6SVDDQ0
R26 0ΩR26 0Ω
5
DUMPING REGISTER for SDRAM
CP27
CP27
0.1µF
0.1µF
CP28
CP28
0.1µF
0.1µF
SD[31:0]
CP29
CP29
0.1µF
0.1µF
Decoupling Caps
SVDD0
CP30
CP30
CP31
CP31
0.1µF
0.1µF
0.1µF
0.1µF
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
SD23
SD22
SD21
SD20
SD19
SD18
SD17
SD16
SD31
SD30
SD29
SD28
SD27
SD26
SD25
SD24
CP32
CP32
0.1µF
0.1µF
RA6
RA6
1
2
3
4
5
6
7
8
N0Ω
N0Ω
RA7
RA7
1
2
3
4
5
6
7
8
N0Ω
N0Ω
RA8
RA8
1
2
3
4
5
6
7
8
N0Ω
N0Ω
RA9
RA9
1
2
3
4
5
6
7
8
N0Ω
N0Ω
SVDD1SVDDQ1
CP33
CP33
0.1µF
0.1µF
D7
16
D6
15
D5
14
D4
13
D3
12
D2
11
D1
10
D0
9
D15
16
D14
15
D13
14
D12
13
D11
12
D10
11
D9
10
D8
9
D23
16
D22
15
D21
14
D20
13
D19
12
D18
11
D17
10
D16
9
D31
16
D30
15
D29
14
D28
13
D27
12
D26
11
D25
10
D24
9
CP34
CP34
0.1µF
0.1µF
U5
U5
SA14
21
SA1
46
SA2
45
SA3
44
SA4
43
SA5
42
SA6
40
SA7
39
SA8
38
SA9
37
SA10
36
SA11
35
SA12
34
SA13
33
SA14
31
30
29
28
27
26
25
1
NC
3VCC
CP23
CP23
0.1µF
0.1µF
SA1
46
SA2
45
SA3
44
SA4
43
SA5
42
SA6
40
SA7
39
SA8
38
SA9
37
SA10
36
SA11
35
SA12
34
SA13
33
SA14
31
30
29
28
27
26
25
1
NC
3VCC
CP25
CP25
0.1µF
0.1µF
3VCC
R25
R25
4.7KΩ
4.7KΩ
_RASL[2,6]
_CASL[2,6]
RD_WR[2,6]
_WE3/_DQMUU[2,6]
_WE2/_DQMUL[2,6]
CKE[2,6]
CKIOH[2]
_WE1/_DQMLU[2,6]
_WE0/_DQMLL[2,3,6]
CKIOL[2]
R28 0ΩR28 0Ω
R30 0ΩR30 0Ω
R29 0ΩR29 0Ω
R31 0ΩR31 0Ω
R32 0ΩR32 0Ω
R33 0ΩR33 0Ω
R36 0ΩR36 0Ω
R37 0ΩR37 0Ω
SDRAS#
SDCAS#
SDWE#
DQMUU
DQMUL
SDCKE
DQMLU
DQMLL
_CS3H
_CS3L
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
BA1
20
BA0
35
A11
22
A10
34
A9
33
A8
32
A7
31
A6
30
A5
29
A4
26
A3
25
A2
24
A1
23
A0
19
CS
18
RAS
17
CAS
16
WE
39
DQMU
15
DQML
37
CKE
38
CLK
EDS1216AATA
EDS1216AATA
H7
1
SVDD1H7SVDD1
3VCC 3VCC
R34 0ΩR34 0Ω
U8
U8
21
BA1
20
BA0
35
A11
22
A10
34
A9
33
A8
32
A7
31
A6
30
A5
29
A4
26
A3
25
A2
24
A1
23
A0
19
CS
18
RAS
17
CAS
16
WE
39
DQMU
15
DQML
37
CKE
38
CLK
EDS1216AATA
EDS1216AATA
27
VDD1VDD14VDD
VDDQ3VDDQ9VDDQ
VSSQ6VSSQ
VSS28VSS41VSSQ46VSSQ
VSS
12
54
SVDD1
SVDDQ1
27
VDD1VDD14VDD
VDDQ3VDDQ9VDDQ
EDS1216AATA EDS1216AATA
VSSQ6VSSQ
VSS28VSS41VSSQ46VSSQ
VSS
12
54
43
49
VDDQ
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
52
R35 0ΩR35 0Ω
43
49
VDDQ
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
52
SD31
53
SD30
51
SD29
50
SD28
48
SD27
47
SD26
45
SD25
44
SD24
42
SD23
13
SD22
11
SD21
10
SD20
8
SD19
7
SD18
5
SD17
4
SD16
2
40
NC
36
NC
H8
1
SVDDQ1H8SVDDQ1
SD15
53
SD14
51
SD13
50
SD12
48
SD11
47
SD10
45
SD9
44
SD8
42
SD7
13
SD6
11
SD5
10
SD4
8
SD3
7
SD2
5
SD1
4
SD0
2
40
NC
36
NC
SVDDQ0
D D
RENESAS SOLUTIONS CORPORATION
RENESAS SOLUTIONS CORPORATION
CHANGE
CHANGE
CHANGE
Ver. 1.0
Ver. 1.0
Ver. 1.0
RENESAS SOLUTIONS CORPORATION
4
APPROVED
APPROVED
APPROVED
DESIGNEDCHECKED
DESIGNEDCHECKED
DRAWN
DRAWN
SCALE
SCALE
SCALE
DATE
DATE
DATE
05-06-01
05-06-01
1
2
05-06-01
3
DRAWN
DESIGNEDCHECKED
M3A-HS60
M3A-HS60
M3A-HS60
SDRAM
SDRAM
SDRAM
DK30477-A
DK30477-A
DK30477-A
5
( / )47
( / )47
( / )47
1
2
3
4
5
H-UDI INTERFACE
3VCC3VCC3VCC
10
1 5234678
AUDCK[2]
A A
AUDATA0[2]
AUDATA1[2]
AUDATA2[2]
AUDATA3[2]
_AUDSYNC[2]
TCK[2]
TMS[2]
_TRST[2]
TDI[2]
TDO[2]
_ASEBRAK/_ASEBRK[2]
R40 22ΩR40 22Ω
R43 22ΩR43 22Ω
R41 22ΩR41 22Ω
R42 22ΩR42 22Ω
R45
R45
1KΩ
1KΩ
R38
R38
R39
4.7KΩ
4.7KΩ
R39
4.7KΩ
4.7KΩ
3VCC
29
11
17
19
21
23
25
27
31
1
3
5
7
9
J1
UVCC
AUDCK
AUDATA0
AUDATA1
AUDATA2
AUDATA3
_AUDSYNC
TCK
TMS
_TRST
TDI
TDO
_ASEBRAK
_RES
DX10M-36J1DX10M-36
15
NC
13
NC
35
NC
2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3VCC
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
33
34
36
R44
R44
4.7KΩ
4.7KΩ
_ASEMD [2]
RA10
RA10
A4.7KΩ
A4.7KΩ
9
Power On Reset
3VCC
R48
R48
Ra
10KΩ
10KΩ
U11
U11
R52
R52
10KΩ
10KΩ
7
OUT
2
IN
VCC
GND
4
M51957BFP
M51957BFP
B B
Decoupling Caps
3VCC
Rb
CP36
CP36
0.1µF
0.1µF
R49
R49
4.7KΩ
4.7KΩ
6
5
Cd
R50
R50
100Ω
100Ω
SW2
C5
0.1µFC50.1µF
Cd
SW2
B3SN-3012
B3SN-3012
RESET
SWITCH
U6B
U6B
3 4
HD74LVC14T
HD74LVC14T
td = 34ms[0.34*Cd(pF)usec]
Vs = 2.5V[1.25*((Ra+Rb)/Rb)]
U6C
U6C
5 6
HD74LVC14T
HD74LVC14T
_RESET [2,3,6]
3VCC
CP37
CP37
0.1µF
0.1µF
Decoupling Caps
7414
SERIAL CONNECTOR(COM)
TXD0[2]
RXD0[2]
5V TO 3.3V LINEAR REGULATOR
1-2 Power On
2-3 Power Off
Power
Switch
J4
S2B-XH-AJ4S2B-XH-A
SW1
SW1
1
2
1
2
Power
Connector
3
+
+
CE4
MS-12AAH1
MS-12AAH1
CE4
10µF
10µF
VOUT = VREF * (1 + Rb/Ra) + IADJ * (Rb)
U9
1
C1+
C1
0.1µFC10.1µF
3
C1-
4
C2+
C3
0.1µFC30.1µF
5
C2-
CTS# CTS#
12
R1OUT
TxD
11
T1IN
RTS#
10
T2IN
RxD
9
R2OUT
SP3232EU9SP3232E
U10
U10
RC1587M
RC1587M
IN3OUT
ADJ/GND
1
IADJ = 25µA
2
V+
6
V-
13
R1IN
14
T1OUT
7
T2OUT
8
R2IN
Vout = 3.302V
2
R47
R47
Ra
110Ω
110Ω
R51
R51
Rb
180Ω
180Ω
C2
0.1µFC20.1µF
C4
0.1µFC40.1µF
+
CE6
+
CE6
22µF
22µF
RI#
DTR#
TxD
RTS#
RxD
DSR#
DCD#
3VCCVCC
+
CE5
+
CE5
22µF
22µF
UART connector
mount hole = GND
J2
J2
5
9
4
8
3
7
2
6
1
XM2C-0912-112
XM2C-0912-112
3.3V EXTERNAL
3VCC_EX
J3
J3
1
2
+
+
CE3
JP1
JP1
1
3
HW-3P
HW-3P
CE3
10µF
10µF
2
A2-2PA-2.54DSA
A2-2PA-2.54DSA
3VCC_EX 3VCC 3VCC_CPU
1-2 Fixed 3.3V
2-3 External 3.3V
3VCC
+
+
CP35
CP35
CE2
CE2
0.1µF
0.1µF
4.7µF
4.7µF
Decoupling Caps
for SP3232E
POWER LED 3.3VCC
3VCC
R46
R46
330Ω
330Ω
LED1
LED1
BR1102W
BR1102W
RED
All regulator TABs are VOUT.
User Port
C C
TEND0/TIOC0B/PE1[2,6]
DREQ1/TIOC0C/PE2[2,6]
SCK2/TIOC3A/PE8[2,6]
TXD2/TIOC3C/PE10[2,6]
Mode
Switch
D D
CHANGE
CHANGE
CHANGE
Ver. 1.0
Ver. 1.0
Ver. 1.0
1
2
3
4
5
PE1
PE2
PE8
PE10
SW4
SW4
A6S-5101
A6S-5101
1
3VCC
R54
R53
R53
330Ω
330Ω
ON
ON
10
9
8
7
6
R54
330Ω
330Ω
LED2LED2
GREEN GREEN GREEN GREEN
3VCC
10
1 5234678
LED3LED3
RA11
RA11
A4.7KΩ
A4.7KΩ
9
R55
R55
330Ω
330Ω
LED4LED4
R56
R56
330Ω
330Ω
LED5LED5
PA2 [2,4]
SDRAM_SZ [2,4]
MD_CLK2 [2]
RSVD2 [2]
RSVD1 [2]
FLASH_WP# [3]
3VCC
R57
R57
R58
R58
4.7KΩ
4.7KΩ
4.7KΩ
SW3
SW3
ON
ON
1
2
3
4
A6S-4104
A6S-4104
1:ON SDRAM_SZ = L (16bit access)
1:OFF SDRAM_SZ = H (32bit access)
2:ON MD_CLK2 = L
2:OFF MD_CLK2 = H
3:ON RESERVED2 = L
3:OFF RESERVED2 = H
4:ON RESERVED1 = L
4:OFF RESERVED1 = H
5:ON FLASH WRITE PROTECT
5:OFF FLASH UNLOCK
2
4.7KΩ
8
7
6
5
R59
R59
4.7KΩ
4.7KΩ
R60
R60
4.7KΩ
4.7KΩ
PA18
PA19
PA24
PA25
_BREQ/TEND0/PINT2/PA18 [2,6]
_BACK/TEND1/PINT3/PA19 [2,6]
DREQ3/PINT6/PA24 [2,6]
DACK3/PINT7/_POE8/PA25 [2,6]
SCALE
SCALE
SCALE
DATE
DATE
DATE
05-06-01
05-06-01
05-06-01
5V TO 1.25V STEP DOWN REGULATOR
VCC
+
CE8
+
CE8
+
CE7
+
CE7
10µF
10µF
10µF
10µF
R62
R62
150KΩ
150KΩ
C7
47pFC747pF
RENESAS SOLUTIONS CORPORATION
RENESAS SOLUTIONS CORPORATION
RENESAS SOLUTIONS CORPORATION
DRAWN
DRAWN
DRAWN
3
C8
220pFC8220pF
DESIGNEDCHECKED
DESIGNEDCHECKED
DESIGNEDCHECKED
8
9
2
13
15
16
14
4
LTC1875
LTC1875
U12
U12
PVIN1
PVIN2
RUN/SS
SVIN
SYNC/MODE
PLL_LPF
PGOOD
ITH
PGND17PGND2
10
4
SWP1
SWP2
SWN1
SWN2
SGND
VFB
5
12
6
11
3
1
APPROVED
APPROVED
APPROVED
1.2VCC_IN
L1 4.7µHL1 4.7µH
R61
R61
28KΩ
28KΩ
+
+
CE9
CE9
330µF
330µF
R63
R63
49.9KΩ
49.9KΩ
M3A-HS60
M3A-HS60
M3A-HS60
H-UDI/RESET/UART/POWER
H-UDI/RESET/UART/POWER
H-UDI/RESET/UART/POWER
DK30477-A
DK30477-A
DK30477-A
1.2V EXTERNAL
J5
J5
A2-2PA-2.54DSA
A2-2PA-2.54DSA
C6
1µFC61µF
1.2VCC_EX 1.2VCC_IN 1.2VCC
1-2 Fixed 1.2V
2-3 External 1.2V
5
1.2VCC_EX
1
2
+
+
CE10
CE10
10µF
10µF
JP2
JP2
1
2
3
HW-3P
HW-3P
( / )57
( / )57
( / )57
1
2
3
4
5
Extension Connector
VCC
R73
R73
10KΩ
10KΩ
R75 0ΩR75 0Ω
CE11
CE11
4.7µF
4.7µF
R78
R78
10KΩ
10KΩ
R80 0ΩR80 0Ω
CE12
CE12
4.7µF
4.7µF
J6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
XG4C-2634J6XG4C-2634
TIOC3D/PE11
TIOC4C/PE14
TIOC4D/PE15
9 8
U6D
U6D
HD74LVC14T
HD74LVC14T
_MRES
IRQ0/PD16[2,4]
IRQ1/PD17[2,4]
IRQ2/PD18[2,4]
3VCC
R68
R68
330Ω
330Ω
11 10
IRQ0/PD16
IRQ1/PD17
IRQ2/PD18
AN5[2]
AN6[2]
AN7[2]
R69
R69
330Ω
330Ω
LED6LED6
GREEN GREEN GREEN
U6E
U6E
HD74LVC14T
HD74LVC14T
A A
TIOC4AS[2,4]
TIOC4BS[2,4]
TIOC4CS[2,4]
TIOC3B/PE9[2]
TIOC4A/PE12[2]
_MRES/TIOC4B[2]
TIOC3D/PE11[2]
TIOC4D/PE15[2]
TIOC4C/PE14[2]
IRQ4/PD20[2,4]
IRQ5/PD21[2,4]
IRQ6/PD22[2,4]
IRQ3/PD19[2,4]
AN2[2]
AN3[2]
AN4[2]
PD28[2,4]
PD29[2,4]
PD30[2,4]
PD31[2,4]
AN0[2]
AN1[2]
B B
AN3
R66 0ΩR66 0Ω
TIOC4B _MRES
TIOC3D/PE11
TIOC4D/PE15
TIOC4C/PE14
IRQ4/PD20
IRQ5/PD21
IRQ6/PD22
IRQ3/PD19
AN2
AN3
AN4
AN4
R67 0ΩR67 0Ω
PD28
PD29
PD30
PD31
NMI SWITCH CIRCUIT
3VCC
R74 100ΩR74 100Ω
+
NMI
SW5
SW5
B3SN-3012
B3SN-3012
SWITCH
C C
MRES SWITCH
CIRCUIT
R79 100ΩR79 100Ω
MRES
SW6
SW6
B3SN-3012
B3SN-3012
SWITCH
D D
+
3VCC
+
+
LED7LED7
NMI [2]
J7
J7
1
2
3
A2-3PA-2.54DSA
A2-3PA-2.54DSA
J8
J8
1
2
3
A2-3PA-2.54DSA
A2-3PA-2.54DSA
R72
R72
330Ω
330Ω
LED8LED8
Extension Bus Connector
_WDTOVF[2]
A[0:25][2,3,4]
EXCLK[2]
_CS0[2,3]
_CS1/POE5/PA11[2]
_CS2/TCLKA/PA6[2]
_RASU/PINT4/_CS4/PA20[2]
_CASU/PINT5/_CS5/_CE1A/TIC5U/PA21[2]
_RESET[2,3,5]
_WAIT/DACK2/PA17[2]
D[0:31][2,3,4]
_RD[2,3]
_RESET
EXCLK
_CS0
PA11
PA6
PA20
PA21
_RD
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
3VCC
R650ΩR65
R640ΩR64
0Ω
0Ω
J10
J10
1
_WDTOVF
TXD1/PA4 A23
IRQ7/_ADTRG/_POE8/PB9 A21
J9
1
2
3
A9
4
A8
5
A7
6
A6
7
A5
8
A4
9
A3
10
A2
11
A1
12
A0
13
14
15
16
17
18
19
20
XG4C-2031J9XG4C-2031
_WAIT/DACK2/PA17
D31
D30
D29
D28
D27TIOC4AS DACK1/PD27
D26TIOC4BS DACK0/PD26
D25TIOC4CS DREQ1/PD25
D24DREQ0/PD24
D23IRQ7/PD23
D22IRQ6/PD22
D21IRQ5/PD21
D20IRQ4/PD20
D19IRQ3/PD19
D18IRQ2/PD18
D17IRQ1/PD17
J13
J13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
XG4C-2031
XG4C-2031
TEND0/TIOC0B/PE1[2,5]
DREQ1/TIOC0C/PE2[2,5]
D16IRQ0/PD16
TEND0/TIOC0B/PE1
DREQ1/TIOC0C/PE2
TEND0/TIOC0B/PE1
DREQ1/TIOC0C/PE2
2
3
A25DREQ0/IRQ0/SCK0/PA2
4
A24RXD1/PA3
5
6
A22DREQ1/IRQ1/SCK1/PA5
7
8
A20
9
A19
10
A18
11
A17
12
A16
13
A15
14
A14
15
A13
16
A12
17
A11
18
A10
19
EXCLK
R760ΩR76
0Ω
_RD
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
_CS0
PA11
PA6
PA20
PA21
_RESET
VCC
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
XG4C-4031
XG4C-4031
R770ΩR77
0Ω
J12
J12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
XG4C-4031
XG4C-4031
IRQ1/_POE1/SDA/PB3[2]
IRQ0/_POE0/SCL/PB2[2]
_CS3[2,4]
RD_WR[2,4]
_WE0/_DQMLL[2,3,4]
_WE1/_DQMLU[2,4]
_WE2/_DQMUL[2,4]
_WE3/_DQMUU[2,4]
CKE[2,4]
_RASL[2,4]
_CASL[2,4]
_CS8/PE16[2]
SCK2/TIOC3A/PE8[2,5]
TXD2/TIOC3C/PE10[2,5]
_BS/RXD2/TIOC2B/_UBCTRG/PE7[2]
DREQ3/PINT6/PA24[2,5]
DACK3/PINT7/_POE8/PA25[2,5]
_BREQ/TEND0/PINT2/PA18[2,5]
_BACK/TEND1/PINT3/PA19[2,5]
R71 0ΩR71 0Ω
R70 0ΩR70 0Ω
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
J11
J11
XG4C-2031
XG4C-2031
CHANGE
CHANGE
CHANGE
Ver. 1.0
Ver. 1.0
Ver. 1.0
RENESAS SOLUTIONS CORPORATION
RENESAS SOLUTIONS CORPORATION
RENESAS SOLUTIONS CORPORATION
4
APPROVED
APPROVED
APPROVED
DESIGNEDCHECKED
DESIGNEDCHECKED
DRAWN
DRAWN
SCALE
SCALE
SCALE
DATE
DATE
DATE
05-06-01
05-06-01
1
2
05-06-01
3
DRAWN
DESIGNEDCHECKED
M3A-HS60
M3A-HS60
M3A-HS60
BUS CONNECTORS/PUSH SW
BUS CONNECTORS/PUSH SW
BUS CONNECTORS/PUSH SW
DK30477-A
DK30477-A
DK30477-A
5
( / )67
( / )67
( / )67
1
2
3
4
5
TEST PIN
A A
MH1
MH1
H9
VCC 3VCC 1.2VCC
H10
H10
H11
H11
H12
H12
1
VCCH9VCC
B B
1
3VCC
3VCC
1
1.2VCC
1.2VCC
1
GND
GND
H13
H13
1
GND
GND
MOUNT-HOLE
MOUNT-HOLE
MH2
MH2
1
1
1
1
UNUSED LOGIC
MOUNT-HOLE
MOUNT-HOLE
MH3
MH3
1
13 12
MOUNT-HOLE
U6F
U6F
HD74LVC14T
HD74LVC14T
C C
MOUNT-HOLE
MH4
MH4
AGND-GND
1
1
1
R81 0ΩR81 0Ω
D D
RENESAS SOLUTIONS CORPORATION
RENESAS SOLUTIONS CORPORATION
RENESAS SOLUTIONS CORPORATION
DESIGNED
DESIGNED
DESIGNED
CHANGE
CHANGE
CHANGE
Ver. 1.0
Ver. 1.0
Ver. 1.0
CHECKEDDRAWN
CHECKEDDRAWN
SCALE
SCALE
SCALE
DATE
DATE
DATE
05-06-01
05-06-01
05-06-01
1
2
3
CHECKEDDRAWN
MOUNT-HOLE
MOUNT-HOLE
4
APPROVED
APPROVED
APPROVED
M3A-HS60
M3A-HS60
M3A-HS60
OTHERS
OTHERS
OTHERS
DK30477-A
DK30477-A
DK30477-A
5
(
/)
77
(
/)
77
(
/)
77
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SH7206 CPU Board
M3A-HS60
User's Manual
Publication Data June 1,2005
Published by
© 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
Renesas Technology Corp.
Renesas Solutions Corp.
Rev. 1.00
M3A-HS60
User's Manual
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