Renesas SH7145F User Manual

APPLICATION NOTE

SH7145F

Asynchronous Serial Data Transmission/Reception

Summary

The SH7144 series is a single-chip microprocessor based on the SH-2 RISC (Reduced Instruction
Set Computer) CPU core and integrating a number of peripheral functions.

This application note describes asynchronous serial data transmission/reception using the SCI
(Serial Communication Interface) module of the SH7145F. It is intended to be used as reference
by users designing software applications.

The program examples contained in this application note have b een tested. However, operation
should be confirmed before using them in an actual application.

Device for Which Operation Has Been Confirmed

SH7145F

Contents

1. Specifications................................................................................................ 2

2 Functions Used ............................................................................................. 3

3. Operation....................................................................................................... 6

4. Software........................................................................................................ 8

5. Flowcharts..................................................................................................... 11

6. Program Listing............................................................................................. 14

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SH7145F

Asynchronous Serial Data Transmission/Reception

1. Specifications

As shown in figure 1, asynchronous serial data transmission is performed using channel 1 (ch1) of
the SCI module of the SH7145F. In this task example 3 bytes of serial data are received by
SH7145,

and the receive data is then transmitted. The communication format is 192,000 bps, 8-

bit, one stop bit, and no parity.

Serial data

3.3 V 3.3 V

SH7145

transfer
target MCU

the

SCI

(ch1)

TXD
RXD

RXD
TXD

Figure 1 Asynchronous Serial Data Transmission/Reception by SH7145

Table 1 Asynchronous Serial Data Transmission Format

Format Item Setting

Bit rate 19200 bps
Data length 8 bits
Parity bit No
Stop bit 1 bit
Serial/parallel conversion format LSB first

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SH7145F

k

Asynchronous Serial Data Transmission/Reception

2 Functions Used

In this task example the SCI (Serial Communication Interface) is used to perform asynchronous
serial data transmission/reception. Figure 2 shows a block diagram of channel 1 (ch1) of the SCI
module. The functions of the elements shown in figure 2 are described below.

SCI0 synchronous serial transfer function block

On-chip
peripheral cloc

Pφ/128
Pφ/32
Pφ/8
Pφ1

SCI1 clock I/O pin
(SCK1)

External
clock

Baud rate generator

Clock

Transmit/receive operation control settings

Transfer rate generator

Bit rate register 1

(BRR_1)

SCI1 transmit data
output pin
(TXD1)

SCI1 receive data
input pin
(RXD1)

Transmit/receive

control circuit

Transmit shift register 1

(TSR_1)

Receive shift register 1

(RSR_1)

Serial mode register 1

(SMR_1)

Serial control register 1

(SCR_1)

Serial status register 1

(SSR_1)

Serial direction control register 1

(SDCR_1)

Transmit data control

Transmit data register 1

(TDR_1)

Receive data control

Receive data register 1

(RDR_1)

Interrupt
requests

Figure 2 SCI (ch1) Block Diagram

• Asynchronous Mode

Serial data communication is performed using synchronization by character unit. This allows
serial communication with a standard dedicated asynchronous communication chip such as a
Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication
Interface Adapter (ACIA). In addition, the asynchronous mode supports serial communication
among multiple processors (multiprocessor communication function).

TEI_1
TXI_1

RXI_1

ERI_1

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Asynchronous Serial Data Transmission/Reception

• On-Chip Peripheral Clock Pφ

This is the reference clock for operation of on-chip peripheral functions. The clock signal is
generated by a clock oscillator.

• Receive Shift Register (RSR_1)

This register is used to receive serial data. Serial data is i nput to RSR_1 from the RxD_1 pin.
When one frame of data has been received, it is automatically tra nsferred to the receive data
register (RDR_1). RSR_1 cannot be accessed by the CPU.

• Receive Data Register (RDR_1)

Received data is stored in this 8-bit register. When one frame of data has been received, it is
automatically transferred from RSR_1. RSR_1 and RDR_1 are in a double-buffer
configuration, allowing continuous reception of data. RDR_1 is a receive-only register, so it
can only be read b y the CPU.

• Transmit Shift Register (TSR_1)

This register is used to transmit serial data. In order to transmit data, the data is first
transferred from the transmit data register (TDR_1) to TSR_1. Then the transmit data is
output from the TxD_1 pin. TSR_1 cannot be accessed directly by the CPU.

• Transmit Data Register (TDR_1)

SH7145F

Data to be transmitted is stored in this 8-bit register. When it is detected that TDR_1 is empty,
data that has been written to TDR_1 is automatically transferred to TSR_1. TDR_1 and
TSR_1 are in a double-buffer configuration. This allows data to be transferred to TSR_1 after
one frame of data has been transmitted and the next frame of data is still being written to
TDR_1, making possible continuous transmission of data. It is always possible to read or
write to the TDR from the CPU, but before writing to the TDR it should be confirmed that the
value of the TDRE bit in the serial status register (SSR_1) is 1.

• Serial Mode Register (SMR_1)

This 8-bit register is used to select the serial data communication format and the clock source
for the on-chip baud rate generator.

• Serial Control Register (SCR_1)

This register is used for transmit and receive control, interrupt control, and to select the
transmit and receive clock source.

• Serial Status Register (SSR_1)

This register comprises the SCI1 stat us flag and the transmit and receive multiprocessor bits.
TDRE, RDRF, ORER, PER, and FER can be cleared only.

• Serial Direction Control Register (SDCR_1)

This register is used to select whether the LSB or MSB is first. For 8-bit communication
either LSB-first or MSB-first may be selected, but LSB-first should be used for 7-bit
communication.

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Asynchronous Serial Data Transmission/Reception

• Bit Rate Register (BRR_1)

This 8-bit register is used to adjust the bit rate. The SCI has independent baud rate generators
for the individual channels, allowing different bit rates to be set for each. See the hardware
manual for details on sett ing values, execution rate relationship s, etc.

Table 2 shows the function allocations for the task example.

Table 2 Function Allocations

Function Classification Function Allocation

TXD1 Pin Channel 1 transmit data output pin
RXD1 Pin Channel 1 transmit data input pin
SMR_1 SCI1 Sets communication format to asynchronous mode
SCR_1 SCI1 Enables transmit operation
SSR_1 SCI1 Status flag showing SCI1 operation status
SDCR_1 SCI1 Specifies LSB-first
BRR_1 SCI1 Sets communication bit rate
TSR_1 SCI1 Register for transmitting serial data
TDR_1 SCI1 Register for storing transmit data
RSR_1 SCI1 Register for receiving serial data
RDR_1 SCI1 Register for storing receive data

SH7145F

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SH7145F

Asynchronous Serial Data Transmission/Reception

3. Operation

Figure 3 shows the operation of asynchronous mode data transmission in the task example. To
help explain figure 3, table 3 lists the software and hardware processing that is performed.

(1)

(3)

TxD1
(pin)

RDRF
(SSR_1 bit)

Receive operation
Transmit operation

TDR_1
(register)

TSR_1
(register)

TXD1
(pin)

Start
bit

0

Data
bits

(2)

Stop
bit

1

(6)

(4)

(7) (8)

(5)

Start
bit

Data bits D0 to D7

0

(9)

(10)

Start
bit

Data bits D0 to D7

0

(11)
(12)(13)

(14)
(15)

TDRE
(SSR_1 bit)

Notes: 1. The start bit, transmit data, parity bit, and stop bit are output, in that order, from the TxD1 pin.

2. To perform continuous reception, read data transferred to RDR until reception of next data is
complete.

Figure 3 Data Transmission Operation

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