Page 1
REJ09B0243-0300
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
SH7125 Group, SH7124 Group
32
Hardware Manual
Renesas 32-Bit RISC Microcomputer
SuperH™ RISC engine Family
SH7125 R5F7125
SH7124 R5F7124
Rev.3.00
Revision Date: Sep. 27, 2007
Page 2
Rev. 3.00 Sep. 27, 2007 Page ii of xx
Page 3
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
Rev. 3.00 Sep. 27, 2007 Page iii of xx
Page 4
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product's state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.
Rev. 3.00 Sep. 27, 2007 Page iv of xx
Page 5
Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 3.00 Sep. 27, 2007 Page v of xx
Page 6
Preface
The SH7125 Group and SH7124 Group RISC (Reduced Instruction Set Computer) microcomputer
include a Renesas Technology-original RISC CPU as its core, and the peripheral functions
required to configure a system.
Target Users: This manual was written for users who will be using the SH7125 Group and
SH7124 Group in the design of application systems. Target users are expected to
understand the fundamentals of electrical circuits, logical circuits, and
microcomputers.
Objective: This manual was written to explain the hardware functions and electrical
characteristics of the SH7125 Group and SH7124 Group to the target users.
Refer to the SH-1/SH-2/SH-DSP Software Manual for a detailed description of the
instruction set.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
• In order to understand the details of the CPU's functions
Read the SH-1/SH-2/SH-DSP Software Manual.
• In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 20,
List of Registers.
Examples: Register name: The following notation is used for cases when the same or a
similar function, e.g. serial communication interface, is
implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order: The MSB is on the left and the LSB is on the right.
Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx.
Signal notation: An overbar is added to a low-active signal: xxxx
Related Manuals: The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/
Rev. 3.00 Sep. 27, 2007 Page vi of xx
Page 7
SH7125 Group and SH7124 Group manuals:
Document Title Document No.
SH7125 Group, SH7124 Group Hardware Manual This manual
SH-1/SH-2/SH-DSP Software Manual REJ09B0171
User's manuals for development tools:
Document Title Document No.
TM
SuperH
Optimizing Linkage Editor Compiler Package V.9.00 User's Manual
SuperHTM RISC engine High-performance Embedded Workshop 3
User's Manual
SuperH RISC engine High-Performance Embedded Workshop 3 Tutorial REJ10B0023
RISC engine C/C++ Compiler, Assembler,
REJ10B0152
REJ10B0025
Application note:
Document Title Document No.
SuperH RISC engine C/C++ Compiler Package Application Note REJ05B0463
All trademarks and registered trademarks are the property of their respective owners.
Rev. 3.00 Sep. 27, 2007 Page vii of xx
Page 8
Rev. 3.00 Sep. 27, 2007 Page viii of xx
Page 9
Contents
Section 1 Overview................................................................................................1
1.1 Features of SH7125 and SH7124........................................................................................... 1
1.2 Block Diagram....................................................................................................................... 6
1.3 Pin Assignments .................................................................................................................... 7
1.4 Pin Functions ....................................................................................................................... 11
Section 2 CPU......................................................................................................17
2.1 Features................................................................................................................................ 17
2.2 Register Configuration......................................................................................................... 18
2.2.1 General Registers (Rn)............................................................................................ 19
2.2.2 Control Registers .................................................................................................... 19
2.2.3 System Registers..................................................................................................... 21
2.2.4 Initial Values of Registers....................................................................................... 21
2.3 Data Formats........................................................................................................................ 22
2.3.1 Register Data Format.............................................................................................. 22
2.3.2 Memory Data Formats............................................................................................ 22
2.3.3 Immediate Data Formats......................................................................................... 23
2.4 Features of Instructions........................................................................................................23
2.4.1 RISC Type .............................................................................................................. 23
2.4.2 Addressing Modes .................................................................................................. 26
2.4.3 Instruction Formats................................................................................................. 29
2.5 Instruction Set...................................................................................................................... 33
2.5.1 Instruction Set by Type........................................................................................... 33
2.5.2 Data Transfer Instructions ...................................................................................... 37
2.5.3 Arithmetic Operation Instructions .......................................................................... 39
2.5.4 Logic Operation Instructions .................................................................................. 41
2.5.5 Shift Instructions..................................................................................................... 42
2.5.6 Branch Instructions................................................................................................. 43
2.5.7 System Control Instructions.................................................................................... 44
2.6 Processing States.................................................................................................................. 46
Section 3 MCU Operating Modes .......................................................................49
3.1 Selection of Operating Modes.............................................................................................. 49
3.2 Input/Output Pins................................................................................................................. 50
3.3 Operating Modes.................................................................................................................. 50
3.3.1 Mode 3 (Single Chip Mode) ................................................................................... 50
Rev. 3.00 Sep. 27, 2007 Page ix of xx
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3.4 Address Map........................................................................................................................ 51
3.5 Initial State in This LSI........................................................................................................ 54
3.6 Note on Changing Operating Mode..................................................................................... 54
Section 4 Clock Pulse Generator (CPG) .............................................................55
4.1 Features................................................................................................................................ 55
4.2 Input/Output Pins................................................................................................................. 58
4.3 Clock Operating Mode......................................................................................................... 59
4.4 Register Descriptions...........................................................................................................61
4.4.1 Frequency Control Register (FRQCR) ................................................................... 61
4.4.2 Oscillation Stop Detection Control Register (OSCCR).......................................... 64
4.5 Changing Frequency............................................................................................................ 65
4.6 Oscillator.............................................................................................................................. 66
4.6.1 Connecting Crystal Resonator ................................................................................ 66
4.6.2 External Clock Input Method.................................................................................. 67
4.7 Function for Detecting Oscillator Stop ................................................................................ 68
4.8 Usage Notes ......................................................................................................................... 69
4.8.1 Note on Crystal Resonator...................................................................................... 69
4.8.2 Notes on Board Design........................................................................................... 69
Section 5 Exception Handling .............................................................................71
5.1 Overview.............................................................................................................................. 71
5.1.1 Types of Exception Handling and Priority ............................................................. 71
5.1.2 Exception Handling Operations.............................................................................. 72
5.1.3 Exception Handling Vector Table .......................................................................... 73
5.2 Resets................................................................................................................................... 75
5.2.1 Types of Resets....................................................................................................... 75
5.2.2 Power-On Reset...................................................................................................... 75
5.2.3 Manual Reset .......................................................................................................... 76
5.3 Address Errors ..................................................................................................................... 77
5.3.1 Address Error Sources ............................................................................................ 77
5.3.2 Address Error Exception Source............................................................................. 78
5.4 Interrupts.............................................................................................................................. 79
5.4.1 Interrupt Sources..................................................................................................... 79
5.4.2 Interrupt Priority ..................................................................................................... 80
5.4.3 Interrupt Exception Handling ................................................................................. 80
5.5 Exceptions Triggered by Instructions.................................................................................. 81
5.5.1 Types of Exceptions Triggered by Instructions ...................................................... 81
5.5.2 Trap Instructions..................................................................................................... 81
5.5.3 Illegal Slot Instructions........................................................................................... 82
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5.5.4 General Illegal Instructions..................................................................................... 82
5.6 Cases when Exceptions are Accepted.................................................................................. 83
5.7 Stack States after Exception Handling Ends........................................................................ 84
5.8 Usage Notes ......................................................................................................................... 86
5.8.1 Value of Stack Pointer (SP) .................................................................................... 86
5.8.2 Value of Vector Base Register (VBR).................................................................... 86
5.8.3 Address Errors Caused by Stacking for Address Error Exception Handling.......... 86
5.8.4 Notes on Slot Illegal Instruction Exception Handling ............................................ 87
Section 6 Interrupt Controller (INTC) .................................................................89
6.1 Features................................................................................................................................ 89
6.2 Input/Output Pins................................................................................................................. 91
6.3 Register Descriptions...........................................................................................................92
6.3.1 Interrupt Control Register 0 (ICR0)........................................................................ 93
6.3.2 IRQ Control Register (IRQCR) .............................................................................. 94
6.3.3 IRQ Status register (IRQSR) .................................................................................. 96
6.3.4 Interrupt Priority Registers A to F and H to M
(IPRA to IPRF and IPRH to IPRM) ....................................................................... 99
6.4 Interrupt Sources................................................................................................................ 102
6.4.1 External Interrupts ................................................................................................ 102
6.4.2 On-Chip Peripheral Module Interrupts ................................................................. 103
6.4.3 User Break Interrupt ............................................................................................. 103
6.5 Interrupt Exception Handling Vector Table....................................................................... 104
6.6 Interrupt Operation ............................................................................................................ 107
6.6.1 Interrupt Sequence................................................................................................ 107
6.6.2 Stack after Interrupt Exception Handling ............................................................. 110
6.7 Interrupt Response Time.................................................................................................... 110
6.8 Usage Note......................................................................................................................... 112
Section 7 User Break Controller (UBC) ............................................................113
7.1 Features.............................................................................................................................. 113
7.2 Register Descriptions......................................................................................................... 115
7.2.1 Break Address Register A (BARA)...................................................................... 116
7.2.2 Break Address Mask Register A (BAMRA)......................................................... 116
7.2.3 Break Bus Cycle Register A (BBRA)................................................................... 117
7.2.4 Break Data Register A (BDRA) ........................................................................... 119
7.2.5 Break Data Mask Register A (BDMRA) .............................................................. 120
7.2.6 Break Address Register B (BARB) ...................................................................... 121
7.2.7 Break Address Mask Register B (BAMRB)......................................................... 122
7.2.8 Break Data Register B (BDRB)............................................................................ 123
Rev. 3.00 Sep. 27, 2007 Page xi of xx
Page 12
7.2.9 Break Data Mask Register B (BDMRB)............................................................... 124
7.2.10 Break Bus Cycle Register B (BBRB) ................................................................... 125
7.2.11 Break Control Register (BRCR) ........................................................................... 127
7.2.12 Execution Times Break Register (BETR)............................................................. 131
7.2.13 Branch Source Register (BRSR)........................................................................... 132
7.2.14 Branch Destination Register (BRDR)................................................................... 133
7.3 Operation ........................................................................................................................... 134
7.3.1 Flow of the User Break Operation........................................................................ 134
7.3.2 Break on Instruction Fetch Cycle ......................................................................... 135
7.3.3 Break on Data Access Cycle................................................................................. 135
7.3.4 Sequential Break................................................................................................... 137
7.3.5 Value of Saved Program Counter ......................................................................... 137
7.3.6 PC Trace ............................................................................................................... 138
7.3.7 Usage Examples.................................................................................................... 139
7.4 Usage Notes ....................................................................................................................... 144
Section 8 Bus State Controller (BSC) ............................................................... 147
8.1 Features.............................................................................................................................. 147
8.2 Address Map...................................................................................................................... 147
8.3 Access to on-chip FLASH and on-chip RAM ................................................................... 147
8.4 Access to on-chip Peripheral I/O Register ......................................................................... 148
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2).....................................151
9.1 Features.............................................................................................................................. 151
9.2 Input/Output Pins............................................................................................................... 157
9.3 Register Descriptions......................................................................................................... 158
9.3.1 Timer Control Register (TCR).............................................................................. 162
9.3.2 Timer Mode Register (TMDR)............................................................................. 166
9.3.3 Timer I/O Control Register (TIOR)...................................................................... 169
9.3.4 Timer Compare Match Clear Register (TCNTCMPCLR).................................... 188
9.3.5 Timer Interrupt Enable Register (TIER)............................................................... 189
9.3.6 Timer Status Register (TSR)................................................................................. 194
9.3.7 Timer Buffer Operation Transfer Mode Register (TBTM)................................... 202
9.3.8 Timer Input Capture Control Register (TICCR)................................................... 203
9.3.9 Timer A/D Converter Start Request Control Register (TADCR)......................... 205
9.3.10 Timer A/D Converter Start Request Cycle Set Registers
(TADCORA_4 and TADCORB_4)...................................................................... 208
9.3.11 Timer A/D Converter Start Request Cycle Set Buffer Registers
(TADCOBRA_4 and TADCOBRB_4) ................................................................ 208
9.3.12 Timer Counter (TCNT)......................................................................................... 209
Rev. 3.00 Sep. 27, 2007 Page xii of xx
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9.3.13 Timer General Register (TGR) ............................................................................. 209
9.3.14 Timer Start Register (TSTR) ................................................................................ 210
9.3.15 Timer Synchronous Register (TSYR)................................................................... 212
9.3.16 Timer Counter Synchronous Start Register (TCSYSTR) ..................................... 214
9.3.17 Timer Read/Write Enable Register (TRWER) ..................................................... 216
9.3.18 Timer Output Master Enable Register (TOER) .................................................... 217
9.3.19 Timer Output Control Register 1 (TOCR1).......................................................... 218
9.3.20 Timer Output Control Register 2 (TOCR2).......................................................... 221
9.3.21 Timer Output Level Buffer Register (TOLBR) .................................................... 224
9.3.22 Timer Gate Control Register (TGCR) .................................................................. 225
9.3.23 Timer Subcounter (TCNTS) ................................................................................. 227
9.3.24 Timer Dead Time Data Register (TDDR)............................................................. 228
9.3.25 Timer Cycle Data Register (TCDR) ..................................................................... 228
9.3.26 Timer Cycle Buffer Register (TCBR)................................................................... 229
9.3.27 Timer Interrupt Skipping Set Register (TITCR)................................................... 229
9.3.28 Timer Interrupt Skipping Counter (TITCNT)....................................................... 231
9.3.29 Timer Buffer Transfer Set Register (TBTER) ...................................................... 232
9.3.30 Timer Dead Time Enable Register (TDER).......................................................... 234
9.3.31 Timer Waveform Control Register (TWCR) ........................................................ 235
9.3.32 Bus Master Interface............................................................................................. 236
9.4 Operation ........................................................................................................................... 237
9.4.1 Basic Functions..................................................................................................... 237
9.4.2 Synchronous Operation......................................................................................... 243
9.4.3 Buffer Operation................................................................................................... 245
9.4.4 Cascaded Operation .............................................................................................. 249
9.4.5 PWM Modes......................................................................................................... 254
9.4.6 Phase Counting Mode........................................................................................... 259
9.4.7 Reset-Synchronized PWM Mode ......................................................................... 266
9.4.8 Complementary PWM Mode................................................................................ 269
9.4.9 A/D Converter Start Request Delaying Function.................................................. 308
9.4.10 External Pulse Width Measurement...................................................................... 312
9.4.11 Dead Time Compensation .................................................................................... 313
9.4.12 TCNT Capture at Crest and/or Trough in Complementary PWM Operation ....... 315
9.5 Interrupt Sources................................................................................................................ 316
9.5.1 Interrupt Sources and Priorities ............................................................................ 316
9.5.2 A/D Converter Activation..................................................................................... 319
9.6 Operation Timing............................................................................................................... 321
9.6.1 Input/Output Timing............................................................................................. 321
9.6.2 Interrupt Signal Timing ........................................................................................ 328
9.7 Usage Notes ....................................................................................................................... 332
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9.7.1 Module Standby Mode Setting ............................................................................. 332
9.7.2 Input Clock Restrictions ....................................................................................... 332
9.7.3 Caution on Period Setting..................................................................................... 333
9.7.4 Contention between TCNT Write and Clear Operations ...................................... 333
9.7.5 Contention between TCNT Write and Increment Operations............................... 334
9.7.6 Contention between TGR Write and Compare Match.......................................... 335
9.7.7 Contention between Buffer Register Write and Compare Match ......................... 336
9.7.8 Contention between Buffer Register Write and TCNT Clear ............................... 337
9.7.9 Contention between TGR Read and Input Capture............................................... 338
9.7.10 Contention between TGR Write and Input Capture.............................................. 339
9.7.11 Contention between Buffer Register Write and Input Capture............................. 340
9.7.12 TCNT_2 Write and Overflow/Underflow Contention in Cascade Connection .... 340
9.7.13 Counter Value during Complementary PWM Mode Stop.................................... 342
9.7.14 Buffer Operation Setting in Complementary PWM Mode ................................... 342
9.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag.................. 343
9.7.16 Overflow Flags in Reset Synchronous PWM Mode ............................................. 344
9.7.17 Contention between Overflow/Underflow and Counter Clearing......................... 345
9.7.18 Contention between TCNT Write and Overflow/Underflow................................ 346
9.7.19 Cautions on Transition from Normal Operation or PWM Mode 1 to
Reset-Synchronized PWM Mode ......................................................................... 346
9.7.20 Output Level in Complementary PWM Mode and
Reset-Synchronized PWM Mode ......................................................................... 347
9.7.21 Interrupts in Module Standby Mode..................................................................... 347
9.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection............ 347
9.8 MTU2 Output Pin Initialization......................................................................................... 348
9.8.1 Operating Modes .................................................................................................. 348
9.8.2 Reset Start Operation............................................................................................ 348
9.8.3 Operation in Case of Re-Setting Due to Error During Operation, etc. ................. 349
9.8.4 Overview of Initialization Procedures and Mode Transitions in Case of
Error during Operation, etc................................................................................... 350
Section 10 Port Output Enable (POE) ...............................................................381
10.1 Features.............................................................................................................................. 381
10.2 Input/Output Pins............................................................................................................... 383
10.3 Register Descriptions......................................................................................................... 384
10.3.1 Input Level Control/Status Register 1 (ICSR1) .................................................... 385
10.3.2 Output Level Control/Status Register 1 (OCSR1) ................................................ 388
10.3.3 Input Level Control/Status Register 3 (ICSR3) .................................................... 389
10.3.4 Software Port Output Enable Register (SPOER) .................................................. 391
10.3.5 Port Output Enable Control Register 1 (POECR1)............................................... 393
Rev. 3.00 Sep. 27, 2007 Page xiv of xx
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10.3.6 Port Output Enable Control Register 2 (POECR2)............................................... 394
10.4 Operation ........................................................................................................................... 396
10.4.1 Input Level Detection Operation .......................................................................... 396
10.4.2 Output-Level Compare Operation ........................................................................ 398
10.4.3 Release from High-Impedance State .................................................................... 398
10.5 Interrupts............................................................................................................................ 399
10.6 Usage Note......................................................................................................................... 400
10.6.1 Pin State when a Power-On Reset is Issued from the Watchdog Timer............... 400
Section 11 Watchdog Timer (WDT) .................................................................401
11.1 Features.............................................................................................................................. 401
11.2 Input/Output Pin for WDT................................................................................................. 403
11.3 Register Descriptions......................................................................................................... 404
11.3.1 Watchdog Timer Counter (WTCNT).................................................................... 404
11.3.2 Watchdog Timer Control/Status Register (WTCSR)............................................ 405
11.3.3 Notes on Register Access ..................................................................................... 407
11.4 Operation ........................................................................................................................... 408
11.4.1 Canceling Software Standbys ............................................................................... 408
11.4.2 Using Watchdog Timer Mode .............................................................................. 408
11.4.3 Using Interval Timer Mode .................................................................................. 409
11.5 Usage Note......................................................................................................................... 410
Section 12 Serial Communication Interface (SCI) ............................................411
12.1 Features.............................................................................................................................. 411
12.2 Input/Output Pins............................................................................................................... 413
12.3 Register Descriptions......................................................................................................... 414
12.3.1 Receive Shift Register (SCRSR) .......................................................................... 415
12.3.2 Receive Data Register (SCRDR) .......................................................................... 415
12.3.3 Transmit Shift Register (SCTSR) ......................................................................... 415
12.3.4 Transmit Data Register (SCTDR)......................................................................... 416
12.3.5 Serial Mode Register (SCSMR)............................................................................ 416
12.3.6 Serial Control Register (SCSCR).......................................................................... 419
12.3.7 Serial Status Register (SCSSR) ............................................................................ 422
12.3.8 Serial Port Register (SCSPTR) ............................................................................. 428
12.3.9 Serial Direction Control Register (SCSDCR)....................................................... 430
12.3.10 Bit Rate Register (SCBRR) .................................................................................. 431
12.4 Operation ........................................................................................................................... 442
12.4.1 Overview .............................................................................................................. 442
12.4.2 Operation in Asynchronous Mode........................................................................ 444
12.4.3 Clock Synchronous Mode (Channel 1 in the SH7124 is not Available)............... 454
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12.4.4 Multiprocessor Communication Function ............................................................ 463
12.4.5 Multiprocessor Serial Data Transmission ............................................................. 465
12.4.6 Multiprocessor Serial Data Reception .................................................................. 466
12.5 SCI Interrupt Sources......................................................................................................... 469
12.6 Serial Port Register (SCSPTR) and SCI Pins .................................................................... 470
12.7 Usage Notes ....................................................................................................................... 471
12.7.1 SCTDR Writing and TDRE Flag .......................................................................... 471
12.7.2 Multiple Receive Error Occurrence ...................................................................... 471
12.7.3 Break Detection and Processing ........................................................................... 472
12.7.4 Sending a Break Signal......................................................................................... 472
12.7.5 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode)...... 472
12.7.6 Note on Using External Clock in Clock Synchronous Mode................................ 474
12.7.7 Module Standby Mode Setting ............................................................................. 474
Section 13 A/D Converter (ADC) ..................................................................... 475
13.1 Features.............................................................................................................................. 475
13.2 Input/Output Pins............................................................................................................... 477
13.3 Register Descriptions......................................................................................................... 478
13.3.1 A/D Data Registers 0 to 7 (ADDR0 to ADDR7).................................................. 479
13.3.2 A/D Control/Status Registers_0 and _1 (ADCSR_0 and ADCSR_1) .................. 479
13.3.3 A/D Control Registers_0 and _1 (ADCR_0 and ADCR_1) ................................. 482
13.3.4 A/D Trigger Select Register_0 (ADTSR_0) ......................................................... 484
13.4 Operation ........................................................................................................................... 488
13.4.1 Single Mode.......................................................................................................... 488
13.4.2 Continuous Scan Mode......................................................................................... 488
13.4.3 Single-Cycle Scan Mode ...................................................................................... 489
13.4.4 Input Sampling and A/D Conversion Time .......................................................... 489
13.4.5 A/D Converter Activation by MTU2.................................................................... 492
13.4.6 External Trigger Input Timing.............................................................................. 492
13.4.7 2-Channel Scanning.............................................................................................. 493
13.5 Interrupt Sources................................................................................................................ 494
13.6 Definitions of A/D Conversion Accuracy.......................................................................... 495
13.7 Usage Notes ....................................................................................................................... 498
13.7.1 Module Standby Mode Setting ............................................................................. 498
13.7.2 Permissible Signal Source Impedance .................................................................. 498
13.7.3 Influences on Absolute Accuracy ......................................................................... 498
13.7.4 Range of Analog Power Supply and Other Pin Settings....................................... 499
13.7.5 Notes on Board Design ......................................................................................... 499
13.7.6 Notes on Noise Countermeasures ......................................................................... 500
Rev. 3.00 Sep. 27, 2007 Page xvi of xx
Page 17
Section 14 Compare Match Timer (CMT) ........................................................501
14.1 Features.............................................................................................................................. 501
14.2 Register Descriptions......................................................................................................... 502
14.2.1 Compare Match Timer Start Register (CMSTR) .................................................. 503
14.2.2 Compare Match Timer Control/Status Register (CMCSR) .................................. 503
14.2.3 Compare Match Counter (CMCNT)..................................................................... 505
14.2.4 Compare Match Constant Register (CMCOR) ..................................................... 505
14.3 Operation ........................................................................................................................... 506
14.3.1 Interval Count Operation ...................................................................................... 506
14.3.2 CMCNT Count Timing......................................................................................... 506
14.4 Interrupts............................................................................................................................ 507
14.4.1 CMT Interrupt Sources ......................................................................................... 507
14.4.2 Timing of Setting Compare Match Flag ............................................................... 507
14.4.3 Timing of Clearing Compare Match Flag............................................................. 507
14.5 Usage Notes ....................................................................................................................... 508
14.5.1 Module Standby Mode Setting ............................................................................. 508
14.5.2 Conflict between Write and Compare-Match Processes of CMCNT ................... 508
14.5.3 Conflict between Word-Write and Count-Up Processes of CMCNT ................... 509
14.5.4 Conflict between Byte-Write and Count-Up Processes of CMCNT..................... 510
14.5.5 Compare Match between CMCNT and CMCOR ................................................. 510
Section 15 Pin Function Controller (PFC).........................................................511
15.1 Register Descriptions......................................................................................................... 519
15.1.1 Port A I/O Register L (PAIORL).......................................................................... 520
15.1.2 Port A Control Registers L1 to L4 (PACRL1 to PACRL4).................................. 520
15.1.3 Port B I/O Registers L and H (PBIORL and PBIORH)........................................ 531
15.1.4 Port B Control Registers L1, L2, and H1 (PBCRL1, PBCRL2, and PBCRH1) ... 532
15.1.5 Port E I/O Register L (PEIORL)........................................................................... 537
15.1.6 Port E Control Registers L1 to L4 (PECRL1 to PECRL4)................................... 537
15.1.7 IRQOUT Function Control Register (IFCR) ........................................................ 547
15.2 Usage Notes ....................................................................................................................... 548
Section 16 I/O Ports...........................................................................................549
16.1 Port A................................................................................................................................. 550
16.1.1 Register Descriptions............................................................................................ 551
16.1.2 Port A Data Register L (PADRL) ......................................................................... 551
16.1.3 Port A Port Register L (PAPRL) .......................................................................... 555
16.2 Port B................................................................................................................................. 557
16.2.1 Register Descriptions............................................................................................ 557
16.2.2 Port B Data Registers H and L (PBDRH and PBDRL) ........................................ 558
Rev. 3.00 Sep. 27, 2007 Page xvii of xx
Page 18
16.2.3 Port B Port Registers H and L (PBPRH and PBPRL) .......................................... 561
16.3 Port E ................................................................................................................................. 564
16.3.1 Register Descriptions............................................................................................ 566
16.3.2 Port E Data Register L (PEDRL).......................................................................... 566
16.3.3 Port E Port Register L (PEPRL) ........................................................................... 569
16.4 Port F ................................................................................................................................. 571
16.4.1 Register Descriptions............................................................................................ 571
16.4.2 Port F Data Register L (PFDRL) .......................................................................... 572
Section 17 Flash Memory.................................................................................. 573
17.1 Features.............................................................................................................................. 573
17.2 Overview............................................................................................................................ 575
17.2.1 Block Diagram...................................................................................................... 575
17.2.2 Operating Mode .................................................................................................... 576
17.2.3 Mode Comparison ................................................................................................ 577
17.2.4 Flash Memory Configuration................................................................................ 578
17.2.5 Block Division ...................................................................................................... 578
17.2.6 Programming/Erasing Interface ............................................................................ 579
17.3 Input/Output Pins............................................................................................................... 581
17.4 Register Descriptions......................................................................................................... 581
17.4.1 Registers ............................................................................................................... 581
17.4.2 Programming/Erasing Interface Registers ............................................................ 584
17.4.3 Programming/Erasing Interface Parameters ......................................................... 590
17.5 On-Board Programming Mode .......................................................................................... 605
17.5.1 Boot Mode ............................................................................................................ 605
17.5.2 User Program Mode (Only in On-Chip 128-Kbyte and
64-Kbyte ROM Version) ...................................................................................... 609
17.6 Protection........................................................................................................................... 618
17.6.1 Hardware Protection ............................................................................................. 618
17.6.2 Software Protection............................................................................................... 619
17.6.3 Error Protection .................................................................................................... 619
17.7 Usage Notes ....................................................................................................................... 621
17.7.1 Interrupts during Programming/Erasing ............................................................... 621
17.7.2 Other Notes ........................................................................................................... 623
17.8 Supplementary Information ............................................................................................... 625
17.8.1 Specifications of the Standard Serial Communications Interface
in Boot Mode ........................................................................................................ 625
17.8.2 Areas for Storage of the Procedural Program and Data for Programming............ 652
17.9 Off-Board Programming Mode.......................................................................................... 656
Rev. 3.00 Sep. 27, 2007 Page xviii of xx
Page 19
Section 18 RAM ................................................................................................657
18.1 Usage Notes ....................................................................................................................... 658
18.1.1 Module Standby Mode Setting ............................................................................. 658
18.1.2 Address Error........................................................................................................ 658
18.1.3 Initial Values in RAM........................................................................................... 658
Section 19 Power-Down Modes ........................................................................659
19.1 Features.............................................................................................................................. 659
19.1.1 Types of Power-Down Modes .............................................................................. 659
19.2 Input/Output Pins............................................................................................................... 661
19.3 Register Descriptions......................................................................................................... 661
19.3.1 Standby Control Register 1 (STBCR1)................................................................. 662
19.3.2 Standby Control Register 2 (STBCR2)................................................................. 663
19.3.3 Standby Control Register 3 (STBCR3)................................................................. 664
19.3.4 Standby Control Register 4 (STBCR4)................................................................. 665
19.3.5 Standby Control Register 5 (STBCR5)................................................................. 666
19.3.6 Standby Control Register 6 (STBCR6)................................................................. 667
19.3.7 RAM Control Register (RAMCR)........................................................................ 668
19.4 Sleep Mode ........................................................................................................................ 669
19.4.1 Transition to Sleep Mode...................................................................................... 669
19.4.2 Canceling Sleep Mode .......................................................................................... 669
19.5 Software Standby Mode..................................................................................................... 670
19.5.1 Transition to Software Standby Mode .................................................................. 670
19.5.2 Canceling Software Standby Mode....................................................................... 671
19.6 Module Standby Mode....................................................................................................... 672
19.6.1 Transition to Module Standby Mode .................................................................... 672
19.6.2 Canceling Module Standby Function.................................................................... 672
19.7 Usage Note......................................................................................................................... 672
19.7.1 Current Consumption while Waiting for Oscillation to be Stabilized .................. 672
19.7.2 Executing the SLEEP Instruction ......................................................................... 672
Section 20 List of Registers ...............................................................................673
20.1 Register Address Table (In the Order from Lower Addresses).......................................... 674
20.2 Register Bit List................................................................................................................. 682
20.3 Register States in Each Operating Mode ........................................................................... 696
Section 21 Electrical Characteristics .................................................................705
21.1 Absolute Maximum Ratings .............................................................................................. 705
21.2 DC Characteristics ............................................................................................................. 706
21.3 AC Characteristics ............................................................................................................. 709
Rev. 3.00 Sep. 27, 2007 Page xix of xx
Page 20
21.3.1 Clock Timing ........................................................................................................ 710
21.3.2 Control Signal Timing .......................................................................................... 712
21.3.3 Multi Function Timer Pulse Unit 2 (MTU2) Timing............................................ 715
21.3.4 I/O Port Timing..................................................................................................... 717
21.3.5 Watchdog Timer (WDT) Timing.......................................................................... 718
21.3.6 Serial Communication Interface (SCI) Timing..................................................... 719
21.3.7 Port Output Enable (POE) Timing........................................................................ 721
21.3.8 A/D Converter Timing.......................................................................................... 722
21.3.9 Conditions for Testing AC Characteristics ........................................................... 723
21.4 A/D Converter Characteristics........................................................................................... 724
21.5 Flash Memory Characteristics ........................................................................................... 725
21.6 Usage Note......................................................................................................................... 726
21.6.1 Notes on Connecting VCL Capacitor...................................................................... 726
Appendix .........................................................................................................727
A. Pin States ........................................................................................................................... 727
B. Product Code Lineup ......................................................................................................... 731
C. Package Dimensions .......................................................................................................... 732
Main Revisions and Additions in this Edition..................................................... 737
Index .........................................................................................................753
Rev. 3.00 Sep. 27, 2007 Page xx of xx
Page 21
Section 1 Overview
Section 1 Overview
1.1 Features of SH7125 and SH7124
This LSI is a single-chip RISC (Reduced Instruction Set Computer) microcomputer that integrates
a Renesas Technology original RISC CPU core with peripheral functions required for system
configuration.
The CPU in this LSI has a RISC-type instruction set. Most instructions can be executed in one
state (one system clock cycle), which greatly improves instruction execution speed. In addition,
the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become
possible to assemble low-cost, high-performance, and high-functioning systems, even for
applications that were previously impossible with microcomputers, such as real-time control,
which demands high speeds.
In addition, this LSI includes on-chip peripheral functions necessary for system configuration,
such as a ROM, a RAM, timers, a serial communication interface (SCI), an A/D converter, an
interrupt controller (INTC), and I/O ports.
TM
The version of the on-chip ROM is F-ZTAT
flash memory. The flash memory can be programmed with a programmer that supports
programming of this LSI, and can also be programmed and erased by software. This enables LSI
chip to be re-programmed at a user-site while mounted on a board.
(Flexible Zero Turn Around Time)* that includes
The features of this LSI are listed in table 1.1.
TM
Note: * F-ZTAT
Rev. 3.00 Sep. 27, 2007 Page 1 of 758
REJ09B0243-0300
is a trademark of Renesas Technology Corp.
Page 22
Section 1 Overview
Table 1.1 Features
Items Specification
CPU
Operating modes
User break controller
(UBC)
On-chip ROM
On-chip RAM
• Central processing unit with an internal 32-bit RISC (Reduced
Instruction Set Computer) architecture
• Instruction length: 16-bit fixed length for improved code efficiency
• Load-store architecture (basic operations are executed between
registers)
• Sixteen 32-bit general registers
• Five-stage pipeline
• On-chip multiplier: Multiplication operations (32 bits × 32 bits → 64 bits)
executed in two to five cycles
• C language-oriented 62 basic instructions
Note: Some specifications on slot illegal instruction exception handling
in this LSI differ from those of the conventional SH-2. For details,
see section 5.8.4, Notes on Slot Illegal Instruction Exception
Handling.
• Operating modes
Single chip mode
• Operating states
Program execution state
Exception handling state
• Power-down modes
Sleep mode
Software standby mode
Module standby mode
• Addresses, data values, type of access, and data size can all be set as
break conditions
• Supports a sequential break function
• Two break channels
• 128 kbytes (SH71253, SH71243)
• 64 kbytes (SH71252, SH71242)
• 32 kbytes (SH71241)
• 8 kbytes
Rev. 3.00 Sep. 27, 2007 Page 2 of 758
REJ09B0243-0300
Page 23
Items Specification
Interrupt controller
(INTC)
• External interrupt pins
SH7125: Five pins (NMI and IRQ3 to IRQ0)
SH7124: Four pins (NMI and IRQ3 to IRQ1)
• On-chip peripheral interrupts: Priority level set for each module
• Vector addresses: A vector address for each interrupt source
User debugging
• E10A emulator support
interface (H-UDI)
Clock pulse
generator (CPG)
• Clock mode: Input clock can be selected from external input or crystal
resonator
• Four types of clocks generated:
CPU clock: Maximum 50 MHz
Bus clock: Maximum 40 MHz
Peripheral clock: Maximum 40 MHz
MTU2 clock: Maximum 40 MHz
Watchdog timer
(WDT)
• On-chip one-channel watchdog timer
• Interrupt generation is supported.
Section 1 Overview
Rev. 3.00 Sep. 27, 2007 Page 3 of 758
REJ09B0243-0300
Page 24
Section 1 Overview
Items Specification
Multi-function timer
pulse unit 2 (MTU2)
• Maximum 16 lines of pulse input/output and three lines of pulse input
based on six channels of 16-bit timers (SH7125)
• Maximum 12 lines of pulse input/output and three lines of pulse input
based on six channels of 16-bit timers (SH7124)
• 21 output compare and input capture registers
• A total of 21 independent comparators
• Selection of eight counter input clocks
• Input capture function
• Pulse output modes
Toggle, PWM, complementary PWM, and reset-synchronized PWM
modes
• Synchronization of multiple counters
• Complementary PWM output mode
Non-overlapping waveforms output for 6-phase inverter control
Automatic dead time setting
0% to 100% PWM duty cycle specifiable
Output suppression
A/D conversion delaying function
Dead time compensation
Interrupt skipping at crest or trough
• Reset-synchronized PWM mode
Three-phase PWM waveforms in positive and negative phases can be
output with a required duty cycle
• Phase counting mode
Two-phase encoder pulse counting available
Port output enable
(POE)
Compare match timer
(CMT)
• High-impedance control of waveform output pins and channel 0 pins in
MTU2
• 16-bit counters
• Compare match interrupts can be generated
• Two channels
Serial communication
interface (SCI)
• Clock synchronous or asynchronous mode
• Three channels
Rev. 3.00 Sep. 27, 2007 Page 4 of 758
REJ09B0243-0300
Page 25
Items Specification
A/D converter (ADC)
• 10 bits × 8 channels
• Conversion request by external triggers or MTU2
• Two sample-and-hold function units (two channels can be sampled
simultaneously)
I/O ports
• 37 general input/output pins and eight general input pins (SH7125)
• 23 general input/output pins and eight general input pins (SH7124)
• Input or output can be selected for each bit
Packages
• QFP-64 (0.8 pitch) (SH7125)
• LQFP-64 (0.5 pitch) (SH7125)
• LQFP-48 (0.65 pitch) (SH7124)
• VQFN-64 (0.4 pitch) (SH7125 and SH7124)
• VQFN-52 (0.4 pitch) (SH7124)
Power supply voltage
• Vcc: 4.0 to 5.5 V
• AVcc: 4.0 to 5.5 V
Section 1 Overview
Rev. 3.00 Sep. 27, 2007 Page 5 of 758
REJ09B0243-0300
Page 26
Section 1 Overview
1.2 Block Diagram
The block diagram of this LSI is shown in figure 1.1.
Internal bus
controller
I/O
port
(PFC)
[Legend]
ROM: On-chip ROM
RAM: On-chip RAM
UBC: User break controller
H-UDI: User debugging interface
INTC: Interrupt controller
CPG: Clock pulse generator
WDT: Watchdog timer
CPU: Central processing unit
SH2
CPU
Peripheral bus
INTC WDT CPG
H-UDI MTU2 POESCI CMT ADC
UBC
L bus (Iφ)
RAMROM
I bus (Bφ)
controller
Peripheral bus (Pφ)
Power-
down
mode
control
PFC: Pin function controller
MTU2: Multi-function timer pulse unit 2
POE: Port output enable
SCI: Serial communication interface
CMT: Compare match timer
ADC: A/D converter
Figure 1.1 Block Diagram
Rev. 3.00 Sep. 27, 2007 Page 6 of 758
REJ09B0243-0300
Page 27
1.3 Pin Assignments
K
8
Section 1 Overview
PB3/IRQ1/POE1/TIC5V
PB2/IRQ0/POE0
PB1/TIC5W
AV
PF7/AN7
PF6/AN6
PF5/AN5
PF4/AN4
PF3/AN3
PF2/AN2
PF1/AN1
PF0/AN0
AV
PB16/POE3
PE15/TIOC4D/IRQOUT
PE14/TIOC4C
PB5/IRQ3/TIC5U
PLLVSSMD1
FWE/ASEBRK/ASEBRKA
NMI
ASEMD0
EXTAL
XTAL
WDTOVF
RES
PA0/POE0/RXD0
VCLPA1/POE1/TXD0
48 4746 4544 4342 4140 39 38 37 36 35 34 33
49
50
51
52
SS
53
54
55
56
57
58
QFP-64
LQFP-64
(Top view)
59
60
61
CC
62
63
64
SS
VCCPA2/IRQ0/SCK0
V
32
PA3/IRQ1/RXD1/TRST
PA4/IRQ2/TXD1/TMS
31
PA5/IRQ3/SCK1
30
PA6/TCLKA
29
PA7/TCLKB/SCK2/TCK
28
PA8/TCLKC/RXD2/TDI
27
PA9/TCLKD/TXD2/TDO/POE
26
PA10/RXD0
25
V
SS
24
PA11/TXD0/ADTRG
23
V
CC
22
PA12/SCK0
21
PA13/SCK1
20
PA14/RXD1
19
PA15/TXD1
18
PE0/TIOC0A
17
12345678910111213141516
CC
V
PE12/TIOC4A
PE11/TIOC3D
PE13/TIOC4B/MRES
V
V
PE9/TIOC3B
PE10/TIOC3C
PE8/TIOC3A
PE7/TIOC2B
PE5/TIOC1B/TXD1
PE6/TIOC2A/SCK1
PE2/TIOC0C/TXD0
PE4/TIOC1A/RXD1
PE3/TIOC0D/SCK0
PE1/TIOC0B/RXD0
CL
SS
Pins for the system development tool.
When these pins are used for an on-chip
debugger, they are not available.
Figure 1.2 (1) Pin Assignments of SH7125
Rev. 3.00 Sep. 27, 2007 Page 7 of 758
REJ09B0243-0300
Page 28
Section 1 Overview
K
8
PB3/IRQ1/POE1/TIC5V
PB2/IRQ0/POE0
PB1/TIC5W
AV
PF7/AN7
PF6/AN6
PF5/AN5
PF4/AN4
PF3/AN3
PF2/AN2
PF1/AN1
PF0/AN0
AV
PB16/POE3
PB15/TIOC4D/IRQOUT
PE14/TIOC4C
PB5/IRQ3/TIC5U
PLLVSSMD1
FWE/ASEBRK/ASEBRKA
NMI
ASEMD0
EXTAL
XTAL
WDTOVF
RES
PA0/POE0/RXD0
VCLPA1/POE1/TXD0
48 4746 4544 4342 4140 39 38 37 36 35 34 33
VCCPA2/IRQ0/SCK0
49
50
51
52
SS
53
54
55
56
57
VQFN-64
(Top view)
58
59
60
61
CC
62
63
64
12345678910111213141516
CC
V
PE12/TIOC4A
PE11/TIOC3D
PE13/TIOC4B/MRES
V
V
PE9/TIOC3B
PE10/TIOC3C
PE8/TIOC3A
PE7/TIOC2B
PE5/TIOC1B/TXD1
PE6/TIOC2A/SCK1
PE4/TIOC1A/RXD1
PE3/TIOC0D/SCK0
CL
SS
Figure 1.2 (2) Pin Assignments of SH7125
SS
V
32
PA3/IRQ1/RXD1/TRST
PA4/IRQ2/TXD1/TMS
31
PA5/IRQ3/SCK1
30
PA6/TCLKA
29
PA7/TCLKB/SCK2/TCK
28
PA8/TCLKC/RXD2/TDI
27
PA9/TCLKD/TXD2/TDO/POE
26
PA10/RXD0
25
V
SS
24
PA11/TXD0/ADTRG
23
V
CC
22
PA12/SCK0
21
PA13/SCK1
20
PA14/RXD1
19
PA15/TXD1
18
PE0/TIOC0A
17
PE2/TIOC0C/TXD0
PE1/TIOC0B/RXD0
Rev. 3.00 Sep. 27, 2007 Page 8 of 758
REJ09B0243-0300
Page 29
Section 1 Overview
K
8
PB3/IRQ1/POE1/TIC5V
PB1/TIC5W
AV
PF7/AN7
PF6/AN6
PF5/AN5
PF4/AN4
PF3/AN3
PF2/AN2
PF1/AN1
PF0/AN0
AV
PB5/IRQ3/TIC5U
PLLVSSMD1
FWE/ASEBRK/ASEBRKA
NMI
ASEMD0
EXTAL
XTAL
36 35 34 33 32 31 30 29 28
37
38
39
SS
40
41
42
43
LQFP-48
(Top view)
44
45
46
47
48
CC
123456789101112
CL
SS
CC
V
PE14/TIOC4C
PE13/TIOC4B/MRES
PE15/TIOC4D/IRQOUT
V
V
PE12/TIOC4A
PE11/TIOC3D
CL
WDTOVF
RES
PA0/POE0/RXD0
V
27 26
25
24
23
22
21
20
19
18
17
16
15
14
13
PE9/TIOC3B
PE8/TIOC3A
PE10/TIOC3C
PE3/TIOC0D/SCK0
PA1/POE1/TXD0
PA3/IRQ1/RXD1/TRST
PA4/IRQ2/TXD1/TMS
PA6/TCLKA
PA7/TCLKB/SCK2/TCK
V
SS
PA8/TCLKC/RXD2/TDI
V
CC
PA9/TCLKD/TXD2/TDO/POE
PE0/TIOC0A
PE1/TIOC0B/RXD0
PE2/TIOC0C/TXD0
Pins for the system development tool.
When these pins are used for an on-chip
debugger, they are not available.
Figure 1.3 (1) Pin Assignments of SH7124
Rev. 3.00 Sep. 27, 2007 Page 9 of 758
REJ09B0243-0300
Page 30
Section 1 Overview
K
8
PB3/IRQ1/POE1/TIC5V
PB1/TIC5W
AVss
PF7/AN7
PF6/AN6
PF5/AN5
PF4/AN4
PF3/AN3
PF2/AN2
PF1/AN1
PF0/AN0
AVcc
NC
PB5/IRQ3/TIC5U
VSSPLLVSSMD1
FWE/ASEBRK/ASEBRKA
NMI
39 3837 3635 3433 3231 30 29 28 27
ASEMD0
40
41
42
43
44
45
46
47
VQFN-52
(Top view)
48
49
50
51
52
EXTAL
XTAL
WDTOVF
RES
PA0/POE0/TXD0
CL
V
26
PA1/POE1/TXD0
25
PA3/IRQ1/RXD1/TRST
24
PA4/IRQ2/TXD1/TMS
23
PA6/TCLKA
22
PA7/TCLKB/SCK2/TCK
21
V
SS
20
V
SS
19
PA8/TCLKC/RXD2/TDI
18
V
CC
17
PA9/TCLKD/TXD2/TDO/POE
16
PE0/TIOC0A
15
PE1/TIOC0B/RXD0
14
PE2/TIOC0C/TXD0
12345678910111213
CL
SS
PE14/TIOC4C
PE13/TIOC4B/MRES
PE15/TIOC4D/IRQOUT
CC
V
V
PE12/TIOC4A
V
PE9/TIOC3B
PE11/TIOC3D
NC
PE8/TIOC3A
PE10/TIOC3C
PE3/TIOC0D/SCK0
Figure 1.3 (2) Pin Assignments of SH7124
Rev. 3.00 Sep. 27, 2007 Page 10 of 758
REJ09B0243-0300
Page 31
1.4 Pin Functions
Table 1.2 summarizes the pin functions.
Table 1.2 Pin F unctions
Classification Symbol I/O Name Function
Power supply
Clock
Operating mode
control
Vcc I Power supply Power supply pin
Connect all Vcc pins to the system.
There will be no operation if any pins
are open.
Vss I Ground Ground pin
Connect all Vss pins to the system
power supply (0V). There will be no
operation if any pins are open.
VCL O Power supply for
internal powerdown
PLLVss I PLL ground Ground pin for the on-chip PLL
EXTAL I External clock Connected to a crystal resonator.
XTAL O Crystal Connected to a crystal resonator.
MD1 I Mode set Sets the operating mode. Do not
FWE I Flash memory
write enable
External capacitance pins for internal
power-down power supply
Connect these pins to Vss via a 0.1
to 0.47 µF capacitor (placed close to
the pins).
oscillator
An external clock signal may also be
input to the EXTAL pin.
change values on this pin during
operation.
Pin for flash memory
Flash memory can be protected
against programming or erasure
through this pin.
Section 1 Overview
Rev. 3.00 Sep. 27, 2007 Page 11 of 758
REJ09B0243-0300
Page 32
Section 1 Overview
Classification Symbol I/O Name Function
System control
RES I Power-on reset When low, this LSI enters the power-
on reset state.
MRES I Manual reset When low, this LSI enters the
manual reset state.
WDTOVF O Watchdog timer
overflow
Output signal for the watchdog timer
overflow
If this pin needs to be pulled down,
use the resistor larger than
1 MΩ to pull this pin down.
Interrupts
NMI I Non-maskable
interrupt
Non-maskable interrupt request pin
Fix to high or low level when not in
use.
IRQ3 to IRQ0
(SH7125)
IRQ3 to IRQ1
(SH7124)
I Interrupt requests
3 to 0
Maskable interrupt request pins
Selectable as level input or edge
input. The rising edge, falling edge,
and both edges are selectable as
edges.
IRQOUT O Interrupt request
output
Shows that an interrupt cause has
occurred. The interrupt cause can be
recognized even in the bus release
state.
Multi function timerpulse unit 2 (MTU2)
TCLKA,
TCLKB,
TCLKC,
I MTU2 timer clock
input
External clock input pins for the timer
TCLKD
TIOC0A,
TIOC0B,
TIOC0C,
TIOC0D
TIOC1A,
TIOC1B
(only in
SH7125)
TIOC2A,
TIOC2B
(only in
SH7125)
I/O MTU2 input
capture/output
compare
(channel 0)
I/O MTU2 input
capture/output
compare
(channel 1)
I/O MTU2 input
capture/output
compare
(channel 2)
The TGRA_0 to TGRD_0 input
capture input/output compare
output/PWM output pins
The TGRA_1 to TGRB_1 input
capture input/output compare
output/PWM output pins
The TGRA_2 to TGRB_2 input
capture input/output compare
output/PWM output pins
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Classification Symbol I/O Name Function
Multi function timerpulse unit 2 (MTU2)
Port output enable
(POE)
TIOC3A,
TIOC3B,
TIOC3C,
TIOC3D
TIOC4A,
TIOC4B,
TIOC4C,
TIOC4D
TIC5U,
TIC5V,
TIC5W
POE8, POE3,
POE1, POE0
(SH7125)
POE8, POE1,
POE0
(SH7124)
I/O MTU2 input
capture/output
compare
(channel 3)
I/O MTU2 input
capture/output
compare
(channel 4)
I MTU2 input
capture
(channel 5)
I Port output
enable
The TGRA_3 to TGRD_3 input
capture input/output compare
output/PWM output pins
The TGRA_4 to TGRD_4 input
capture input/output compare
output/PWM output pins
The TGRU_5, TGRV_5, and
TGRW_5 input capture input pins
Request signal input to place the
waveform output pins and channel 0
pins of MTU2 in high impedance
state.
In the SH7125, while POE3 function
is selected in the PFC, the pin is
pulled up inside this LSI if no signals
are input to them.
Serial
communication
interface (SCI)
TXD2 to
TXD0
RXD2 to
O Transmit data Transmit data output pins
I Receive data Receive data input pins
RXD0
SCK2 to
I/O Serial clock Clock input/output pins
SCK0
(SH7125)
SCK2, SCK0
(SH7124)
A/D converter
(ADC)
AN7 to AN0 I Analog input pins Analog input pins
ADTRG
(only in
I A/D conversion
trigger input
External trigger input pin for starting
A/D conversion
SH7125)
AVcc I Analog power
supply
Power supply pin for the A/D
converter
Connect all AVcc pins to the system
power supply (Vcc) when the A/D
converter is not used. The A/D
converter does not work if any pin is
open.
Section 1 Overview
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Section 1 Overview
Classification Symbol I/O Name Function
A/D converter AVss I Analog ground Ground pin for the A/D converter
Connect it to the system ground (0
V).
Connect all AVss pins to the system
ground (0 V) correctly. The A/D
converter does not work if any pin is
open.
I/O ports
PA15 to PA0
I/O General port 16-bit input/output port pins
(SH7125)
PA9 to PA6,
8-bit input/output port pins
PA4, PA3,
PA1, PA0
(SH7124)
PB16, PB5,
I/O General port 5-bit input/output port pins
PB3 to PB1
(SH7125)
PB5, PB3,
3-bit input/output port pins
PB1
(SH7124)
PE15 to PE0
I/O General port 16-bit input/output port pins
(SH7125)
PE15 to PE8,
12-bit input/output port pins
PE3 to PE0
(SH7124)
PF7 to PF0 I General port 8-bit input port pins
User debugging
interface
(H-UDI)
TCK I Test clock Test-clock input pin
TMS I Test mode select Inputs the test-mode select signal.
TDI I Test data input Serial input pin for instructions and
data
TDO O Test data
output
Serial output pin for instructions and
data
TRST I Test reset Initialization-signal input pin
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Section 1 Overview
Classification Symbol I/O Name Function
E10A interface
ASEMD0 I ASE mode Sets the ASE mode.
When a low level is input, this LSI
enters ASE mode. When a high level
is input, this LSI enters the normal
mode. The emulator functions are
available in ASE mode. When no
signal is input, this pin is pulled up
inside this LSI.
ASEBRK I Break request E10A emulator break input pin
ASEBRKAK O Break mode
acknowledge
Indicates that the E10A emulator has
entered its break mode.
Note: The WDTOVF pin should not be pulled down. When absolutely necessary, pull it down
through a resistor of 1 MΩ or larger.
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Section 1 Overview
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Section 2 CPU
2.1 Features
• General registers: 32-bit register × 16
• Basic instructions: 62
• Addressing modes: 11
Register direct (Rn)
Register indirect (@Rn)
Post-increment register indirect (@Rn+)
Pre-decrement register indirect (@-Rn)
Register indirect with displacement (@disp:4, Rn)
Index register indirect (@R0, Rn)
GBR indirect with displacement (@disp:8, GBR)
Index GBR indirect (@R0, GBR)
PC relative with displacement (@disp:8, PC)
PC relative (disp:8/disp:12/Rn)
Immediate (#imm:8)
Section 2 CPU
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Section 2 CPU
2.2 Register Configuration
There are three types of registers: general registers (32-bit × 16), control registers (32-bit × 3), and
system registers (32-bit × 4).
General register (Rn)
31 0
R15, SP (hardware stack pointer)*
Status register (SR)
31 9 8 7 6 5 4 3 2 1 0
Global base register (GBR)
31
Vector base register (VBR)
31
Multiply and accumulate register (MAC)
31 0
Procedure register (PR)
31 0
Program counter (PC)
31 0
Notes: 1. R0 can be used as an index register in index register indirect or index GBR
indirect addressing mode. For some instructions, only R0 is used as the
source or destination register.
2. R15 is used as a hardware stack pointer during exception handling.
1
R0*
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
M
QI3I2I1I0 S
GBR
VBR
MACH
MACL
PR
PC
2
T
0
0
Figure 2.1 CPU Internal Register Configuration
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Section 2 CPU
2.2.1 General Registers (Rn)
There are sixteen 32-bit general registers (Rn), designated R0 to R15. The general registers are
used for data processing and address calculation. R0 is also used as an index register. With a
number of instructions, R0 is the only register that can be used. R15 is used as a hardware stack
pointer (SP). In exception handling, R15 is used for accessing the stack to save or restore the
status register (SR) and program counter (PC) values.
2.2.2 Control Registers
There are three 32-bit control registers, designated status register (SR), global base register
(GBR), and vector base register (VBR). SR indicates a processing state. GBR is used as a base
address in GBR indirect addressing mode for data transfer of on-chip peripheral module registers.
VBR is used as a base address of the exception handling (including interrupts) vector table.
• Status register (SR)
Bit:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
----------------
Initial value:
0000000000000000
R/W:
RRRRRRRRRRRRRRRR
Bit:
Initial value:
R/W:
151413121110987654321
- - - - - - M Q I[3:0] - - S T
000000- -111100 - RRRRRRR/WR/WR/WR/WR/WR/WRRR/WR/W
0
Bit
Bit
name Default
Read/
Write Description
31 to 10 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
9 M Undefined R/W Used by the DIV0U, DIV0S, and DIV1 instructions.
8 Q Undefined R/W Used by the DIV0U, DIV0S, and DIV1 instructions.
7 to 4 I[3:0] 1111 R/W Interrupt Mask
3, 2 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
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Section 2 CPU
Bit
1 S Undefined R/W S Bit
0 T Undefined R/W T Bit
Bit
name Default
Read/
Write Description
Used by the multiply and accumulate instruction.
Indicates true (1) or false (0) in the following
instructions: MOVT, CMP/cond, TAS, TST, BT (BT/S),
BF (BF/S), SETT, CLRT
Indicates carry, borrow, overflow, or underflow in the
following instructions: ADDV, ADDC, SUBV, SUBC,
NEGC, DIV0U, DIV0S, DIV1, SHAR, SHAL, SHLR,
SHLL, ROTR, ROTL, ROTCR, ROTCL
• Global-base register (GBR)
This register indicates a base address in GBR indirect addressing mode. The GBR indirect
addressing mode is used for data transfer of the on-chip peripheral module registers and logic
operations.
• Vector-base register (VBR)
This register indicates the base address of the exception handling vector table.
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Section 2 CPU
2.2.3 System Registers
There are four 32-bit system registers, designated two multiply and accumulate registers (MACH
and MACL), a procedure register (PR), and program counter (PC).
• Multiply and accumulate registers (MACH and MACL)
This register stores the results of multiplication and multiply-and-accumulate operation.
• Procedure register (PR)
This register stores the return-destination address from subroutine procedures.
• Program counter (PC)
The PC indicates the point which is four bytes (two instructions) after the current execution
instruction.
2.2.4 Initial Values of Registers
Table 2.1 lists the initial values of registers after a reset.
Table 2.1 Initial Values of Registers
Type of register Register Default
General register R0 to R14 Undefined
R15 (SP) SP value set in the exception handling vector table
Control register SR I3 to I0: 1111 (H'F)
Reserved bits: 0
Other bits: Undefined
GBR Undefined
VBR H'00000000
System register MACH, MACL, PR Undefined
PC PC value set in the exception handling vector table
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Section 2 CPU
2.3 Data Formats
2.3.1 Register Data Format
The size of register operands is always longwords (32 bits). When loading byte (8 bits) or word
(16 bits) data in memory into a register, the data is sign-extended to longword and stored in the
register.
31 0
Longword
Figure 2.2 Register Data Format
2.3.2 Memory Data Formats
Memory data formats are classified into bytes, words, and longwords. Byte data can be accessed
from any address. Locate, however, word data at an address 2n, longword data at 4n. Otherwise,
an address error will occur if an attempt is made to access word data starting from an address other
than 2n or longword data starting from an address other than 4n. In such cases, the data accessed
cannot be guaranteed. The hardware stack area, pointed by the hardware stack pointer (SP, R15),
uses only longword data starting from address 4n because this area holds the program counter and
status register.
Address m + 1
Address 2n
Address 4n
Address m
31 23
Byte Byte Byte Byte
Word Word
Address m + 2
15 7
Longword
Figure 2.3 Memory Data Format
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Address m + 3
0
Page 43
Section 2 CPU
2.3.3 Immediate Data Formats
Immediate data of eight bits is placed in the instruction code.
For the MOV, ADD, and CMP/EQ instructions, the immediate data is sign-extended to longword
and then calculated. For the TST, AND, OR, and XOR instructions, the immediate data is zeroextended to longword and then calculated. Thus, if the immediate data is used for the AND
instruction, the upper 24 bits in the destination register are always cleared.
The immediate data of word or longword is not placed in the instruction code. It is placed in a
table in memory. The table in memory is accessed by the MOV immediate data instruction in PC
relative addressing mode with displacement.
2.4 Features of Instructions
2.4.1 RISC Type
The instructions are RISC-type instructions with the following features:
Fixed 16-Bit Length: All instructions have a fixed length of 16 bits. This improves program code
efficiency.
One Instruction per Cycle: Since pipelining is used, basic instructions can be executed in one
cycle.
Data Size: The basic data size for operations is longword. Byte, word, or longword can be
selected as the memory access size. Byte or word data in memory is sign-extended to longword
and then calculated. Immediate data is sign-extended to longword for arithmetic operations or
zero-extended to longword size for logical operations.
Table 2.2 Word Da t a Sign Extension
CPU in this LSI Description Example of Other CPUs
MOV.W @(disp,PC),R1
ADD R1,R0
........
.DATA.W H'1234
Note: * Immediate data is accessed by @(disp,PC).
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Sign-extended to 32 bits, R1
becomes H'00001234, and is
then operated on by the ADD
instruction.
ADD.W #H'1234,R0
Page 44
Section 2 CPU
Load/Store Architecture: Basic operations are executed between registers. In operations
involving memory, data is first loaded into a register (load/store architecture). However, bit
manipulation instructions such as AND are executed directly in memory.
Delayed Branching: Unconditional branch instructions means the delayed branch instructions.
With a delayed branch instruction, the branch is made after execution of the instruction
immediately following the delayed branch instruction. This minimizes disruption of the pipeline
when a branch is made. The conditional branch instructions have two types of instructions:
conditional branch instructions and delayed branch instructions.
Table 2.3 Delayed Branch Instructions
CPU in this LSI Description Example of Other CPUs
BRA TRGET
ADD R1,R0
ADD is executed before branch to TRGET. ADD.W R1,R0
BRA TRGET
Multiply/Multiply-and-Accumulate Operations: A 16 × 16 → 32 multiply operation is
executed in one to two cycles, and a 16 × 16 + 64 → 64 multiply-and-accumulate operation in two
to three cycles. A 32 × 32 → 64 multiply operation and a 32 × 32 + 64 → 64 multiply-andaccumulate operation are each executed in two to four cycles.
T Bit: The result of a comparison is indicated by the T bit in SR, and a conditional branch is
performed according to whether the result is True or False. Processing speed has been improved
by keeping the number of instructions that modify the T bit to a minimum.
Table 2.4 T Bit
CPU in this LSI Description Example of Other CPUs
CMP/GE R1,R0 When R0 ≥ R1, the T bit is set. CMP.W R1,R0
BT TRGET0 When R0 ≥ R1, a branch is made to TRGET0. BGE TRGET0
BF TRGET1 When R0 < R1, a branch is made to TRGET1. BLT TRGET1
ADD #1,R0 The T bit is not changed by ADD. SUB.W #1,R0
CMP/EQ #0,R0 When R0 = 0, the T bit is set. BEQ TRGET
BT TRGET A branch is made when R0 = 0.
Immediate Data: 8-bit immediate data is placed in the instruction code. Word and longword
immediate data is not placed in the instruction code. It is placed in a table in memory. The table in
memory is accessed with the MOV immediate data instruction using PC relative addressing mode
with displacement.
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Section 2 CPU
Table 2.5 Access to Immediate Data
Type This LSI's CPU Example of Other CPU
8-bit immediate MOV #H'12,R0 MOV.B #H'12,R0
16-bit immediate MOV.W @(disp,PC),R0
........
.DATA.W H'1234
32-bit immediate MOV.L @(disp,PC),R0
........
.DATA.L H'12345678
Note: * Immediate data is accessed by @(disp,PC).
MOV.W #H'1234,R0
MOV.L #H'12345678,R0
Absolute Addresses: When data is accessed by absolute address, place the absolute address value
in a table in memory beforehand. The absolute address value is transferred to a register using the
method whereby immediate data is loaded when an instruction is executed, and the data is
accessed using the register indirect addressing mode.
Table 2.6 Ac c e ss to Absolute Address
Type CPU in this LSI Example of Other CPUs
Absolute address MOV.L @(disp,PC),R1
MOV.B @R1,R0
........
.DATA.L H'12345678
Note: * Immediate data is referenced by @(disp,PC).
MOV.B @H'12345678,R0
16-Bit/32-Bit Displacement: When data is accessed using the 16- or 32-bit displacement
addressing mode, the displacement value is placed in a table in memory beforehand. Using the
method whereby immediate data is loaded when an instruction is executed, this value is
transferred to a register and the data is accessed using index register indirect addressing mode.
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Section 2 CPU
Table 2.7 Access with Displacement
Type CPU in this LSI Example of Other CPUs
16-bit displacement MOV.W @(disp,PC),R0
MOV.W @(H'1234,R1),R2
MOV.W @(R0,R1),R2
........
.DATA.W H'1234
Note: * Immediate data is referenced by @(disp,PC).
2.4.2 Addressing Modes
Table 2.8 lists addressing modes and effective address calculation methods.
Table 2.8 Addressing Modes and Effect ive Addresses
Addressing
Mode
Register
direct
Register
indirect
Register
indirect with
post-increment
Register
indirect with
pre-decrement
Instruction
Format Effective Address Calculation Method
Rn Effective address is register Rn.
(Operand is register Rn contents.)
@Rn Effective address is register Rn contents.
Rn Rn
@Rn+ Effective address is register Rn contents. A
constant is added to Rn after instruction
execution: 1 for a byte operand, 2 for a word
operand, 4 for a longword operand.
Rn Rn
Rn + 1/2/4
1/2/4
+
@–Rn Effective address is register Rn contents,
decremented by a constant beforehand: 1 for a
byte operand, 2 for a word operand, 4 for a
longword operand.
Rn
Rn - 1/2/4
1/2/4
-
Rn - 1/2/4
Calculation
Formula
Rn
Rn
After instruction
execution
Byte: Rn + 1 → Rn
Word: Rn + 2 → Rn
Longword: Rn + 4
→ Rn
Byte: Rn – 1 → Rn
Word: Rn – 2 → Rn
Longword: Rn – 4
→ Rn
(Instruction
executed with Rn
after calculation)
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Section 2 CPU
Addressing
Mode
Register
indirect with
displacement
Index
register indirect
GBR indirect
with
displacement
Instruction
Format Effective Address Calculation Method
@(disp:4,
Rn)
Effective address is register Rn contents with
4-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2
(word), or 4 (longword), according to the
operand size.
Rn
disp
(zero-extended)
1/2/4
+
×
Rn
+ disp × 1/2/4
@(R0, Rn) Effective address is sum of register Rn and R0
contents.
Rn
+ R0
Rn
@(disp:8,
GBR)
+
R0
Effective address is register GBR contents with
8-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2
(word), or 4 (longword), according to the
operand size.
GBR
disp
(zero-extended)
+
×
GBR
+ disp × 1/2/4
Calculation
Formula
Byte: Rn + disp
Word: Rn + disp × 2
Longword: Rn +
disp × 4
Rn + R0
Byte: GBR + disp
Word: GBR + disp ×
2
Longword: GBR +
disp × 4
Index GBR
indirect
@(R0,
GBR)
1/2/4
Effective address is sum of register GBR and
R0 contents.
GBR
+
GBR + R0
R0
GBR + R0
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Section 2 CPU
Addressing
Mode
PC relative with
displacement
Instruction
Format Effective Address Calculation Method
@(disp:8,
PC)
Effective address is PC with 8-bit displacement
disp added. After disp is zero-extended, it is
multiplied by 2 (word) or 4 (longword), according
to the operand size. With a longword operand,
the lower 2 bits of PC are masked.
*With longword operand
*
&
+
×
PC + disp × 2
or
PC&
H'FFFFFFFC
+ disp × 4
H'FFFFFFFC
disp
(zero-extended)
PC
2/4
PC relative disp:8 Effective address is PC with 8-bit displacement
disp added after being sign-extended and
multiplied by 2.
PC
disp
(sign-extended)
2
+
PC + disp × 2
×
disp:12 Effective address is PC with 12-bit displacement
disp added after being sign-extended and
multiplied by 2.
PC
disp
(sign-extended)
+
PC + disp × 2
×
Calculation
Formula
Word: PC + disp
× 2
Longword:
PC&H'FFFFFFFC
+ disp × 4
PC + disp × 2
PC + disp × 2
2
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Section 2 CPU
Addressing
Mode
PC relative Rn Effective address is sum of PC and Rn.
Immediate #imm:8 8-bit immediate data imm of TST, AND, OR,
Instruction
Format Effective Address Calculation Method
PC
+
Rn
PC + Rn
Calculation
Formula
PC + Rn
or XOR instruction is zero-extended.
#imm:8 8-bit immediate data imm of MOV, ADD, or
CMP/EQ instruction is sign-extended.
#imm:8 8-bit immediate data imm of TRAPA instruction
is zero-extended and multiplied by 4.
2.4.3 Instruction Formats
This section describes the instruction formats, and the meaning of the source and destination
operands. The meaning of the operands depends on the instruction code. The following symbols
are used in the table.
xxxx: Instruction code
mmmm: Source register
nnnn: Destination register
iiii: Immediate data
dddd: Displacement
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Section 2 CPU
Table 2.9 Instruction Formats
Instruction Format Source Operand
0 type
15 0
xxxx xxxx xxxx xxxx
n type
15 0
xxxx nnnn xxxx xxxx
m type
15 0
xxxx mmmm xxxx xxxx
NOP
nnnn: register
Control register or
system register
Control register or
system register
mmmm: register
direct
mmmm: postincrement register
indirect
mmmm: register
indirect
PC relative using
Rm
Destination
Operand
Sample Instruction
MOVT Rn
direct
nnnn: register
STS MACH,Rn
direct
nnnn: pre-
STC.L SR,@-Rn
decrement register
indirect
Control register or
LDC Rm,SR
system register
Control register or
LDC.L @Rm+,SR
system register
JMP @Rm
BRAF Rm
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Instruction Format Source Operand
nm type
15 0
xxxx nnnn mmmm xxxx
mmmm: register
direct
mmmm: register
direct
mmmm: postincrement register
indirect (multiplyand-accumulate
operation)
nnnn: * post-
increment register
indirect (multiplyand-accumulate
operation)
mmmm: postincrement register
indirect
mmmm: register
direct
mmmm: register
direct
md type
15 0
xxxx xxxx mmmm dddd
nd4 type
15 0
xxxx xxxx nnnn dddd
mmmmdddd:
register indirect
with displacement
R0 (register direct) nnnndddd:
mmmm: register
15 0
xxxx nnnn mmmm dddd
direct
mmmmdddd:
register indirect
with displacement
Section 2 CPU
Destination
Operand
nnnn: register
Sample Instruction
ADD Rm,Rn
direct
nnnn: register
MOV.L Rm,@Rn
indirect
MACH, MACL MAC.W @Rm+,@Rn+
nnnn: register
MOV.L @Rm+,Rn
direct
nnnn: pre-
MOV.L Rm,@-Rn
decrement register
indirect
nnnn: index
MOV.L Rm,@(R0,Rn)
register indirect
R0 (register direct) MOV.B @(disp,Rm),R0
MOV.B R0,@(disp,Rn)
register indirect
with displacement
nnnndddd:
MOV.L Rm,@(disp,Rn) nmd type
register indirect
with displacement
nnnn: register
MOV.L @(disp,Rm),Rn
direct
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Section 2 CPU
Destination
Instruction Format Source Operand
d type
15 0
xxxx xxxx dddd dddd
dddddddd: GBR
indirect with
displacement
R0 (register direct) dddddddd: GBR
Operand
R0 (register direct) MOV.L @(disp,GBR),R0
Sample Instruction
MOV.L R0,@(disp,GBR)
indirect with
displacement
dddddddd:
R0 (register direct) MOVA @(disp,PC),R0
PC relative with
displacement
dddddddd:
BF label
PC relative
d12 type
15 0
xxxx dddd dddd dddd
nd8 type
15 0
xxxx nnnn dddd dddd
i type
15 0
xxxx xxxx iiii iiii
dddddddddddd:
PC relative
dddddddd: PC
relative with
displacement
iiiiiiii:
nnnn: register
direct
Index GBR indirect AND.B
immediate
iiiiiiii:
R0 (register direct) AND #imm,R0
BRA label
(label=disp+PC)
MOV.L @(disp,PC),Rn
#imm,@(R0,GBR)
immediate
iiiiiiii:
TRAPA #imm
immediate
ni type
15 0
xxxx nnnn iiii iiii
iiiiiiii:
immediate
nnnn: register
direct
ADD #imm,Rn
Note: * In multiply and accumulate instructions, nnnn is the source register.
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2.5 Instruction Set
2.5.1 Instruction Set by Type
Table 2.10 lists the instructions classified by type.
Table 2.10 Instruction Types
Section 2 CPU
Type
Data transfer
instructions
Arithmetic
operation
instructions
Kinds of
Instruction
5
21
Number of
Op Code Function
MOV Data transfer
Immediate data transfer
Peripheral module data transfer
Structure data transfer
MOVA Effective address transfer
MOVT T bit transfer
SWAP Upper/lower swap
XTRCT Extraction of middle of linked registers
ADD Binary addition
ADDC Binary addition with carry
ADDV Binary addition with overflow
CMP/cond Comparison
DIV1 Division
DIV0S Signed division initialization
DIV0U Unsigned division initialization
DMULS Signed double-precision multiplication
DMULU Unsigned double-precision multiplication
DT Decrement and test
EXTS Sign extension
EXTU Zero extension
MAC Multiply-and-accumulate, double-
precision multiply-and-accumulate
MUL Double-precision multiplication
Instructions
39
33
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Section 2 CPU
Type
Arithmetic
operation
instructions
Logic
operation
instructions
Shift
instructions
Kinds of
Instruction Op Code Function
21
MULS Signed multiplication
MULU Unsigned multiplication
NEG Sign inversion
NEGC Sign inversion with borrow
SUB Binary subtraction
SUBC Binary subtraction with carry
SUBV Binary subtraction with underflow
6
AND Logical AND
NOT Bit inversion
OR Logical OR
TAS Memory test and bit setting
TST T bit setting for logical AND
XOR Exclusive logical OR
10
ROTL 1-bit left shift
ROTR 1-bit right shift
ROTCL 1-bit left shift with T bit
ROTCR 1-bit right shift with T bit
SHAL Arithmetic 1-bit left shift
SHAR Arithmetic 1-bit right shift
SHLL Logical 1-bit left shift
SHLLn Logical n-bit left shift
SHLR Logical 1-bit right shift
SHLRn Logical n-bit right shift
Number of
Instructions
33
14
14
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Section 2 CPU
Type
Branch
instructions
Kinds of
Instruction Op Code Function
9
BF Conditional branch, delayed conditional
branch (T = 0)
Number of
Instructions
11
BT Conditional branch, delayed conditional
branch (T = 1)
BRA Unconditional branch
BRAF Unconditional branch
BSR Branch to subroutine procedure
BSRF Branch to subroutine procedure
JMP Unconditional branch
JSR Branch to subroutine procedure
RTS Return from subroutine procedure
System
control
instructions
11
CLRT T bit clear
CLRMAC MAC register clear
31
LDC Load into control register
LDS Load into system register
NOP No operation
RTE Return from exception handling
SETT T bit setting
SLEEP Transition to power-down mode
STC Store from control register
STS Store from system register
TRAPA Trap exception handling
Total: 62 142
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Section 2 CPU
The instruction code, operation, and execution cycles of the instructions are listed in the following
tables, classified by type.
Summary of
Instruction Instruction Code
Indicated by mnemonic.
Explanation of Symbols
OP.Sz SRC, DEST
OP: Operation code
Sz: Size
SRC: Source
DEST: Destination
Rm: Source register
Rn: Destination
register
imm: Immediate data
disp: Displacement*
Indicated in MSB ↔
LSB order.
Explanation of Symbols
mmmm: Source register
nnnn: Destination
register
0000: R0
0001: R1
.........
1111: R15
iiii: Immediate data
dddd: Displacement
2
Operation
Indicates summary of
operation.
Explanation of Symbols
→, ←: Transfer direction
(xx): Memory operand
M/Q/T: Flag bits in SR
&: Logical AND of each bit
|: Logical OR of each bit
^: Exclusive logical OR of
each bit
–: Logical NOT of each bit
<<n: n-bit left shift
>>n: n-bit right shift
Execution
Cycles
Value when no
wait cycles are
1
*
inserted
T Bit
Value of T bit after
instruction is executed
Explanation of Symbols
: No change
Notes: 1. The table shows the minimum number of execution states. In practice, the number of
instruction execution states will be increased in cases such as the following:
• When there is contention between an instruction fetch and a data access
• When the destination register of a load instruction (memory → register) is also used
by the following instruction
2. Scaled (×1, ×2, or ×4) according to the instruction operand size, etc.
For details, see SH-1/SH-2/SH-DSP Software Manual.
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Section 2 CPU
2.5.2 Data Transfer Instructions
Table 2.11 Data Transfer Instructions
Execution
Instruction Operation Code
MOV #imm,Rn imm → Sign extension
→ Rn
MOV.W @(disp,PC),Rn (disp × 2 + PC) → Sign
extension →
Rn
1110nnnniiiiiiii 1
1001nnnndddddddd
MOV.L @(disp,PC),Rn (disp × 4 + PC) → Rn 1101nnnndddddddd 1
MOV Rm,Rn Rm → Rn 0110nnnnmmmm0011 1
MOV.B Rm,@Rn Rm → (Rn) 0010nnnnmmmm0000 1
MOV.W Rm,@Rn Rm → (Rn) 0010nnnnmmmm0001 1
MOV.L Rm,@Rn Rm → (Rn) 0010nnnnmmmm0010 1
MOV.B @Rm,Rn (Rm) → Sign extension
→ Rn
MOV.W @Rm,Rn (Rm) → Sign extension
→ Rn
0110nnnnmmmm0000 1
0110nnnnmmmm0001 1
MOV.L @Rm,Rn (Rm) → Rn 0110nnnnmmmm0010 1
MOV.B Rm,@–Rn Rn–1 → Rn, Rm → (Rn) 0010nnnnmmmm0100 1
MOV.W Rm,@–Rn Rn–2 → Rn, Rm → (Rn) 0010nnnnmmmm0101 1
MOV.L Rm,@–Rn Rn–4 → Rn, Rm → (Rn) 0010nnnnmmmm0110 1
MOV.B @Rm+,Rn (Rm) → Sign extension
→ Rn, Rm + 1 → Rm
MOV.W @Rm+,Rn (Rm) → Sign extension
→ Rn, Rm + 2 → Rm
0110nnnnmmmm0100 1
0110nnnnmmmm0101 1
MOV.L @Rm+,Rn (Rm) → Rn,Rm + 4 → Rm 0110nnnnmmmm0110 1
MOV.B R0,@(disp,Rn) R0 → (disp + Rn) 10000000nnnndddd 1
MOV.W R0,@(disp,Rn) R0 → (disp × 2 + Rn) 10000001nnnndddd 1
MOV.L Rm,@(disp,Rn) Rm → (disp × 4 + Rn) 0001nnnnmmmmdddd 1
MOV.B @(disp,Rm),R0 (disp + Rm) → Sign
extension → R0
MOV.W @(disp,Rm),R0 (disp × 2 + Rm) → Sign
extension → R0
10000100mmmmdddd 1
10000101mmmmdddd 1
MOV.L @(disp,Rm),Rn (disp × 4 + Rm) → Rn 0101nnnnmmmmdddd 1
Cycles
1
T Bit
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Section 2 CPU
Execution
Instruction Operation Code
Cycles
MOV.B Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0100 1
MOV.W Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0101 1
MOV.L Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0110 1
MOV.B @(R0,Rm),Rn (R0 + Rm) → Sign
extension → Rn
MOV.W @(R0,Rm),Rn (R0 + Rm) → Sign
extension → Rn
0000nnnnmmmm1100 1
0000nnnnmmmm1101 1
MOV.L @(R0,Rm),Rn (R0 + Rm) → Rn 0000nnnnmmmm1110 1
MOV.B R0,@(disp,GBR) R0 → (disp + GBR) 11000000dddddddd 1
MOV.W R0,@(disp,GBR) R0 → (disp × 2 + GBR) 11000001dddddddd 1
MOV.L R0,@(disp,GBR) R0 → (disp × 4 + GBR) 11000010dddddddd 1
MOV.B @(disp,GBR),R0 (disp + GBR) → Sign
extension → R0
MOV.W @(disp,GBR),R0 (disp × 2 + GBR) →
Sign extension → R0
MOV.L @(disp,GBR),R0 (disp × 4 + GBR) → R0 11000110dddddddd 1
11000100dddddddd 1
11000101dddddddd 1
MOVA @(disp,PC),R0 disp × 4 + PC → R0 11000111dddddddd 1
MOVT Rn T → Rn 0000nnnn00101001 1
SWAP.B Rm,Rn Rm → Swap lowest two
bytes → Rn
SWAP.W Rm,Rn Rm → Swap two
consecutive words → Rn
XTRCT Rm,Rn Rm: Middle 32 bits of
Rn → Rn
0110nnnnmmmm1000 1
0110nnnnmmmm1001 1
0010nnnnmmmm1101 1
T Bit
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Section 2 CPU
2.5.3 Arithmetic Operation Instructions
Table 2.12 Arithmetic Operation Instructions
Execution
Instruction Operation Code
ADD Rm,Rn
Rn + Rm → Rn 0011nnnnmmmm1100 1
Cycles
ADD #imm,Rn Rn + imm → Rn 0111nnnniiiiiiii 1
ADDC Rm,Rn Rn + Rm + T → Rn,
Carry → T
ADDV Rm,Rn Rn + Rm → Rn,
Overflow → T
0011nnnnmmmm1110 1 Carry
0011nnnnmmmm1111 1 Overflow
CMP/EQ #imm,R0 If R0 = imm, 1 → T 10001000iiiiiiii 1 Comparison
CMP/EQ Rm,Rn If Rn = Rm, 1 → T 0011nnnnmmmm0000 1 Comparison
CMP/HS Rm,Rn If Rn ≥ Rm with
unsigned data, 1 → T
CMP/GE Rm,Rn If Rn ≥ Rm with signed
data, 1 → T
CMP/HI Rm,Rn If Rn > Rm with
unsigned data, 1 → T
CMP/GT Rm,Rn If Rn > Rm with signed
data, 1 → T
0011nnnnmmmm0010 1 Comparison
0011nnnnmmmm0011 1 Comparison
0011nnnnmmmm0110 1 Comparison
0011nnnnmmmm0111 1 Comparison
CMP/PZ Rn If Rn ≥ 0, 1 → T 0100nnnn00010001 1 Comparison
CMP/PL Rn If Rn > 0, 1 → T 0100nnnn00010101 1 Comparison
CMP/STR Rm,Rn If Rn and Rm have an
equivalent byte, 1 → T
DIV1 Rm,Rn Single-step division
(Rn/Rm)
DIV0S Rm,Rn MSB of Rn → Q, MSB
of Rm → M, M^ Q → T
0010nnnnmmmm1100 1 Comparison
0011nnnnmmmm0100 1 Calculation
0010nnnnmmmm0111 1 Calculation
DIV0U 0 → M/Q/T 0000000000011001 1 0
DMULS.L Rm,Rn Signed operation of
Rn × Rm → MACH,
MACL 32 × 32 → 64 bits
0011nnnnmmmm1101 2 to 5*
T Bit
result
result
result
result
result
result
result
result
result
result
result
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Section 2 CPU
Execution
Instruction Operation Code
DMULU.L Rm,Rn
DT Rn Rn - 1 → Rn, if Rn = 0, 1 →
EXTS.B Rm,Rn A byte in Rm is sign-
EXTS.W Rm,Rn A word in Rm is sign-
EXTU.B Rm,Rn A byte in Rm is zero-
EXTU.W Rm,Rn A word in Rm is zero-
MAC.L @Rm+,@Rn+ Signed operation of (Rn)
MAC.W @Rm+,@Rn+ Signed operation of (Rn)
MUL.L Rm,Rn Rn × Rm → MACL
MULS.W Rm,Rn Signed operation of Rn
MULU.W Rm,Rn Unsigned operation of
Unsigned operation of
Rn × Rm → MACH,
MACL 32 × 32 → 64 bits
T, else 0 → T
extended → Rn
extended → Rn
extended → Rn
extended → Rn
× (Rm) + MAC → MAC,
32 × 32 + 64 → 64 bits
× (Rm) + MAC → MAC,
16 × 16 + 64 → 64 bits
32 × 32 → 32 bits
× Rm → MAC
16 × 16 → 32 bits
Rn × Rm → MAC
16 × 16 → 32 bits
0011nnnnmmmm0101 2 to 5*
0100nnnn00010000 1 Comparison
0110nnnnmmmm1110 1
0110nnnnmmmm1111 1
0110nnnnmmmm1100 1
0110nnnnmmmm1101 1
0000nnnnmmmm1111 2 to 5*
0100nnnnmmmm1111 2 to 4*
0000nnnnmmmm0111 2 to 5*
0010nnnnmmmm1111 1 to 3*
0010nnnnmmmm1110 1 to 3*
Cycles
NEG Rm,Rn 0-Rm → Rn 0110nnnnmmmm1011 1
NEGC Rm,Rn 0-Rm-T → Rn,
Borrow → T
0110nnnnmmmm1010 1 Borrow
SUB Rm,Rn Rn-Rm → Rn 0011nnnnmmmm1000 1
SUBC Rm,Rn Rn-Rm–T → Rn,
Borrow → T
SUBV Rm,Rn Rn-Rm → Rn,
Underflow → T
Note: * Indicates the number of execution cycles for normal operation.
0011nnnnmmmm1010 1 Borrow
0011nnnnmmmm1011 1 Underflow
T Bit
result
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Section 2 CPU
2.5.4 Logic Operation Instructions
Table 2.13 Logic Operation Instructions
Execution
Instruction Operation Code
AND Rm,Rn
Rn & Rm → Rn 0010nnnnmmmm1001 1
AND #imm,R0 R0 & imm → R0 11001001iiiiiiii 1
AND.B #imm,@(R0,GBR) (R0 + GBR) & imm →
(R0 + GBR)
11001101iiiiiiii 3
NOT Rm,Rn ~Rm → Rn 0110nnnnmmmm0111 1
OR Rm,Rn Rn | Rm → Rn 0010nnnnmmmm1011 1
OR #imm,R0 R0 | imm → R0 11001011iiiiiiii 1
OR.B #imm,@(R0,GBR) (R0 + GBR) | imm →
(R0 + GBR)
TAS.B @Rn If (Rn) is 0, 1 → T;
1 → MSB of (Rn)
TST Rm,Rn Rn & Rm; if the result
is 0, 1 → T
TST #imm,R0 R0 & imm; if the result
is 0, 1 → T
TST.B #imm,@(R0,GBR) (R0 + GBR) & imm;
if the result is 0, 1 → T
11001111iiiiiiii 3
0100nnnn00011011 4 Test result
0010nnnnmmmm1000 1 Test result
11001000iiiiiiii 1 Test result
11001100iiiiiiii 3 Test result
XOR Rm,Rn Rn ^ Rm → Rn 0010nnnnmmmm1010 1
XOR #imm,R0 R0 ^ imm → R0 11001010iiiiiiii 1
XOR.B #imm,@(R0,GBR) (R0 + GBR) ^ imm →
(R0 + GBR)
11001110iiiiiiii 3
Cycles
T Bit
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Section 2 CPU
2.5.5 Shift Instructions
Table 2.14 Shift Instructions
Execution
Instruction Operation Code
ROTL Rn
T ← Rn ← MSB 0100nnnn00000100 1 MSB
Cycles
ROTR Rn LSB → Rn → T 0100nnnn00000101 1 LSB
ROTCL Rn T ← Rn ← T 0100nnnn00100100 1 MSB
ROTCR Rn T → Rn → T 0100nnnn00100101 1 LSB
SHAL Rn T ← Rn ← 0 0100nnnn00100000 1 MSB
SHAR Rn MSB → Rn → T 0100nnnn00100001 1 LSB
SHLL Rn T ← Rn ← 0 0100nnnn00000000 1 MSB
SHLR Rn 0 → Rn → T 0100nnnn00000001 1 LSB
SHLL2 Rn Rn << 2 → Rn 0100nnnn00001000 1
SHLR2 Rn Rn >> 2 → Rn 0100nnnn00001001 1
SHLL8 Rn Rn << 8 → Rn 0100nnnn00011000 1
SHLR8 Rn Rn >> 8 → Rn 0100nnnn00011001 1
SHLL16 Rn Rn << 16 → Rn 0100nnnn00101000 1
SHLR16 Rn Rn >> 16 → Rn 0100nnnn00101001 1
T Bit
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Section 2 CPU
2.5.6 Branch Instructions
Table 2.15 Branch Instructions
Execution
Instruction Operation Code
BF label
BF/S label Delayed branch, if T = 0,
BT label If T = 1, disp × 2 + PC →
BT/S label Delayed branch, if T = 1,
BRA label Delayed branch,
BRAF Rm Delayed branch,
BSR label Delayed branch, PC → PR,
BSRF Rm Delayed branch, PC → PR,
If T = 0, disp × 2 + PC →
PC;
if T = 1, nop
disp × 2 + PC → PC;
if T = 1, nop
PC;
if T = 0, nop
disp × 2 + PC → PC;
if T = 0, nop
disp × 2 + PC → PC
Rm + PC → PC
disp × 2 + PC → PC
Rm + PC → PC
10001011dddddddd 3/1*
10001111dddddddd 2/1*
10001001dddddddd 3/1*
10001101dddddddd 2/1*
1010dddddddddddd 2
0000mmmm00100011 2
1011dddddddddddd 2
0000mmmm00000011 2
JMP @Rm Delayed branch, Rm → PC 0100mmmm00101011 2
JSR @Rm Delayed branch, PC → PR,
Rm → PC
0100mmmm00001011 2
RTS Delayed branch, PR → PC 0000000000001011 2
Note: * One cycle when the branch is not executed.
Cycles
T Bit
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Section 2 CPU
2.5.7 System Control Instructions
Table 2.16 System Control Instructions
Execution
Instruction Operation Code
CLRT 0 → T 0000000000001000 1 0
CLRMAC 0 → MACH, MACL 0000000000101000 1
LDC Rm,SR Rm → SR 0100mmmm00001110 1 LSB
LDC Rm,GBR Rm → GBR 0100mmmm00011110 1
LDC Rm,VBR Rm → VBR 0100mmmm00101110 1
LDC.L @Rm+,SR (Rm) → SR, Rm + 4 → Rm 0100mmmm00000111 3 LSB
LDC.L @Rm+,GBR (Rm) → GBR, Rm + 4 →
Rm
LDC.L @Rm+,VBR (Rm) → VBR, Rm + 4 →
Rm
0100mmmm00010111 3
0100mmmm00100111 3
LDS Rm,MACH Rm → MACH 0100mmmm00001010 1
LDS Rm,MACL Rm → MACL 0100mmmm00011010 1
LDS Rm,PR Rm → PR 0100mmmm00101010 1
LDS.L @Rm+,MACH (Rm) → MACH, Rm + 4 →
Rm
LDS.L @Rm+,MACL (Rm) → MACL, Rm + 4 →
Rm
0100mmmm00000110 1
0100mmmm00010110 1
LDS.L @Rm+,PR (Rm) → PR, Rm + 4 → Rm 0100mmmm00100110 1
NOP No operation 0000000000001001 1
RTE Delayed branch,
Stack area → PC/SR
0000000000101011 5
SETT 1 → T 0000000000011000 1 1
SLEEP Sleep 0000000000011011 4*
STC SR,Rn SR → Rn 0000nnnn00000010 1
STC GBR,Rn GBR → Rn 0000nnnn00010010 1
STC VBR,Rn VBR → Rn 0000nnnn00100010 1
STC.L SR,@–Rn Rn–4 → Rn, SR → (Rn) 0100nnnn00000011 1
STC.L GBR,@–Rn Rn–4 → Rn, GBR → (Rn) 0100nnnn00010011 1
STC.L VBR,@–Rn Rn–4 → Rn, VBR → (Rn) 0100nnnn00100011 1
Cycles
T Bit
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Section 2 CPU
Execution
Instruction Operation Code
Cycles
T Bit
STS MACH,Rn MACH → Rn 0000nnnn00001010 1
STS MACL,Rn MACL → Rn 0000nnnn00011010 1
STS PR,Rn PR → Rn 0000nnnn00101010 1
STS.L MACH,@–Rn Rn–4 → Rn, MACH → (Rn) 0100nnnn00000010 1
STS.L MACL,@–Rn Rn–4 → Rn, MACL → (Rn) 0100nnnn00010010 1
STS.L PR,@–Rn Rn–4 → Rn, PR → (Rn) 0100nnnn00100010 1
TRAPA #imm PC/SR → Stack area,
(imm × 4 + VBR) → PC
11000011iiiiiiii 8
Note: * Number of execution cycles until this LSI enters sleep mode.
About the number of execution cycles:
The table lists the minimum number of execution cycles. In practice, the number of
execution cycles will be increased depending on the conditions such as:
• When there is a conflict between instruction fetch and data access
• When the destination register of a load instruction (memory → register) is also used
by the instruction immediately after the load instruction.
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Section 2 CPU
2.6 Processing States
The CPU has the five processing states: reset, exception handling, program execution, and powerdown. Figure 2.4 shows the CPU state transition.
From any state
when RES = 0
Power-on reset state Manual reset state
When internal power-on reset by WDT
or internal manual reset by WDT occurs.
SSBY bit = 0
Sleep mode
From any state
when RES = 1 and MRES = 0
RES = 1
Exception
processing
for SLEEP
instruction
RES = 0
Exception
handling state
source
occurs
Program
execution state
Exception
processing
ends
RES = 1,
MRES = 1
SSBY bit = 1 and
STBYMD bit = 1
for SLEEP
instruction
standby mode
Figure 2.4 Transitions between Processing States
Software
Power-down mode
Reset state
NMI interrupt or IRQ
interrupt occurs
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Section 2 CPU
• Reset state
The CPU is reset. When the RES pin is low, the CPU enters the power-on reset state. When the
RES pin is high and MRES pin is low, the CPU enters the manual reset state.
• Exception handling state
This state is a transitional state in which the CPU processing state changes due to a request for
exception handling such as a reset or an interrupt.
When a reset occurs, the execution start address as the initial value of the program counter
(PC) and the initial value of the stack pointer (SP) are fetched from the exception handling
vector table. Then, a branch is made for the start address to execute a program.
When an interrupt occurs, the PC and status register (SR) are saved in the stack area pointed to
by SP. The start address of an exception handling routine is fetched from the exception
handling vector table and a branch to the address is made to execute a program.
Then the processing state enters the program execution state.
• Program execution state
The CPU executes programs sequentially.
• Power-down state
The CPU stops to reduce power consumption. The SLEEP instruction makes the CPU enter
sleep mode or software standby mode.
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Section 2 CPU
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Section 3 MCU Operating Modes
Section 3 MCU Operating Modes
3.1 Selection of Operating Modes
This LSI has four MCU operating modes and three on-chip flash memory programming modes.
The operating mode is determined by the setting of FWE, MD1, and MD0 pins. Table 3.1 shows
the allowable combinations of these pin settings; do not set these pins in the other way than the
shown combinations.
When power is applied to the system, be sure to conduct power-on reset.
The MCU operating mode can be selected from MCU extension modes 0 to 2 and single chip
mode. For the on-chip flash memory programming mode, boot mode, user boot mode, and user
program mode, which are on-chip programming modes are available.
Table 3.1 Selection of Operating Modes
Pin Setting
Mode No. FWE MD1 Mode Name On-Chip ROM
Mode 3 0 1 Single chip mode Active
Mode 4* 1 0 Boot mode Active
Mode 6* 1 1 User program mode Active
Note: * Flash memory programming mode.
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Section 3 MCU Operating Modes
3.2 Input/Output Pins
Table 3.2 describes the configuration of operating mode related pin.
Table 3.2 Pin Configuration
Pin Name Input/Output Function
MD1 Input Designates operating mode through the level applied to this pin
FWE Input Enables, by hardware, programming/erasing of the on-chip flash
memory
3.3 Operating Modes
3.3.1 Mode 3 (Single Chip Mode)
All ports can be used in this mode, however the external address cannot be used.
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Section 3 MCU Operating Modes
3.4 Address Map
The address map for the operating modes are shown in figures 3.1 to 3.3.
Mode 3
H'00000000
H'0001FFFF
H'00020000
Single chip mode
On-chip ROM (128 kbytes)
Reserved area
H'FFFF9FFF
H'FFFFA000
On-chip RAM (8 kbytes)
H'FFFFBFFF
H'FFFFC000
On-chip peripheral
I/O registers
H'FFFFFFFF
Figure 3.1 Address Map in SH7125, SH7124 (128 Kbytes Flash Memory Version)
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Section 3 MCU Operating Modes
H'00000000
H'0000FFFF
H'00010000
Mode 3
Single chip mode
On-chip ROM (64 kbytes)
Reserved area
H'FFFF9FFF
H'FFFFA000
On-chip RAM (8 kbytes)
H'FFFFBFFF
H'FFFFC000
On-chip peripheral
I/O registers
H'FFFFFFFF
Figure 3.2 Address Map in SH7125, SH7124 (64 Kbytes Flash Memory Version)
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H'00000000
H'00007FFF
H'00008000
Mode 3
Single chip mode
On-chip ROM (32 kbytes)
Reserved area
Section 3 MCU Operating Modes
H'FFFF9FFF
H'FFFFA000
On-chip RAM (8 kbytes)
H'FFFFBFFF
H'FFFFC000
On-chip peripheral
I/O registers
H'FFFFFFFF
Figure 3.3 Address Map in SH7124 (32 Kbytes Flash Memory Version)
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Section 3 MCU Operating Modes
3.5 Initial State in This LSI
In the initial state of this LSI, some of on-chip modules are set in module standby state for saving
power. When operating these modules, clear module standby state according to the procedure in
section 19, Power-Down Modes.
3.6 Note on Changing Operating Mode
When changing operating mode while power is applied to this LSI, make sure to do it in the
power-on reset state (that is, the low level is applied to the RES pin).
MD1
t
*
MDS
RES
Note: * See section 21.3.2, Control Signal Timing.
Figure 3.4 Reset Input Timing when Changing O pera ting Mode
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Section 4 Clock Pulse Generator (CPG)
Section 4 Clock Pulse Generator (CPG)
This LSI has a clock pulse generator (CPG) that generates an internal clock (Iφ), a bus clock (Bφ),
a peripheral clock (Pφ), and a clock (MPφ) for the MTU2 module. The CPG also controls power-
down modes.
4.1 Features
• Five clocks generated independently
An internal clock (Iφ) for the CPU; a peripheral clock (Pφ) for the on-chip peripheral modules;
a bus clock (Bφ = CK) for the external bus interface; and a MTU2 clock (MPφ) for the on-chip
MTU2 module.
• Frequency change function
Frequencies of the internal clock (Iφ), bus clock (Bφ), peripheral clock (Pφ), and MTU2 clock
(MPφ) can be changed independently using the divider circuit within the CPG. Frequencies are
changed by software using the frequency control register (FRQCR) setting.
• Power-down mode control
The clock can be stopped in sleep mode and standby mode and specific modules can be
stopped using the module standby function.
• Oscillation stop detection
If the clock supplied through the clock input pin stops for any reason, the timer pins can be
automatically placed in the high-impedance state.
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Section 4 Clock Pulse Generator (CPG)
Figure 4.1 shows a block diagram of the CPG.
Oscillator unit
XTAL
EXTAL
Crystal
oscillator
PLL circuit
(×8)
Divider
×1/2
×1/4
×1/8
MTU2 clock
(MPφ)
Internal clock
(Iφ)
Oscillation
stop detection
[Legend]
FRQCR:
OSCCR:
STBCR1:
STBCR2:
STBCR3:
STBCR4:
STBCR5:
STBCR6:
Oscillation stop
detection circuit
Clock frequency
control circuit
OSCCR
Frequency control register
Oscillation stop detection control register
Standby control register 1
Standby control register 2
Standby control register 3
Standby control register 4
Standby control register 5
Standby control register 6
FRQCR
Peripheral clock
(Pφ)
Bus clock
(Bφ = CK)
CPG control unit
Standby
control circuit
STBCR2STBCR1 STBCR3 STBCR4 STBCR5 STBCR6
Bus interface
Internal bus
Figure 4.1 Block Diagram of CPG
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Section 4 Clock Pulse Generator (CPG)
The clock pulse generator blocks function as follows:
PLL Circuit: The PLL circuit multiples the clock frequency input from the crystal oscillator or
the EXTAL pin by 8. The multiplication ratio is fixed at ×8.
Crystal Oscillator: The crystal oscillator is an oscillator circuit when a crystal resonator is
connected to the XTAL and EXTAL pins.
Divider: The divider generates clocks with the frequencies to be used by the internal clock (Iφ),
bus clock (Bφ), peripheral clock (Pφ), and MTU2 clock (MPφ).
The frequencies can be selected from 1/2, 1/4 (initial value), and 1/8 times the frequency output
from the PLL circuit. The division ratio should be specified in the frequency control register
(FRQCR).
Oscillation Stop Detection Circuit: This circuit detects an abnormal condition in the crystal
oscillator.
Clock Frequency Control Circuit: The clock frequency control circuit controls the clock
frequency according to the setting in the frequency control register (FRQCR).
Standby Control Circuit: The standby control circuit controls the state of the on-chip oscillator
circuit and other modules in sleep or standby mode.
Frequency Control Register (FRQCR): The frequency control register (FRQCR) has control
bits for the frequency division ratios of the internal clock (Iφ), bus clock (Bφ), peripheral clock
(Pφ), and MTU2 clock (MPφ).
Oscillation Stop Detection Control Register (OSCCR): The oscillation stop detection control
register (OSCCR) has an oscillation stop detection flag and a bit for selecting flag status output
through an external pin.
Standby Control Registers 1 to 6 (STBCR1 t o STBCR6): The standby control register
(STBCR) has bits for controlling the power-down modes. For details, see section 19, Power-Down
Modes.
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Section 4 Clock Pulse Generator (CPG)
Table 4.1 shows the operating clock for each module.
Table 4.1 Operating Clock for Each Module
Operating Clock Operating Module Operating Clock Operating Module
Internal clock (Iφ) CPU Peripheral clock (Pφ) POE
UBC SCI
ROM A/D
RAM CMT
WDT
Bus clock (Bφ) MTU2 clock (MPφ) MTU2
4.2 Input/Output Pins
Table 4.2 shows the CPG pin configuration.
Table 4.2 Pin Configuration
Pin Name Abbr. I/O Description
Crystal input/output
pins
(clock input pins)
XTAL Output Connects a crystal resonator.
EXTAL Input Connects a crystal resonator or an external clock.
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Section 4 Clock Pulse Generator (CPG)
4.3 Clock Operating Mode
Table 4.3 shows the clock operating mode of this LSI.
Table 4.3 Clock O perating Mode
Source PLL Circuit Input to Divider
EXTAL input or crystal resonator ON (×8) ×8
The frequency of the external clock input from the EXTAL pin is multiplied by 8 in the PLL
circuit before being supplied to the on-chip modules in this LSI, which eliminates the need to
generate a high-frequency clock outside the LSI. Since the input clock frequency ranging from 10
MHz to 12.5 MHz can be used, the internal clock (Iφ) frequency ranges from 10 MHz to 50 MHz.
Maximum operating frequencies:
Iφ = 50 MHz, Bφ = 40 MHz, Pφ = 40 MHz, and MPφ = 40 MHz
Table 4.4 shows the frequency division ratios that can be specified with FRQCR.
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Section 4 Clock Pulse Generator (CPG)
Table 4.4 Frequency Division Ratios Specifiable with FRQCR
PLL
Multiplication
Ratio Iφ Bφ Pφ MPφ Iφ Bφ Pφ MPφ
×8 1/8 1/8 1/8 1/8 1 1 1 1 10 10 10 10 10
1/4 1/8 1/8 1/8 2 1 1 1 10 20 10 10 10
1/4 1/4 1/4 1/4 2 2 2 2 10 20 20 20 20
1/2 1/4 1/4 1/4 4 2 2 2 10 40 20 20 20
1/2 1/2 1/2 1/2 4 4 4 4 10 40 40 40 40
1/8 1/8 1/8 1/8 1 1 1 1 12.5 12.5 12.5 12.5 12.5
1/4 1/8 1/8 1/8 2 1 1 1 12.5 25 12.5 12.5 12.5
1/4 1/4 1/4 1/4 2 2 2 2 12.5 25 25 25 25
1/2 1/4 1/4 1/4 4 2 2 2 12.5 50 25 25 25
FRQCR Division Ratio
Setting
Cl ock Rati o Clock Frequency (MHz)*
Input
Clock
Iφ Bφ Pφ MPφ
Notes: * Clock frequencies when the input clock frequency is assumed to be the shown value.
The internal clock (Iφ) frequency must be 10 to 50 MHz and the peripheral clock (Pφ)
frequency must be 10 to 40 MHz. The bus clock (Bφ) frequency must be equal to the
peripheral clock (Pφ) frequency.
1. The PLL multiplication ratio is fixed at ×8. The division ratio can be selected from ×1/2,
×1/4, and ×1/8 for each clock by the setting in the frequency control register.
2. The output frequency of the PLL circuit is the product of the frequency of the input from
the crystal resonator or EXTAL pin and the multiplication ratio (×8) of the PLL circuit.
3. The input to the divider is always the output from the PLL circuit.
4. The internal clock (Iφ) frequency is the product of the frequency of the input from the
crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the
division ratio of the divider. The resultant frequency must be a maximum of 50 MHz
(maximum operating frequency).
5. The peripheral clock (Pφ) frequency is the product of the frequency of the input from the
crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the
division ratio of the divider. The resultant frequency must be a maximum of 40 MHz.
6. When using the MTU2, the MTU2 clock (MPφ) frequency must be equal to or higher
than the peripheral clock frequency (Pφ). The MTU2 clock (MPφ) frequency are the
product of the frequency of the input from the crystal resonator or EXTAL pin, the
multiplication ratio (×8) of the PLL circuit, and the division ratio of the divider.
7. The frequency of the CK pin is always be equal to the bus clock (Bφ) frequency.
8. The bus clock (Bφ) frequency must be equal to the peripheral clock (Pφ) frequency.
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Section 4 Clock Pulse Generator (CPG)
4.4 Register Descriptions
The CPG has the following registers.
For details on the addresses of these registers and the states of these registers in each processing
state, see section 20, List of Registers
Table 4.5 Register Configuration
Abbrevia-
Register Name
tion
Frequency control register FRQCR R/W H'36DB H'FFFFE800 16
Oscillation stop detection
OSCCR R/W H'00 H'FFFFE814 8
control register
4.4.1 Frequency Control Register (FRQCR)
FRQCR is a 16-bit readable/writable register that specifies the frequency division ratios for the
internal clock (Iφ), bus clock (Bφ), peripheral clock (Pφ), and MTU2 clock (MPφ). FRQCR can be
accessed only in words.
R/W Initial Value Address Access Size
FRQCR is initialized to H'36DB only by a power-on reset (except a power-on reset due to a WDT
overflow).
Before making changes to FRQCR, stop clock supply to each module except the CPU, on-chip
ROM, and on-chip-RAM.
Bit:
151413121110987654321
---- IFC[2:0] BFC[2:0] PFC[2:0] MPFC[2:0]
Initial value:
0011011011011011
R/W:
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
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Section 4 Clock Pulse Generator (CPG)
Initial
Bit Bit Name
Value
R/W Description
15 0 R Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12 IFC[2:0] 011 R/W Internal Clock (Iφ) Frequency Division Ratio
Specify the division ratio of the internal clock (Iφ)
frequency with respect to the output frequency of PLL
circuit. If a prohibited value is specified, subsequent
operation is not guaranteed.
000: Setting prohibited
001: ×1/2
010: Setting prohibited
011: ×1/4 (initial value)
100: ×1/8
Other than above: Setting prohibited
11 to 9 BFC[2:0] 011 R/W Bus Clock (Bφ) Frequency Division Ratio
Specify the division ratio of the bus clock (Bφ)
frequency with respect to the output frequency of PLL
circuit. If a prohibited value is specified, subsequent
operation is not guaranteed.
000: Setting prohibited
001: ×1/2
010: Setting prohibited
011: ×1/4 (initial value)
100: ×1/8
Other than above: Setting prohibited
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Section 4 Clock Pulse Generator (CPG)
Initial
Bit Bit Name
Value
R/W Description
8 to 6 PFC[2:0] 011 R/W Peripheral Clock (Pφ) Frequency Division Ratio
Specify the division ratio of the peripheral clock (Pφ)
frequency with respect to the output frequency of PLL
circuit. If a prohibited value is specified, subsequent
operation is not guaranteed.
000: Setting prohibited
001: ×1/2
010: Setting prohibited
011: ×1/4 (initial value)
100: ×1/8
Other than above: Setting prohibited
5 to 3 011 R/W Reserved
These bits are always read as B'011. The write value
should always be B'011.
2 to 0 MPFC[2:0] 011 R/W MTU2 Clock (MPφ) Frequency Division Ratio
Specify the division ratio of the MTU2 clock (MPφ)
frequency with respect to the output frequency of PLL
circuit. If a prohibited value is specified, subsequent
operation is not guaranteed.
000: Setting prohibited
001: ×1/2
010: Setting prohibited
011: ×1/4 (initial value)
100: ×1/8
Other than above: Setting prohibited
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Section 4 Clock Pulse Generator (CPG)
4.4.2 Oscillation Stop Detection Control Register (OSCCR)
OSCCR is an 8-bit readable/writable register that has an oscillation stop detection flag and selects
flag status output to an external pin. OSCCR can be accessed only in bytes.
Bit:
Initial value:
R/W:
7654321
-----
00000000
RRRRRRRR/W
OSC
STOP
0
OSC
ERS
Initial
Bit Bit Name
Value
R/W Description
7 to 3 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
2 OSCSTOP 0 R Oscillation Stop Detection Flag
[Setting conditions]
• When a stop in the clock input is detected during
normal operation
• When software standby mode is entered
[Clearing conditions]
• By a power-on reset input through the RES pin
• When software standby mode is canceled
1 0 R Reserved
This bit is always read as 0. The write value should
always be 0.
0 OSCERS 0 R/W Oscillation Stop Detection Flag Output Select
Selects whether to output the oscillation stop detection
flag signal through the WDTOVF pin.
0: Outputs only the WDT overflow signal through the
WDTOVF pin
1: Outputs the WDT overflow signal and the oscillation
stop detection flag signal through the WDTOVF pin
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Section 4 Clock Pulse Generator (CPG)
4.5 Changing Frequency
Selecting division ratios for the frequency divider can change the frequencies of the internal clock
(Iφ), bus clock (Bφ), peripheral clock (Pφ), and MTU2 clock (MPφ). This is controlled by software
through the frequency control register (FRQCR). The following describes how to specify the
frequencies.
1. In the initial state, IFC2 to IFC0 = H'011 (×1/4), BFC2 to BFC0 = H'011 (×1/4), PFC2 to
PFC0 = H'011 (×1/4), and MPFC2 to MPFC0 = H'011 (×1/4).
2. Stop all modules except the CPU, on-chip ROM, and on-chip RAM.
3. Set the desired values in bits IFC2 to IFC0, BFC2 to BFC0, PFC2 to PFC0, and MPFC2 to
MPFC0 bits. Since the frequency multiplication ratio in the PLL circuit is fixed at ×8, the
frequencies are determined only be selecting division ratios. When specifying the frequencies,
satisfy the following condition: internal clock (Iφ) ≥ bus clock (Bφ) = peripheral clock (Pφ).
When using the MTU2 clock, specify the frequencies to satisfy the following condition:
internal clock (Iφ) ≥ MTU2 clock (MPφ) ≥ peripheral clock (Pφ).
4. After an instruction to rewrite FRQCR has been issued, the actual clock frequencies will
change after (1 to 24n) cyc + 11Bφ + 7Pφ.
n: Division ratio specified by the BFC bit in FRQCR (1, 1/2, 1/4, or 1/8)
cyc: Clock obtained by dividing EXTAL by 8 with the PLL.
Note: (1 to 24n) depends on the internal state.
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Section 4 Clock Pulse Generator (CPG)
4.6 Oscillator
Clock pulses can be supplied from a connected crystal resonator or an external clock.
4.6.1 Connecting Crystal Resonator
A crystal resonator can be connected as shown in figure 4.2. Use the damping resistance (Rd)
listed in table 4.6. Use a crystal resonator that has a resonance frequency of 10 to 12.5 MHz. It is
recommended to consult the crystal resonator manufacturer concerning the compatibility of the
crystal resonator and the LSI.
C
EXTAL
XTAL
R
d
Figure 4.2 Connection of Crystal Resonator (Example)
Table 4.6 Damping Resistance Values (Reference Values)
L1
C
L2
CL1 = CL2 = 18 to 22 pF (Reference values)
Frequency (MHz) 10 12.5
Rd (Ω) (Reference Values) 0 0
Figure 4.3 shows an equivalent circuit of the crystal resonator. Use a crystal resonator with the
characteristics listed in table 4.7.
C
L
XTAL
L R
C
s
0
EXTAL
Figure 4.3 Crystal Resonator Equivalent Circuit
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Section 4 Clock Pulse Generator (CPG)
Table 4.7 Crystal Resonator Characteristics
Frequency (MHz) 10 12.5
Rs Max. (Ω) (Reference Values) 60 50
C0 Max. (pF) (Reference Values) 7 7
4.6.2 External Clock Input Method
Figure 4.4 shows an example of an external clock input connection. In this case, make the external
clock high level to stop it when in software standby mode. During operation, make the external
input clock frequency 10 to 12.5 MHz.
When leaving the XTAL pin open, make sure the parasitic capacitance is less than 10 pF.
Even when inputting an external clock, be sure to wait at least the oscillation stabilization time in
power-on sequence or in releasing software standby mode, in order to ensure the PLL stabilization
time.
EXTAL
XTAL
Open state
External clock input
Figure 4.4 Example of External Clock Connection
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Section 4 Clock Pulse Generator (CPG)
4.7 Function for Detecting Oscillator Stop
This CPG detects a stop in the clock input if any system abnormality halts the clock supply.
When no change has been detected in the EXTAL input for a certain period, the OSCSTOP bit in
OSCCR is set to 1 and this state is retained until a power-on reset is input through the RES pin or
software standby mode is canceled. If the OSCERS bit is set to 1 at this time, an oscillation stop
detection flag signal is output through the WDTOVF pin. In addition, the high-current ports (pins
to which the TIOC3B, TIOC3D, and TIOC4A to TIOC4D signals in the MTU2 are assigned) are
always placed in high-impedance state regardless of the PFC setting. For details, refer to appendix
A, Pin States.
Even in software standby mode, these pins are always placed in high-impedance state. For details,
refer to appendix A, Pin States. These pins enter the normal state after software standby mode is
canceled. Under an abnormal condition where oscillation stops while the LSI is not in software
standby mode, LSI operations other than the oscillation stop detection function become
unpredictable. In this case, even after oscillation is restarted, LSI operations including the above
high-current pins become unpredictable.
Even while no change is detected in the EXTAL input, the PLL circuit in this LSI continues
oscillating at a frequency range from 100 kHz to 10 MHz (depending on the temperature and
operating voltage).
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Section 4 Clock Pulse Generator (CPG)
4.8 Usage Notes
4.8.1 Note on Crystal Resonator
A sufficient evaluation at the user’s site is necessary to use the LSI, by referring the resonator
connection examples shown in this section, because various characteristics related to the crystal
resonator are closely linked to the user’s board design. As the oscillator circuit's circuit constant
will depend on the resonator and the floating capacitance of the mounting circuit, the value of each
external circuit’s component should be determined in consultation with the resonator
manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied
to the oscillator pin.
4.8.2 Notes on Board Design
Measures against radiation noise are taken in this LSI. If further reduction in radiation noise is
needed, it is recommended to use a multiple layer board and provide a layer exclusive to the
system ground.
When using a crystal resonator, place the crystal resonator and its load capacitors as close as
possible to the XTAL and EXTAL pins. Do not route any signal lines near the oscillator circuitry
as shown in figure 4.5. Otherwise, correct oscillation can be interfered by induction.
C
L2
C
L1
Signal A Signal B
This LSI
XTAL
EXTAL
Avoid
Figure 4.5 Cautio ns for Oscillator Circuit Board Design
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Section 4 Clock Pulse Generator (CPG)
A circuitry shown in figure 4.6 is recommended as an external circuitry around the PLL. Separate
the PLL power lines (PLLVss) and the system power lines (Vcc, Vss) at the board power supply
source, and be sure to insert bypass capacitors CB and CPB close to the pins.
PLLV
SS
V
CL
CPB = 0.1 µF
V
CC
V
SS
*
CB = 0.1 µF
*
(Recommended values are shown.)
Note: * CB and CPB are laminated ceramic type.
Figure 4.6 Recommended External Circuitry around PLL
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Section 5 Exception Handling
Section 5 Exception Handling
5.1 Overview
5.1.1 Types of Exception Handling and Priority
Exception handling is started by four sources: resets, address errors, interrupts and instructions and
have the priority, as shown in table 5.1. When several exceptions are detected at once, they are
processed according to the priority.
Table 5.1 Types of Exceptions and Priority
Exception Exception Source Priority
Reset Power-on reset High
Manual reset
Interrupt User break (break before instruction execution)
Address error CPU address error (instruction fetch)
Instruction General illegal instructions (undefined code)
Illegal slot instruction (undefined code placed immediately after a
delayed branch instruction*
Trap instruction (TRAPA instruction)
Address error CPU address error (data access)
Interrupt User break (break after instruction execution or operand break)
NMI
IRQ
On-chip peripheral modules Low
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and
BRAF.
2. Instructions that change the PC value: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF,
TRAPA, BF/S, BT/S, BSRF, BRAF, LDC Rm,SR, LDC.L @Rm+,SR.
1
or instruction that changes the PC value*2)
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Section 5 Exception Handling
5.1.2 Exception Handling Operations
The exceptions are detected and the exception handling starts according to the timing shown in
table 5.2.
Table 5.2 Timing for Exception Detection and Start of Exception Handling
Exception Timing of Source Detection and Start of Exception Handling
Reset Power-on reset Started when the RES pin changes from low to high or when the
WDT overflows.
Manual reset Started when the MRES pin changes from low to high or when the
WDT overflows.
Address error
Interrupt
Instruction Trap instruction Started by the execution of the TRAPA instruction.
General illegal
instructions
Illegal slot
instructions
Detected during the instruction decode stage and started after the
execution of the current instruction is completed.
Started when an undefined code placed at other than a delay slot
(immediately after a delayed branch instruction) is decoded.
Started when an undefined code placed at a delay slot
(immediately after a delayed branch instruction) or an instruction
that changes the PC value is detected.
When exception handling starts, the CPU operates
Exception Handling Triggered by Reset: The initial values of the program counter (PC) and
stack pointer (SP) are fetched from the exception handling vector table (PC from the address
H'00000000 and SP from the address H'00000004 when a power-on reset. PC from the address
H'00000008 and SP from the address H'0000000C when a manual reset.). For details, see section
5.1.3, Exception Handling Vector Table. H'00000000 is then written to the vector base register
(VBR), and H'F (B'1111) is written to the interrupt mask bits (I3 to I0) in the status register (SR).
The program starts from the PC address fetched from the exception handling vector table.
Exception Handling Triggere d by Address Error, Interrupt, and Instruction: SR and PC are
saved to the stack indicated by R15. For interrupt exception handling, the interrupt priority level is
written to the interrupt mask bits (I3 to I0) in SR. For address error and instruction exception
handling, bits I3 to I0 are not affected. The start address is then fetched from the exception
handling vector table and the program starts from that address.
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Section 5 Exception Handling
5.1.3 Exception Handling Vector Table
Before exception handling starts, the exception handling vector table must be set in memory. The
exception handling vector table stores the start addresses of exception handling routines. (The
reset exception handling table holds the initial values of PC and SP.)
All exception sources are given different vector numbers and vector table address offsets. The
vector table addresses are calculated from these vector numbers and vector table address offsets.
During exception handling, the start addresses of the exception handling routines are fetched from
the exception handling vector table that is indicated by this vector table address.
Table 5.3 shows the vector numbers and vector table address offsets. Table 5.4 shows how vector
table addresses are calculated.
Table 5.3 Vector Numbers and Vector Table Address Offsets
Exception Handling Source Vector Number Vector Table Address Offset
Power-on reset PC 0 H'00000000 to H'00000003
SP 1 H'00000004 to H'00000007
Manual reset PC 2 H'00000008 to H'0000000B
SP 3 H'0000000C to H'0000000F
General illegal instruction 4 H'00000010 to H'00000013
(Reserved for system use) 5 H'00000014 to H'00000017
Illegal slot instruction 6 H'00000018 to H'0000001B
(Reserved for system use) 7 H'0000001C to H'0000001F
8 H'00000020 to H'00000023
CPU address error 9 H'00000024 to H'00000027
(Reserved for system use) 10 H'00000028 to H'0000002B
Interrupt NMI 11 H'0000002C to H'0000002F
User break 12 H'00000030 to H'00000033
(Reserved for system use) 13 H'00000034 to H'00000037
: :
31 H'0000007C to H'0000007F
Trap instruction (user vector) 32 H'00000080 to H'00000083
: :
63 H'000000FC to H'000000FF
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Section 5 Exception Handling
Exception Handling Source Vector Number Vector Table Address Offset
Interrupt IRQ0 (SH7125)
IRQ1
IRQ2
IRQ3
(Reserved for system use)
64 H'00000100 to H'00000103
65 H'00000104 to H'00000107
66 H'00000108 to H'0000010B
67 H'0000010C to H'0000010F
68 H'00000110 to H'00000113
: :
71 H'0000011C to H'0000011F
On-chip peripheral module* 72 H'00000120 to H'00000123
: :
255 H'000003FC to H'000003FF
Note: * For details on the vector numbers and vector table address offsets of on-chip peripheral
module interrupts, see table 6.3 in section 6, Interrupt Controller (INTC).
Table 5.4 Calculating Exception Handling Vector Table Addresses
Exception Source Vector Table Address Calculation
Resets Vector table address = (vector table address offset)
= (vector number) × 4
Address errors, interrupts,
instructions
Notes: 1. VBR: Vector base register
2. Vector table address offset: See table 5.3.
3. Vector number: See table 5.3.
Vector table address = VBR + (vector table address offset)
= VBR + (vector number) × 4
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Section 5 Exception Handling
5.2 Resets
5.2.1 Types of Resets
Resets have priority over any exception source. There are two types of resets: power-on resets and
manual resets. As table 5.5 shows, both types of resets initialize the internal status of the CPU. In
power-on resets, all registers of the on-chip peripheral modules are initialized; in manual resets,
they are not.
Table 5.5 Reset Status
Conditions for Transition to
Type RES
Low Initialized Initialized Initialized Power-on reset
High Overflow High Initialized Initialized Initialized
High Not overflowed Low Initialized Not initialized Not initialized Manual reset
High Overflow High Initialized Not initialized Not initialized
Reset State
WDT
Overflow
MRES CPU, INTC
Internal State
On-Chip
Peripheral
Module
POE, PFC,
I/O Port
5.2.2 Power-On Reset
Power-On Reset by RES Pin: When the RES pin is driven low, this LSI enters the power-on
reset state. To reliably reset this LSI, the RES pin should be kept low for at least the oscillation
settling time when applying the power or when in standby mode (when the clock is halted) or at
least 20 tcyc when the clock is operating. During the power-on reset state, CPU internal states and
all registers of on-chip peripheral modules are initialized. See appendix A, Pin States, for the
status of individual pins during power-on reset mode.
In the power-on reset state, power-on reset exception handling starts when driving the RES pin
high after driving the pin low for the given time. The CPU operates as follows:
1. The initial value (execution start address) of the program counter (PC) is fetched from the
exception handling vector table.
2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table.
3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0)
of the status register (SR) are set to H'F (B'1111).
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Section 5 Exception Handling
4. The values fetched from the exception handling vector table are set in PC and SP, then the
program starts.
Be certain to always perform power-on reset exception handling when turning the system power
on.
Power-On Reset by WDT: When WTCNT of the WDT overflows while a setting is made so that
a power-on reset can be generated in watchdog timer mode of the WDT, this LSI enters the
power-on reset state.
The frequency control register (FRQCR) in the clock pulse generator (CPG) and the watchdog
timer (WDT) registers are not initialized by a reset generated by the WDT (these registers are only
initialized by a power-on reset from the RES pin).
If a reset caused by the signal input on the RES pin and a reset caused by a WDT overflow occur
simultaneously, the RES pin reset has priority, and the WOVF bit in RSTCSR is cleared to 0.
When the power-on reset exception handling caused by the WDT is started, the CPU operates as
follows:
1. The initial value (execution start address) of the program counter (PC) is fetched from the
exception handling vector table.
2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table.
3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0)
of the status register (SR) are set to H'F (B'1111).
4. The values fetched from the exception handling vector table are set in the PC and SP, then the
program starts.
5.2.3 Manual Reset
When the RES pin is high and the MRES pin is driven low, the LSI becomes to be a manual reset
state. To reliably reset the LSI, the MRES pin should be kept at low for at least the duration of the
oscillation settling time that is set in WDT when in software standby mode (when the clock is
halted) or at least 20 t
when the clock is operating. During manual reset, the CPU internal status
cyc
is initialized. Registers of on-chip peripheral modules are not initialized. See appendix A, Pin
States, for the status of individual pins during manual reset mode.
In the manual reset status, manual reset exception processing starts when the MRES pin is first
kept low for a set period of time and then returned to high. The CPU will then operate in the same
procedures as described for power-on resets.
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Section 5 Exception Handling
5.3 Address Errors
5.3.1 Address Error Sources
Address errors occur when instructions are fetched or data is read from or written to, as shown in
table 5.6.
Table 5.6 Bus Cycles and Address Errors
Bus Cycle
Type Bus Master Bus Cycle Description Address Errors
CPU Instruction fetched from even address None (normal) Instruction
fetch
Instruction fetched from a space other than
Instruction fetched from on-chip peripheral
Instruction fetched from external memory
read/write
Longword data accessed from a longword
Longword data accessed from other than a
Byte or word data accessed in on-chip
Longword data accessed in 16-bit on-chip
Longword data accessed in 8-bit on-chip
Reserved space accessed when in single
Instruction fetched from odd address Address error occurs
None (normal)
on-chip peripheral module space
Address error occurs
module space
Address error occurs
space in single chip mode
CPU
Word data accessed from even address None (normal) Data
Word data accessed from odd address Address error occurs
None (normal)
boundary
Address error occurs
long-word boundary
None (normal)
peripheral module space
None (normal)
peripheral module space
None (normal)
peripheral module space
Address error occurs
chip mode
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Section 5 Exception Handling
5.3.2 Address Error Exception So urce
When an address error exception is generated, the bus cycle which caused the address error ends,
the current instruction finishes, and then the address error exception handling starts. The CPU
operates as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value to be saved is the start address
of the instruction which caused an address error exception. When the instruction that caused
the exception is placed in the delay slot, the address of the delayed branch instruction which is
placed immediately before the delay slot.
3. The start address of the exception handling routine is fetched from the exception handling
vector table that corresponds to the generated address error, and the program starts executing
from that address. This branch is not a delayed branch.
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Section 5 Exception Handling
5.4 Interrupts
5.4.1 Interrupt Sources
Table 5.7 shows the sources that start the interrupt exception handling. They are NMI, user break,
IRQ, and on-chip peripheral modules.
Table 5.7 Interrupt Sources
Number of
Type Request Source
NMI NMI pin (external input) 1
User break User break controller (UBC) 1
IRQ IRQ0 to IRQ3 pins (external input) 4 (SH7125)
On-chip peripheral module Multi-function timer pulse unit 2 (MTU2) 28
Watchdog timer (WDT) 1
A/D converter (A/D_0 and A/D_1) 2
Compare match timer (CMT_0 and CMT_1) 2
Serial communication interface (SCI_0, SCI_1,
and SCI_2)
Port output enable (POE) 2
All interrupt sources are given different vector numbers and vector table address offsets. For
details on vector numbers and vector table address offsets, see table 6.3 in section 6, Interrupt
Controller (INTC).
Sources
3 (SH7124)
12
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Section 5 Exception Handling
5.4.2 Interrupt Priority
The interrupt priority is predetermined. When multiple interrupts occur simultaneously
(overlapped interruptions), the interrupt controller (INTC) determines their relative priorities and
starts the exception handling according to the results.
The priority of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and
priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always
accepted. The priority level of the user break interrupt is 15. IRQ interrupt and on-chip peripheral
module interrupt priority levels can be set freely using the interrupt priority registers A to F and H
to M (IPRA to IPRF and IPRH to IPRM) of the INTC as shown in table 5.8. The priority levels
that can be set are 0 to 15. Level 16 cannot be set. For details on IPRA to IPRF, see section 6.3.4,
Interrupt Priority Registers A to F and H to M (IPRA to IPRF and IPRH to IPRM).
Table 5.8 Interrupt Priority
Type Priority Level Comment
NMI 16 Fixed priority level. Cannot be masked.
User break 15 Fixed priority level. Can be masked.
IRQ 0 to 15
On-chip peripheral module
Set with interrupt priority registers A to F and H
to M (IPRA to IPRF and IPRH to IPRM).
5.4.3 Interrupt Exception Handling
When an interrupt occurs, the interrupt controller (INTC) ascertains its priority level. NMI is
always accepted, but other interrupts are only accepted if they have a priority level higher than the
priority level set in the interrupt mask bits (I3 to I0) of the status register (SR).
When an interrupt is accepted, exception handling begins. In interrupt exception handling, the
CPU saves SR and the program counter (PC) to the stack. The priority level of the accepted
interrupt is written to bits I3 to I0 in SR. Although the priority level of the NMI is 16, the value set
in bits I3 to I0 is H'F (level 15). Next, the start address of the exception handling routine is fetched
from the exception handling vector table for the accepted interrupt, and program execution
branches to that address and the program starts. For details on the interrupt exception handling, see
section 6.6, Interrupt Operation.
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