RENESAS R5F61657 User Manual

REJ09B0106-0100Z

32

H8SX/1657Group

Hardware Manual

Renesas 32-Bit CISC Microcomputer

H8SX Family / H8SX/1600 Series

H8SX/1657 R5F61657

Rev.1.00
Revision Date: Mar. 18, 2004

Rev. 1.00, 03/04, page ii of xl

Keep safety first in your circuit designs!

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third­party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.

5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.

7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.

8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.

Rev. 1.00, 03/04, page iii of xl

General Precautions on Handling of Product

1. Treatment of NC Pins

Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins

Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass­through current flows internally, and a malfunction may occur.

3. Processing before Initialization

Note: When power is first supplied, the product's state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses

Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.

Rev. 1.00, 03/04, page iv of xl

Configuration of This Manual

This manual comprises the following items:

1. General Precautions on Handling of Product

2. Configuration of This Manual

3. Preface

4. Contents

5. Overview

6. Description of Functional Modules

• CPU and System-Control Modules

• On-Chip Peripheral Modules

The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:

i) Feature

ii) Input/Output Pin

iii) Register Description

iv) Operation

v) Usage Note

When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.

7. List of Registers

8. Electrical Characteristics

9. Appendix

10. Main Revisions and Additions in this Edition (only for revised versions)

The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.

11. Index

Rev. 1.00, 03/04, page v of xl

Preface

The H8SX/1657 is a single-chip microcomputer made up of the high-speed internal 32-bit H8SX
CPU as its core, and the peripheral functions required to configure a system. The H8SX CPU is
upward compatible with the H8/300, H8/300H, and H8S CPUs.

Target Users: This manual was written for users who will be using the H8SX/1657 in the design

of application systems. Target users are expected to understand the fundamentals
of electrical circuits, logical circuits, and microcomputers.

Objective: This manual was written to explain the hardware functions and electrical

characteristics of the H8SX/1657 to the target users.
Refer to the H8SX Programming Manual for a detailed description of the
instruction set.

Notes on reading this manual:

• In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.

• In order to understand the details of the CPU's functions

Read the H8SX Programming Manual.

• In order to understand the details of a register when its name is known

Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 21,
List of Registers.

Examples: Register name: The following notation is used for cases when the same or a

similar function, e.g. 16-bit timer pulse unit or serial
communication interface, is implemented on more than one
channel:
XXX_N (XXX is the register name and N is the channel
number)

Bit order: The MSB is on the left and the LSB is on the right.

Number notation: Binary is B′xxxx, hexadecimal is H'xxxx, decimal is xxxx.
Signal notation: An overbar is added to a low-active signal: xxxx

Related Manuals: The latest versions of all related manuals are available from our web site.

Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/eng/

Rev. 1.00, 03/04, page vi of xl

H8SX/1657 Group manuals:

Document Title Document No.

H8SX/1657 Group Hardware Manual This manual

H8/SX Programming Manual REJ09B0102

Rev. 1.00, 03/04, page vii of xl

Rev. 1.00, 03/04, page viii of xl

Contents

Section 1 Overview............................................................................................1

1.1 Features............................................................................................................................. 1

1.2 Block Diagram.................................................................................................................. 2

1.3 Pin Assignments................................................................................................................3

1.3.1 Pin Assignments ..................................................................................................3

1.3.2 Pin Configuration in Each Operating Mode.........................................................4

1.3.3 Pin Functions ....................................................................................................... 8

Section 2 CPU....................................................................................................17

2.1 Features............................................................................................................................. 17

2.2 CPU Operating Modes...................................................................................................... 19

2.2.1 Normal Mode....................................................................................................... 19

2.2.2 Middle Mode ....................................................................................................... 21

2.2.3 Advanced Mode................................................................................................... 22

2.2.4 Maximum Mode .................................................................................................. 23

2.3 Instruction Fetch ...............................................................................................................25

2.4 Address Space...................................................................................................................25

2.5 Registers............................................................................................................................26

2.5.1 General Registers................................................................................................. 27

2.5.2 Program Counter (PC) .........................................................................................28

2.5.3 Condition-Code Register (CCR).......................................................................... 29

2.5.4 Extended Control Register (EXR) .......................................................................30

2.5.5 Vector Base Register (VBR)................................................................................ 31

2.5.6 Short Address Base Register (SBR).....................................................................31

2.5.7 Multiply-Accumulate Register (MAC)................................................................ 31

2.5.8 Initial Values of CPU Registers........................................................................... 31

2.6 Data Formats..................................................................................................................... 32

2.6.1 General Register Data Formats............................................................................ 32

2.6.2 Memory Data Formats......................................................................................... 33

2.7 Instruction Set................................................................................................................... 34

2.7.1 Instructions and Addressing Modes..................................................................... 36

2.7.2 Table of Instructions Classified by Function ....................................................... 40

2.7.3 Basic Instruction Formats .................................................................................... 50

2.8 Addressing Modes and Effective Address Calculation..................................................... 51

2.8.1 Register DirectRn ............................................................................................ 51

2.8.2 Register Indirect@ERn.................................................................................... 52

2.8.3 Register Indirect with Displacement @(d:2, ERn), @(d:16, ERn),

or @(d:32, ERn)...................................................................................................52

Rev. 1.00, 03/04, page ix of xl

2.8.4 Index Register Indirect with Displacement@(d:16,RnL.B),

@(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or

@(d:32,ERn.L) .................................................................................................... 52

2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment,

or Post-Decrement@ERn+, @−ERn, @+ERn, or @ERn− ............................. 52

2.8.6 Absolute Address@aa:8, @aa:16, @aa:24, or @aa:32....................................53

2.8.7 Immediate#xx .................................................................................................. 54

2.8.8 Program-Counter Relative@(d:8, PC) or @(d:16, PC): .................................. 54

2.8.9 Program-Counter Relative with Index Register@(RnL.B, PC),

@(Rn.W, PC), or @(ERn.L, PC)......................................................................... 55

2.8.10 Memory Indirect@@aa:8 ................................................................................ 55

2.8.11 Extended Memory Indirect@@vec:7 .............................................................. 56

2.8.12 Effective Address Calculation .............................................................................56

2.8.13 MOVA Instruction............................................................................................... 58

2.9 Processing States...............................................................................................................59

Section 3 MCU Operating Modes .....................................................................61

3.1 Operating Mode Selection ................................................................................................ 61

3.2 Register Descriptions........................................................................................................ 62

3.2.1 Mode Control Register (MDCR) ......................................................................... 62

3.2.2 System Control Register (SYSCR)...................................................................... 63

3.3 Operating Mode Descriptions........................................................................................... 66

3.3.1 Mode 1................................................................................................................. 66

3.3.2 Mode 2................................................................................................................. 66

3.3.3 Mode 4................................................................................................................. 66

3.3.4 Mode 5................................................................................................................. 67

3.3.5 Mode 6................................................................................................................. 67

3.3.6 Mode 7................................................................................................................. 67

3.3.7 Pin Functions ....................................................................................................... 68

3.4 Address Map.....................................................................................................................69

3.4.1 Address Map........................................................................................................ 69

Section 4 Exception Handling........................................................................... 71

4.1 Exception Handling Types and Priority............................................................................ 71

4.2 Exception Sources and Exception Handling Vector Table............................................... 72

4.3 Reset ................................................................................................................................. 74

4.3.1 Reset Exception Handling ................................................................................... 74

4.3.2 Interrupts after Reset............................................................................................ 74

4.3.3 On-Chip Peripheral Functions after Reset Release.............................................. 74

4.4 Traces................................................................................................................................ 77

4.5 Address Error.................................................................................................................... 78

4.5.1 Address Error Source........................................................................................... 78

4.5.2 Address Error Exception Handling...................................................................... 79

Rev. 1.00, 03/04, page x of xl

4.6 Interrupts........................................................................................................................... 80

4.6.1 Interrupt Sources.................................................................................................. 80

4.6.2 Interrupt Exception Handling ..............................................................................80

4.7 Instruction Exception Handling ........................................................................................81

4.7.1 Trap Instruction.................................................................................................... 81

4.7.2 Exception Handling by Illegal Instruction ........................................................... 82

4.8 Stack Status after Exception Handling..............................................................................83

4.9 Usage Note........................................................................................................................ 84

Section 5 Interrupt Controller ............................................................................85

5.1 Features............................................................................................................................. 85

5.2 Input/Output Pins.............................................................................................................. 87

5.3 Register Descriptions........................................................................................................ 87

5.3.1 Interrupt Control Register (INTCR) ....................................................................88

5.3.2 CPU Priority Control Register (CPUPCR) .......................................................... 89

5.3.3 Interrupt Priority Registers A to C, E to I, K, and L

(IPRA to IPRC, IPRE to IPRI, IPRK, and IPRL) ................................................90

5.3.4 IRQ Enable Register (IER) ..................................................................................92

5.3.5 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 94

5.3.6 IRQ Status Register (ISR).................................................................................... 98

5.3.7 Software Standby Release IRQ Enable Register (SSIER)................................... 99

5.4 Interrupt Sources...............................................................................................................100

5.4.1 External Interrupts ...............................................................................................100

5.4.2 Internal Interrupts ................................................................................................101

5.5 Interrupt Exception Handling Vector Table...................................................................... 102

5.6 Interrupt Control Modes and Interrupt Operation............................................................. 106

5.6.1 Interrupt Control Mode 0..................................................................................... 106

5.6.2 Interrupt Control Mode 2..................................................................................... 108

5.6.3 Interrupt Exception Handling Sequence .............................................................. 110

5.6.4 Interrupt Response Times ....................................................................................111

5.6.5 DTC and DMAC Activation by Interrupt ............................................................ 112

5.7 CPU Priority Control Function Over DTC and DMAC.................................................... 115

5.8 Usage Notes...................................................................................................................... 118

5.8.1 Conflict between Interrupt Generation and Disabling ......................................... 118

5.8.2 Instructions that Disable Interrupts...................................................................... 119

5.8.3 Times when Interrupts are Disabled .................................................................... 119

5.8.4 Interrupts during Execution of EEPMOV Instruction.......................................... 119

5.8.5 Interrupts during Execution of MOVMD and MOVSD Instructions...................119

5.8.6 Interrupts of Peripheral Modules .........................................................................120

Section 6 Bus Controller (BSC).........................................................................121

6.1 Features............................................................................................................................. 121

6.2 Register Descriptions........................................................................................................ 124

Rev. 1.00, 03/04, page xi of xl

6.2.1 Bus Width Control Register (ABWCR) .............................................................. 125

6.2.2 Access State Control Register (ASTCR) ............................................................. 126

6.2.3 Wait Control Registers A and B (WTCRA, WTCRB) ........................................ 127

6.2.4 Read Strobe Timing Control Register (RDNCR) ................................................ 132

6.2.5 CS Assertion Period Control Registers (CSACR) ............................................... 133

6.2.6 Idle Control Register (IDLCR)............................................................................ 135

6.2.7 Bus Control Register 1 (BCR1) ........................................................................... 137

6.2.8 Bus Control Register 2 (BCR2) ........................................................................... 139

6.2.9 Endian Control Register (ENDIANCR) ..............................................................140

6.2.10 SRAM Mode Control Register (SRAMCR) ........................................................ 141

6.2.11 Burst ROM Interface Control Register (BROMCR) ........................................... 142

6.2.12 Address/Data Multiplexed I/O Control Register (MPXCR) ................................ 144

6.3 Bus Configuration............................................................................................................. 145

6.4 Multi-Clock Function and Number of Access Cycles ...................................................... 146

6.5 External Bus...................................................................................................................... 149

6.5.1 Input/Output Pins................................................................................................. 149

6.5.2 Area Division....................................................................................................... 152

6.5.3 Chip Select Signals.............................................................................................. 153

6.5.4 External Bus Interface .........................................................................................154

6.5.5 Area and External Bus Interface.......................................................................... 158

6.5.6 Endian and Data Alignment................................................................................. 162

6.6 Basic Bus Interface........................................................................................................... 165

6.6.1 Data Bus .............................................................................................................. 165

6.6.2 I/O Pins Used for Basic Bus Interface ................................................................. 165

6.6.3 Basic Timing........................................................................................................166

6.6.4 Wait Control ........................................................................................................ 170

6.6.5 Read Strobe (RD) Timing.................................................................................... 172

6.6.6 Extension of Chip Select (CS) Assertion Period ................................................. 173

6.6.7 DACK Signal Output Timing .............................................................................. 175

6.7 Byte Control SRAM Interface .......................................................................................... 176

6.7.1 Byte Control SRAM Space Setting...................................................................... 176

6.7.2 Data Bus .............................................................................................................. 176

6.7.3 I/O Pins Used for Byte Control SRAM Interface ................................................ 176

6.7.4 Basic Timing........................................................................................................177

6.7.5 Wait Control ........................................................................................................ 180

6.7.6 Read Strobe (RD) ................................................................................................ 182

6.7.7 Extension of Chip Select (CS) Assertion Period ................................................. 182

6.7.8 DACK Signal Output Timing .............................................................................. 182

6.8 Burst ROM Interface ........................................................................................................184

6.8.1 Burst ROM Space Setting.................................................................................... 184

6.8.2 Data Bus .............................................................................................................. 184

6.8.3 I/O Pins Used for Burst ROM Interface............................................................... 185

6.8.4 Basic Timing........................................................................................................186

Rev. 1.00, 03/04, page xii of xl

6.8.5 Wait Control ........................................................................................................188

6.8.6 Read Strobe (RD) Timing.................................................................................... 188

6.8.7 Extension of Chip Select (CS) Assertion Period.................................................. 188

6.9 Address/Data Multiplexed I/O Interface........................................................................... 189

6.9.1 Address/Data Multiplexed I/O Space Setting ...................................................... 189

6.9.2 Address/Data Multiplex....................................................................................... 189

6.9.3 Data Bus...............................................................................................................189

6.9.4 I/O Pins Used for Address/Data Multiplexed I/O Interface................................. 190

6.9.5 Basic Timing........................................................................................................191

6.9.6 Address Cycle Control......................................................................................... 193

6.9.7 Wait Control ........................................................................................................194

6.9.8 Read Strobe (RD) Timing................................................................................... 194

6.9.9 Extension of Chip Select (CS) Assertion Period.................................................. 196

6.9.10 DACK Signal Output Timing .............................................................................. 198

6.10 Idle Cycle.......................................................................................................................... 199

6.10.1 Operation ............................................................................................................. 199

6.10.2 Pin States in Idle Cycle ........................................................................................ 208

6.11 Bus Release....................................................................................................................... 209

6.11.1 Operation ............................................................................................................. 209

6.11.2 Pin States in External Bus Released State............................................................ 210

6.11.3 Transition Timing ................................................................................................211

6.12 Internal Bus....................................................................................................................... 212

6.12.1 Access to Internal Address Space ........................................................................ 212

6.13 Write Data Buffer Function .............................................................................................. 213

6.13.1 Write Data Buffer Function for External Data Bus.............................................. 213

6.13.2 Write Data Buffer Function for Peripheral Modules ...........................................214

6.14 Bus Arbitration.................................................................................................................. 215

6.14.1 Operation ............................................................................................................. 215

6.14.2 Bus Transfer Timing............................................................................................ 216

6.15 Bus Controller Operation in Reset .................................................................................... 217

6.16 Usage Notes ......................................................................................................................218

Section 7 DMA Controller (DMAC) .................................................................219

7.1 Features............................................................................................................................. 219

7.2 Input/Output Pins.............................................................................................................. 221

7.3 Register Descriptions........................................................................................................ 222

7.3.1 DMA Source Address Register (DSAR) .............................................................223

7.3.2 DMA Destination Address Register (DDAR)...................................................... 224

7.3.3 DMA Offset Register (DOFR)............................................................................. 225

7.3.4 DMA Transfer Count Register (DTCR) ..............................................................226

7.3.5 DMA Block Size Register (DBSR) .....................................................................227

7.3.6 DMA Mode Control Register (DMDR)............................................................... 228

7.3.7 DMA Address Control Register (DACR)............................................................ 235

Rev. 1.00, 03/04, page xiii of xl

7.3.8 DMA Module Request Select Register (DMRSR) .............................................. 241

7.4 Transfer Modes................................................................................................................. 241

7.5 Operations......................................................................................................................... 242

7.5.1 Address Modes ....................................................................................................242

7.5.2 Transfer Modes.................................................................................................... 245

7.5.3 Activation Sources............................................................................................... 250

7.5.4 Bus Access Modes............................................................................................... 252

7.5.5 Extended Repeat Area Function .......................................................................... 254

7.5.6 Address Update Function using Offset ................................................................ 256

7.5.7 Register during DMA Transfer............................................................................ 260

7.5.8 Priority of Channels............................................................................................. 265

7.5.9 DMA Basic Bus Cycle......................................................................................... 266

7.5.10 Bus Cycles in Dual Address Mode ...................................................................... 267

7.5.11 Bus Cycles in Single Address Mode.................................................................... 276

7.6 DMA Transfer End........................................................................................................... 281

7.7 Relationship among DMAC and Other Bus Masters ........................................................ 283

7.7.1 CPU Priority Control Function Over DMAC ...................................................... 283

7.7.2 Bus Arbitration among DMAC and Other Bus Masters ...................................... 284

7.8 Interrupt Sources...............................................................................................................285

7.9 Notes on Usage................................................................................................................. 288

Section 8 Data Transfer Controller (DTC)........................................................ 289

8.1 Features............................................................................................................................. 289

8.2 Register Descriptions........................................................................................................ 291

8.2.1 DTC Mode Register A (MRA) ............................................................................ 292

8.2.2 DTC Mode Register B (MRB)............................................................................. 293

8.2.3 DTC Source Address Register (SAR).................................................................. 294

8.2.4 DTC Destination Address Register (DAR).......................................................... 294

8.2.5 DTC Transfer Count Register A (CRA) .............................................................. 295

8.2.6 DTC Transfer Count Register B (CRB)............................................................... 295

8.2.7 DTC Enable Registers A to H (DTCERA to DTCERE)...................................... 296

8.2.8 DTC Control Register (DTCCR)......................................................................... 297

8.2.9 DTC Vector Base Register (DTCVBR)............................................................... 298

8.3 Activation Sources............................................................................................................ 299

8.4 Location of Transfer Information and DTC Vector Table................................................ 299

8.5 Operation .......................................................................................................................... 303

8.5.1 Bus Cycle Division .............................................................................................. 305

8.5.2 Transfer Information Read Skip Function ........................................................... 307

8.5.3 Transfer Information Writeback Skip Function................................................... 308

8.5.4 Normal Transfer Mode ........................................................................................ 308

8.5.5 Repeat Transfer Mode .........................................................................................309

8.5.6 Block Transfer Mode........................................................................................... 311

8.5.7 Chain Transfer ..................................................................................................... 312

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8.5.8 Operation Timing................................................................................................. 313

8.5.9 Number of DTC Execution Cycles ...................................................................... 315

8.5.10 DTC Bus Release Timing .................................................................................... 316

8.5.11 DTC Priority Level Control to the CPU ..............................................................316

8.6 DTC Activation by Interrupt............................................................................................. 317

8.7 Examples of Use of the DTC............................................................................................ 318

8.7.1 Normal Transfer Mode ........................................................................................318

8.7.2 Chain Transfer ..................................................................................................... 318

8.7.3 Chain Transfer when Counter = 0........................................................................ 319

8.8 Interrupt Sources...............................................................................................................321

8.9 Usage Notes...................................................................................................................... 321

8.9.1 Module Stop Mode Setting .................................................................................. 321

8.9.2 On-Chip RAM ..................................................................................................... 321

8.9.3 DMAC Transfer End Interrupt............................................................................. 321

8.9.4 DTCE Bit Setting................................................................................................. 321

8.9.5 Chain Transfer ..................................................................................................... 322

8.9.6 Transfer Information Start Address, Source Address,

and Destination Address ......................................................................................322

8.9.7 Transfer Information Modification ...................................................................... 322

8.9.8 Endian Format...................................................................................................... 322

Section 9 I/O Ports.............................................................................................323

9.1 Register Descriptions........................................................................................................ 329

9.1.1 Data Direction Register (PnDDR) (n = 1 to 3, 6, A, B, D to F, H, and I)............ 330

9.1.2 Data Register (PnDR) (n = 1 to 3, 6, A, B, D to F, H, and I)............................... 330

9.1.3 Port Register (PORTn) (n = 1 to 3, 5, 6, A, B, D to F, H, and I) .........................331

9.1.4 Input Buffer Control Register

(PnICR) (n = 1 to 3, 5, 6, A, B, D to F, H, and I) ................................................331

9.1.5 Pull-Up MOS Control Register (PnPCR) (n = D to F, H, and I)..........................332

9.1.6 Open-Drain Control Register (PnODR) (n = 2 and F)......................................... 333

9.2 Output Buffer Control....................................................................................................... 334

9.2.1 Port 1....................................................................................................................334

9.2.2 Port 2....................................................................................................................337

9.2.3 Port 3....................................................................................................................340

9.2.4 Port 5....................................................................................................................343

9.2.5 Port 6....................................................................................................................343

9.2.6 Port A................................................................................................................... 345

9.2.7 Port B................................................................................................................... 349

9.2.8 Port D................................................................................................................... 351

9.2.9 Port E................................................................................................................... 352

9.2.10 Port F ................................................................................................................... 352

9.2.11 Port H................................................................................................................... 356

9.2.12 Port I ....................................................................................................................356

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9.3 Port Function Controller................................................................................................... 362

9.3.1 Port Function Control Register 0 (PFCR0).......................................................... 362

9.3.2 Port Function Control Register 1 (PFCR1).......................................................... 363

9.3.3 Port Function Control Register 2 (PFCR2).......................................................... 364

9.3.4 Port Function Control Register 4 (PFCR4).......................................................... 365

9.3.5 Port Function Control Register 6 (PFCR6).......................................................... 367

9.3.6 Port Function Control Register 7 (PFCR7).......................................................... 368

9.3.7 Port Function Control Register 9 (PFCR9).......................................................... 369

9.3.8 Port Function Control Register B (PFCRB) ........................................................370

9.3.9 Port Function Control Register C (PFCRC) ........................................................371

9.4 Usage Notes...................................................................................................................... 373

9.4.1 Notes on Input Buffer Control Register (ICR) Setting ........................................373

9.4.2 Notes on Port Function Control Register (PFCR) Settings.................................. 373

Section 10 16-Bit Timer Pulse Unit (TPU) .......................................................375

10.1 Features............................................................................................................................. 375

10.2 Input/Output Pins.............................................................................................................. 379

10.3 Register Descriptions........................................................................................................ 380

10.3.1 Timer Control Register (TCR)............................................................................. 382

10.3.2 Timer Mode Register (TMDR)............................................................................ 387

10.3.3 Timer I/O Control Register (TIOR)..................................................................... 388

10.3.4 Timer Interrupt Enable Register (TIER).............................................................. 406

10.3.5 Timer Status Register (TSR)................................................................................ 408

10.3.6 Timer Counter (TCNT)........................................................................................ 411

10.3.7 Timer General Register (TGR) ............................................................................ 411

10.3.8 Timer Start Register (TSTR) ............................................................................... 412

10.3.9 Timer Synchronous Register (TSYR).................................................................. 413

10.4 Operation ..........................................................................................................................414

10.4.1 Basic Functions.................................................................................................... 414

10.4.2 Synchronous Operation........................................................................................ 420

10.4.3 Buffer Operation .................................................................................................. 422

10.4.4 Cascaded Operation ............................................................................................. 426

10.4.5 PWM Modes ........................................................................................................ 428

10.4.6 Phase Counting Mode.......................................................................................... 433

10.5 Interrupt Sources...............................................................................................................439

10.6 DTC Activation................................................................................................................. 441

10.7 DMAC Activation............................................................................................................. 441

10.8 A/D Converter Activation................................................................................................. 441

10.9 Operation Timing.............................................................................................................. 442

10.9.1 Input/Output Timing ............................................................................................ 442

10.9.2 Interrupt Signal Timing ....................................................................................... 446

10.10 Usage Notes ......................................................................................................................449

10.10.1 Module Stop Mode Setting.................................................................................. 449

Rev. 1.00, 03/04, page xvi of xl

10.10.2 Input Clock Restrictions ......................................................................................449

10.10.3 Caution on Cycle Setting ..................................................................................... 450

10.10.4 Conflict between TCNT Write and Clear Operations.......................................... 450

10.10.5 Conflict between TCNT Write and Increment Operations ..................................451

10.10.6 Conflict between TGR Write and Compare Match..............................................451

10.10.7 Conflict between Buffer Register Write and Compare Match ............................. 452

10.10.8 Conflict between TGR Read and Input Capture .................................................. 452

10.10.9 Conflict between TGR Write and Input Capture .................................................453

10.10.10 Conflict between Buffer Register Write and Input Capture............................... 454

10.10.11 Conflict between Overflow/Underflow and Counter Clearing ..........................455

10.10.12 Conflict between TCNT Write and Overflow/Underflow .................................455

10.10.13 Multiplexing of I/O Pins.................................................................................... 456

10.10.14 Interrupts and Module Stop Mode ..................................................................... 456

Section 11 Programmable Pulse Generator (PPG) ............................................457

11.1 Features............................................................................................................................. 457

11.2 Input/Output Pins.............................................................................................................. 458

11.3 Register Descriptions........................................................................................................ 459

11.3.1 Next Data Enable Registers H, L (NDERH, NDERL) ........................................ 459

11.3.2 Output Data Registers H, L (PODRH, PODRL).................................................. 461

11.3.3 Next Data Registers H, L (NDRH, NDRL) ......................................................... 462

11.3.4 PPG Output Control Register (PCR) ................................................................... 465

11.3.5 PPG Output Mode Register (PMR) ..................................................................... 466

11.4 Operation ..........................................................................................................................468

11.4.1 Output Timing...................................................................................................... 468

11.4.2 Sample Setup Procedure for Normal Pulse Output.............................................. 469

11.4.3 Example of Normal Pulse Output (Example of 5-Phase Pulse Output) ............... 470

11.4.4 Non-Overlapping Pulse Output............................................................................ 471

11.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output .............................. 473

11.4.6 Example of Non-Overlapping Pulse Output

(Example of 4-Phase Complementary Non-Overlapping Pulse Output) .............474

11.4.7 Inverted Pulse Output ..........................................................................................476

11.4.8 Pulse Output Triggered by Input Capture ............................................................ 477

11.5 Usage Notes ......................................................................................................................478

11.5.1 Module Stop Mode Setting .................................................................................. 478

11.5.2 Operation of Pulse Output Pins............................................................................ 478

Section 12 8-Bit Timers (TMR).........................................................................479

12.1 Features............................................................................................................................. 479

12.2 Input/Output Pins.............................................................................................................. 482

12.3 Register Descriptions........................................................................................................ 483

12.3.1 Timer Counter (TCNT)........................................................................................ 484

12.3.2 Time Constant Register A (TCORA)................................................................... 484

Rev. 1.00, 03/04, page xvii of xl

12.3.3 Time Constant Register B (TCORB) ................................................................... 485

12.3.4 Timer Control Register (TCR)............................................................................ 485

12.3.5 Timer Counter Control Register (TCCR) ........................................................... 487

12.3.6 Timer Control/Status Register (TCSR)................................................................ 489

12.4 Operation ..........................................................................................................................493

12.4.1 Pulse Output ........................................................................................................ 493

12.4.2 Reset Input ........................................................................................................... 494

12.5 Operation Timing.............................................................................................................. 495

12.5.1 TCNT Count Timing ........................................................................................... 495

12.5.2 Timing of CMFA and CMFB Setting at Compare Match ................................... 496

12.5.3 Timing of Timer Output at Compare Match........................................................ 496

12.5.4 Timing of Counter Clear by Compare Match ...................................................... 497

12.5.5 Timing of TCNT External Reset.......................................................................... 497

12.5.6 Timing of Overflow Flag (OVF) Setting .............................................................498

12.6 Operation with Cascaded Connection............................................................................... 499

12.6.1 16-Bit Counter Mode ........................................................................................... 499

12.6.2 Compare Match Count Mode .............................................................................. 499

12.7 Interrupt Sources...............................................................................................................500

12.7.1 Interrupt Sources and DTC Activation ................................................................ 500

12.7.2 A/D Converter Activation.................................................................................... 500

12.8 Usage Notes ...................................................................................................................... 501

12.8.1 Notes on Setting Cycle ........................................................................................ 501

12.8.2 Conflict between TCNT Write and Clear ............................................................501

12.8.3 Conflict between TCNT Write and Increment..................................................... 502

12.8.4 Conflict between TCOR Write and Compare Match........................................... 503

12.8.5 Conflict between Compare Matches A and B...................................................... 503

12.8.6 Switching of Internal Clocks and TCNT Operation ............................................ 504

12.8.7 Mode Setting with Cascaded Connection ............................................................505

12.8.8 Module Stop Mode Setting .................................................................................. 505

12.8.9 Interrupts in Module Stop Mode.......................................................................... 506

Section 13 Watchdog Timer (WDT) .................................................................507

13.1 Features............................................................................................................................. 507

13.2 Input/Output Pin ............................................................................................................... 508

13.3 Register Descriptions........................................................................................................ 508

13.3.1 Timer Counter (TCNT)........................................................................................ 508

13.3.2 Timer Control/Status Register (TCSR)................................................................ 508

13.3.3 Reset Control/Status Register (RSTCSR)............................................................ 510

13.4 Operation ..........................................................................................................................511

13.4.1 Watchdog Timer Mode ........................................................................................ 511

13.4.2 Interval Timer Mode............................................................................................ 512

13.5 Interrupt Source ................................................................................................................513

13.6 Usage Notes ...................................................................................................................... 513

Rev. 1.00, 03/04, page xviii of xl

13.6.1 Notes on Register Access..................................................................................... 513

13.6.2 Conflict between Timer Counter (TCNT) Write and Increment.......................... 514

13.6.3 Changing Values of Bits CKS2 to CKS0............................................................. 515

13.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 515

13.6.5 Internal Reset in Watchdog Timer Mode............................................................. 515

13.6.6 System Reset by WDTOVF Signal...................................................................... 515

13.6.7 Transition to Watchdog Timer Mode or Software Standby Mode....................... 516

Section 14 Serial Communication Interface (SCI) ............................................517

14.1 Features............................................................................................................................. 517

14.2 Input/Output Pins.............................................................................................................. 519

14.3 Register Descriptions........................................................................................................ 519

14.3.1 Receive Shift Register (RSR) .............................................................................. 521

14.3.2 Receive Data Register (RDR) .............................................................................. 521

14.3.3 Transmit Data Register (TDR)............................................................................. 521

14.3.4 Transmit Shift Register (TSR) ............................................................................. 521

14.3.5 Serial Mode Register (SMR) ............................................................................... 522

14.3.6 Serial Control Register (SCR) ............................................................................. 525

14.3.7 Serial Status Register (SSR) ................................................................................529

14.3.8 Smart Card Mode Register (SCMR) .................................................................... 536

14.3.9 Bit Rate Register (BRR) ...................................................................................... 537

14.3.10 Serial Extended Mode Register (SEMR)............................................................. 544

14.4 Operation in Asynchronous Mode ....................................................................................546

14.4.1 Data Transfer Format........................................................................................... 547

14.4.2 Receive Data Sampling Timing

and Reception Margin in Asynchronous Mode ...................................................548

14.4.3 Clock.................................................................................................................... 549

14.4.4 SCI Initialization (Asynchronous Mode) .............................................................550

14.4.5 Serial Data Transmission (Asynchronous Mode) ................................................ 551

14.4.6 Serial Data Reception (Asynchronous Mode)...................................................... 553

14.5 Multiprocessor Communication Function......................................................................... 557

14.5.1 Multiprocessor Serial Data Transmission ............................................................558

14.5.2 Multiprocessor Serial Data Reception ................................................................. 559

14.6 Operation in Clocked Synchronous Mode........................................................................ 562

14.6.1 Clock.................................................................................................................... 562

14.6.2 SCI Initialization (Clocked Synchronous Mode) ................................................. 563

14.6.3 Serial Data Transmission (Clocked Synchronous Mode) ....................................564

14.6.4 Serial Data Reception (Clocked Synchronous Mode).......................................... 566

14.6.5 Simultaneous Serial Data Transmission and Reception

(Clocked Synchronous Mode) .............................................................................567

14.7 Operation in Smart Card Interface Mode.......................................................................... 569

14.7.1 Sample Connection ..............................................................................................569

14.7.2 Data Format (Except in Block Transfer Mode) ...................................................570

Rev. 1.00, 03/04, page xix of xl

14.7.3 Block Transfer Mode ........................................................................................... 571

14.7.4 Receive Data Sampling Timing and Reception Margin ...................................... 572

14.7.5 Initialization ......................................................................................................... 573

14.7.6 Data Transmission (Except in Block Transfer Mode) ......................................... 574

14.7.7 Serial Data Reception (Except in Block Transfer Mode) .................................... 577

14.7.8 Clock Output Control........................................................................................... 578

14.8 Interrupt Sources...............................................................................................................580

14.8.1 Interrupts in Normal Serial Communication Interface Mode .............................. 580

14.8.2 Interrupts in Smart Card Interface Mode ............................................................. 581

14.9 Usage Notes ...................................................................................................................... 582

14.9.1 Module Stop Mode Setting .................................................................................. 582

14.9.2 Break Detection and Processing .......................................................................... 582

14.9.3 Mark State and Break Detection .......................................................................... 582

14.9.4 Receive Error Flags and Transmit Operations

(Clocked Synchronous Mode Only) .................................................................... 582

14.9.5 Relation between Writing to TDR and TDRE Flag ............................................. 582

14.9.6 Restrictions on Using DMAC or DTC................................................................. 583

14.9.7 SCI Operations during Mode Transitions ............................................................ 583

Section 15 A/D Converter ................................................................................. 587

15.1 Features............................................................................................................................. 587

15.2 Input/Output Pins.............................................................................................................. 589

15.3 Register Descriptions........................................................................................................ 589

15.3.1 A/D Data Registers A to H (ADDRA to ADDRH) ............................................. 590

15.3.2 A/D Control/Status Register (ADCSR) ...............................................................591

15.3.3 A/D Control Register (ADCR) ............................................................................ 593

15.4 Operation ..........................................................................................................................594

15.4.1 Single Mode......................................................................................................... 594

15.4.2 Scan Mode ...........................................................................................................595

15.4.3 Input Sampling and A/D Conversion Time ......................................................... 597

15.4.4 External Trigger Input Timing............................................................................. 598

15.5 Interrupt Source ................................................................................................................599

15.6 A/D Conversion Accuracy Definitions............................................................................. 599

15.7 Usage Notes ...................................................................................................................... 601

15.7.1 Module Stop Mode Setting .................................................................................. 601

15.7.2 Permissible Signal Source Impedance ................................................................. 601

15.7.3 Influences on Absolute Accuracy ........................................................................ 601

15.7.4 Setting Range of Analog Power Supply and Other Pins...................................... 602

15.7.5 Notes on Board Design ........................................................................................ 602

15.7.6 Notes on Noise Countermeasures ........................................................................ 602

15.7.7 A/D Input Hold Function in Software Standby Mode .........................................603

Rev. 1.00, 03/04, page xx of xl

Section 16 D/A Converter..................................................................................605

16.1 Features............................................................................................................................. 605

16.2 Input/Output Pins.............................................................................................................. 606

16.3 Register Descriptions........................................................................................................ 606

16.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)............................................ 606

16.3.2 D/A Control Register 01 (DACR01) ................................................................... 607

16.4 Operation ..........................................................................................................................609

16.5 Usage Notes ......................................................................................................................610

16.5.1 Module Stop Mode Setting .................................................................................. 610

16.5.2 D/A Output Hold Function in Software Standby Mode.......................................610

Section 17 RAM ................................................................................................611

Section 18 Flash Memory (0.18-µm F-ZTAT Version) ....................................613

18.1 Features............................................................................................................................. 613

18.2 Mode Transition Diagram................................................................................................. 615

18.3 Memory MAT Configuration............................................................................................ 617

18.4 Block Structure .................................................................................................................618

18.5 Programming/Erasing Interface ........................................................................................ 619

18.6 Input/Output Pins.............................................................................................................. 621

18.7 Register Descriptions........................................................................................................ 621

18.7.1 Programming/Erasing Interface Registers ...........................................................622

18.7.2 Programming/Erasing Interface Parameters ........................................................629

18.7.3 RAM Emulation Register (RAMER)................................................................... 641

18.8 On-Board Programming Mode .........................................................................................642

18.8.1 Boot Mode ...........................................................................................................642

18.8.2 User Program Mode............................................................................................. 646

18.8.3 User Boot Mode................................................................................................... 656

18.8.4 On-Chip Program and Storable Area for Program Data ...................................... 660

18.9 Protection.......................................................................................................................... 665

18.9.1 Hardware Protection ............................................................................................665

18.9.2 Software Protection.............................................................................................. 666

18.9.3 Error Protection.................................................................................................... 666

18.10 Flash Memory Emulation Using RAM ............................................................................. 668

18.11 Switching between User MAT and User Boot MAT ........................................................ 671

18.12 Programmer Mode ............................................................................................................672

18.13 Standard Serial Communication Interface Specifications for Boot Mode ........................672

18.14 Usage Notes ......................................................................................................................699

Section 19 Clock Pulse Generator .....................................................................701

19.1 Register Description.......................................................................................................... 702

19.1.1 System Clock Control Register (SCKCR) ........................................................... 702

Rev. 1.00, 03/04, page xxi of xl

19.2 Oscillator........................................................................................................................... 704

19.2.1 Connecting Crystal Resonator ............................................................................. 704

19.2.2 External Clock Input ............................................................................................ 705

19.3 PLL Circuit ....................................................................................................................... 706

19.4 Frequency Divider ............................................................................................................706

19.5 Usage Notes ...................................................................................................................... 706

19.5.1 Notes on Clock Pulse Generator .......................................................................... 706

19.5.2 Notes on Resonator.............................................................................................. 707

19.5.3 Notes on Board Design ........................................................................................ 708

Section 20 Power-Down Modes........................................................................ 709

20.1 Features............................................................................................................................. 709

20.2 Register Descriptions........................................................................................................ 712

20.2.1 Standby Control Register (SBYCR) .................................................................... 712

20.2.2 Module Stop Control Registers A and B (MSTPCRA and MSTPCRB) ............. 714

20.2.3 Module Stop Control Register C (MSTPCRC).................................................... 717

20.3 Multi-Clock Function ....................................................................................................... 718

20.4 Sleep Mode ....................................................................................................................... 719

20.4.1 Transition to Sleep Mode..................................................................................... 719

20.4.2 Clearing Sleep Mode ........................................................................................... 719

20.5 Software Standby Mode.................................................................................................... 720

20.5.1 Transition to Software Standby Mode ................................................................. 720

20.5.2 Clearing Software Standby Mode ........................................................................ 720

20.5.3 Setting Oscillation Settling Time after Clearing Software Standby Mode ..........721

20.5.4 Software Standby Mode Application Example.................................................... 723

20.6 Hardware Standby Mode .................................................................................................. 724

20.6.1 Transition to Hardware Standby Mode................................................................ 724

20.6.2 Clearing Hardware Standby Mode....................................................................... 724

20.6.3 Hardware Standby Mode Timing......................................................................... 724

20.6.4 Timing Sequence at Power-On ............................................................................ 725

20.7 Module Stop Mode ...........................................................................................................726

20.7.1 Module Stop Mode .............................................................................................. 726

20.7.2 All-Module-Clock-Stop Mode............................................................................. 726

20.8 Bφ Clock Output Control.................................................................................................. 727

20.9 Usage Notes ...................................................................................................................... 728

20.9.1 I/O Port Status...................................................................................................... 728

20.9.2 Current Consumption during Oscillation Settling Standby Period ......................728

20.9.3 Module Stop Mode of DMAC or DTC................................................................ 728

20.9.4 On-Chip Peripheral Module Interrupts ................................................................ 728

20.9.5 Writing to MSTPCRA, MSTPCRB, and MSTPCRC .......................................... 728

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Section 21 List of Registers ...............................................................................729

21.1 Register Addresses (Address Order)................................................................................. 730

21.2 Register Bits...................................................................................................................... 740

21.3 Register States in Each Operating Mode ..........................................................................753

Section 22 Electrical Characteristics .................................................................763

22.1 Absolute Maximum Ratings ............................................................................................. 763

22.2 DC Characteristics ............................................................................................................ 764

22.3 AC Characteristics ............................................................................................................ 767

22.3.1 Clock Timing ....................................................................................................... 768

22.3.2 Control Signal Timing .........................................................................................770

22.3.3 Bus Timing .......................................................................................................... 771

22.3.4 DMAC Timing..................................................................................................... 786

22.3.5 Timing of On-Chip Peripheral Modules ..............................................................789

22.4 A/D Conversion Characteristics........................................................................................ 792

22.5 D/A Conversion Characteristics........................................................................................ 793

22.6 Flash Memory Characteristics ..........................................................................................794

Appendix .........................................................................................................795

A. Port States in Each Pin State............................................................................................. 795

B. Product Lineup..................................................................................................................800

C. Package Dimensions .........................................................................................................801

Index .........................................................................................................805

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Rev. 1.00, 03/04, page xxiv of xl

Figures

Section 1 Overview

Figure 1.1 Block Diagram ..............................................................................................................2

Figure 1.2 Pin Assignments............................................................................................................ 3

Section 2 CPU

Figure 2.1 CPU Operating Modes ................................................................................................19

Figure 2.2 Exception Vector Table (Normal Mode)..................................................................... 20

Figure 2.3 Stack Structure (Normal Mode) ..................................................................................20

Figure 2.4 Exception Vector Table (Middle and Advanced Modes)............................................ 22

Figure 2.5 Stack Structure (Middle and Advanced Modes).......................................................... 23

Figure 2.6 Exception Vector Table (Maximum Modes)............................................................... 24

Figure 2.7 Stack Structure (Maximum Mode).............................................................................. 24

Figure 2.8 Memory Map............................................................................................................... 25

Figure 2.9 CPU Registers ............................................................................................................. 26

Figure 2.10 Usage of General Registers....................................................................................... 27

Figure 2.11 Stack.......................................................................................................................... 28

Figure 2.12 General Register Data Formats .................................................................................32

Figure 2.13 Memory Data Formats...............................................................................................33

Figure 2.14 Instruction Formats.................................................................................................... 50

Figure 2.15 Branch Address Specification in Memory Indirect Mode......................................... 55

Figure 2.16 State Transitions........................................................................................................ 60

Section 3 MCU Operating Modes

Figure 3.1 Address Map (1).......................................................................................................... 69

Figure 3.2 Address Map (2).......................................................................................................... 70

Section 4 Exception Handling

Figure 4.1 Reset Sequence (On-chip ROM Enabled Advanced Mode)........................................75

Figure 4.2 Reset Sequence

(16-Bit External Access in On-chip ROM Disabled Advanced Mode) ......................76

Figure 4.3 Stack Status after Exception Handling........................................................................ 83

Figure 4.4 Operation when SP Value Is Odd................................................................................ 84

Section 5 Interrupt Controller

Figure 5.1 Block Diagram of Interrupt Controller........................................................................ 86

Figure 5.2 Block Diagram of Interrupts IRQn............................................................................ 101

Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0... 107
Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2... 109

Figure 5.5 Interrupt Exception Handling.................................................................................... 110

Figure 5.6 Block Diagram of DTC, DMAC, and Interrupt Controller ....................................... 113

Figure 5.7 Conflict between Interrupt Generation and Disabling............................................... 118

Rev. 1.00, 03/04, page xxv of xl

Section 6 Bus Controller (BSC)

Figure 6.1 Block Diagram of Bus Controller..............................................................................123

Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space).......................... 133

Figure 6.3 CS and Address Assertion Period Extension

(Example of Basic Bus Interface, 3-State Access Space, and RDNn = 0)................. 135

Figure 6.4 Internal Bus Configuration........................................................................................ 145

Figure 6.5 System Clock: External Bus Clock = 4:1, External 2-State Access .......................... 147

Figure 6.6 System Clock: External Bus Clock = 2:1, External 3-State Access .......................... 148

Figure 6.7 Address Space Area Division.................................................................................... 152

Figure 6.8 CSn Signal Output Timing (n = 0 to 7)..................................................................... 153

Figure 6.9 Timing When CS Signal is Output to the Same Pin.................................................. 154

Figure 6.10 Access Sizes and Data Alignment Control for 8-Bit Access Space

(Big Endian) ...........................................................................................................162

Figure 6.11 Access Sizes and Data Alignment Control for 8-Bit Access Space

(Little Endian)......................................................................................................... 163

Figure 6.12 Access Sizes and Data Alignment Control for 16-Bit Access Space

(Big Endian) ...........................................................................................................164

Figure 6.13 Access Sizes and Data Alignment Control for 16-Bit Access Space

(Little Endian).......................................................................................................... 164

Figure 6.14 16-Bit 2-State Access Space Bus Timing (Byte Access for Even Address)........... 166

Figure 6.15 16-Bit 2-State Access Space Bus Timing (Byte Access for Odd Address)............ 167

Figure 6.16 16-Bit 2-State Access Space Bus Timing (Word Access for Even Address)......... 168

Figure 6.17 16-Bit 3-State Access Space Bus Timing (Byte Access for Even Address)........... 169

Figure 6.18 16-Bit 3-State Access Space Bus Timing (Word Access for Odd Address) ..........170

Figure 6.19 16-Bit 3-State Access Space Bus Timing (Word Access for Even Address)......... 171

Figure 6.20 Example of Wait Cycle Insertion Timing................................................................ 173

Figure 6.21 Example of Read Strobe Timing ............................................................................. 174

Figure 6.22 Example of Timing when Chip Select Assertion Period is Extended ..................... 176

Figure 6.23 DACK Signal Output Timing.................................................................................. 177

Figure 6.24 16-Bit 2-State Access Space Bus Timing................................................................ 180

Figure 6.25 16-Bit 3-State Access Space Bus Timing................................................................ 181

Figure 6.26 Example of Wait Cycle Insertion Timing................................................................ 183

Figure 6.27 DACK Signal Output Timing.................................................................................. 185

Figure 6.28 Example of Burst ROM Access Timing (ASTn = 1, Two Burst Cycles)................ 188

Figure 6.29 Example of Burst ROM Access Timing (ASTn = 0, One Burst Cycle) .................. 189

Figure 6.30 8-Bit Access Space Access Timing (ABWHn = 1, ABWLn = 1) ........................... 193

Figure 6.31 16-Bit Access Space Access Timing (ABWHn = 0, ABWLn = 1)......................... 194

Figure 6.32 Access Timing of 3 Address Cycles (ADDEX = 1)................................................ 195

Figure 6.33 Read Strobe Timing ................................................................................................197

Figure 6.34 Chip Select (CS) Assertion Period Extension Timing in Data Cycle...................... 198

Figure 6.35 Consecutive Read Accesses to Same Area

(Address/Data Multiplexed I/O Space).................................................................... 199

Figure 6.36 DACK Signal Output Timing.................................................................................. 200

Rev. 1.00, 03/04, page xxvi of xl

Figure 6.37 Example of Idle Cycle Operation (Consecutive Reads in Different Areas) ............203

Figure 6.38 Example of Idle Cycle Operation (Write after Read).............................................. 204

Figure 6.39 Example of Idle Cycle Operation (Read after Write).............................................. 205

Figure 6.40 Example of Idle Cycle Operation (Write after Single Address Transfer Write)...... 206

Figure 6.41 Idle Cycle Insertion Example.................................................................................. 207

Figure 6.42 Relationship between Chip Select (CS) and Read (RD)..........................................208

Figure 6.43 Bus Released State Transition Timing ....................................................................213

Figure 6.44 Example of Timing when Write Data Buffer Function is Used .............................. 215

Figure 6.45 Example of Timing when Peripheral Module

Write Data Buffer Function is Used ....................................................................... 216

Section 7 DMA Controller (DMAC)

Figure 7.1 Block Diagram of DMAC ......................................................................................... 220

Figure 7.2 Example of Signal Timing in Dual Address Mode....................................................242

Figure 7.3 Operations in Dual Address Mode ............................................................................ 243

Figure 7.4 Data Flow in Single Address Mode........................................................................... 244

Figure 7.5 Example of Signal Timing in Single Address Mode................................................. 244

Figure 7.6 Operations in Single Address Mode.......................................................................... 245

Figure 7.7 Example of Signal Timing in Normal Transfer Mode............................................... 245

Figure 7.8 Operations in Normal Transfer Mode .......................................................................246

Figure 7.9 Operations in Repeat Transfer Mode.........................................................................247

Figure 7.10 Operations in Block Transfer Mode ........................................................................ 248

Figure 7.11 Operation in Single Address Mode in Block Transfer Mode

(Block Area Specified) ............................................................................................248

Figure 7.12 Operation in Dual Address Mode in Block Transfer Mode

(Block Area Not Specified) .................................................................................... 249

Figure 7.13 Example of Timing in Cycle Stealing Mode ........................................................... 252

Figure 7.14 Example of Timing in Burst Mode.......................................................................... 253

Figure 7.15 Example of Extended Repeat Area Operation......................................................... 254

Figure 7.16 Example of Extended Repeat Area Function in Block Transfer Mode ................... 255

Figure 7.17 Address Update Method.......................................................................................... 256

Figure 7.18 Operation of Offset Addition................................................................................... 257

Figure 7.19 XY Conversion Operation Using Offset Addition in Repeat Transfer Mode..........258

Figure 7.20 XY Conversion Flowchart Using Offset Addition in Repeat Transfer Mode .........259

Figure 7.21 Procedure for Changing Register Setting For Channel being Transferred.............. 263

Figure 7.22 Example of Timing for Channel Priority................................................................. 265

Figure 7.23 Example of Bus Timing of DMA Transfer.............................................................. 266

Figure 7.24 Example of Transfer in Normal Transfer Mode by Cycle Stealing......................... 267

Figure 7.25 Example of Transfer in Normal Transfer Mode by Cycle Stealing

(Transfer Source DSAR = Odd Address and Source Address Increment).............. 268

Figure 7.26 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer

Destination DDAR = Odd Address and Destination Address Decrement)............. 268

Figure 7.27 Example of Transfer in Normal Transfer Mode by Burst Access ........................... 269

Rev. 1.00, 03/04, page xxvii of xl

Figure 7.28 Example of Transfer in Block Transfer Mode......................................................... 270

Figure 7.29 Example of Transfer in Normal Transfer Mode Activated

by DREQ Falling Edge........................................................................................... 271

Figure 7.30 Example of Transfer in Block Transfer Mode Activated

by DREQ Falling Edge........................................................................................... 272

Figure 7.31 Example of Transfer in Normal Transfer Mode Activated

by DREQ Low Level.............................................................................................. 273

Figure 7.32 Example of Transfer in Block Transfer Mode Activated

by DREQ Low Level............................................................................................... 274

Figure 7.33 Example of Transfer in Normal Transfer Mode Activated

by DREQ Low Level with NRD = 1 ......................................................................275

Figure 7.34 Example of Transfer in Single Address Mode (Byte Read) .................................... 276

Figure 7.35 Example of Transfer in Single Address Mode (Byte Write) .................................... 277

Figure 7.36 Example of Transfer in Single Address Mode Activated

by DREQ Falling Edge........................................................................................... 278

Figure 7.37 Example of Transfer in Single Address Mode Activated by DREQ Low Level..... 279

Figure 7.38 Example of Transfer in Single Address Mode Activated

by DREQ Low Level with NRD = 1 ......................................................................280

Figure 7.39 Interrupt and Interrupt Sources................................................................................ 287

Figure 7.40 Procedure Example of Resuming Transfer by Clearing Interrupt Source ............... 287

Section 8 Data Transfer Controller (DTC)

Figure 8.1 Block Diagram of DTC............................................................................................. 292

Figure 8.2 Transfer Information on Data Area........................................................................... 301

Figure 8.3 Correspondence between DTC Vector Address and Transfer Information............... 302

Figure 8.4 Flowchart of DTC Operation .................................................................................... 306

Figure 8.5 Bus Cycle Division Example .................................................................................... 308

Figure 8.6 Transfer Information Read Skip Timing................................................................... 309

Figure 8.7 Memory Map in Normal Transfer Mode................................................................... 311

Figure 8.8 Memory Map in Repeat Transfer Mode

(When Transfer Source is Specified as Repeat Area)................................................ 312

Figure 8.9 Memory Map in Block Transfer Mode

(When Transfer Destination is Specified as Block Area) .......................................... 313

Figure 8.10 Operation of Chain Transfer.................................................................................... 314

Figure 8.11 DTC Operation Timing (Example of Short Address Mode

in Normal Transfer Mode or Repeat Transfer Mode)............................................. 315

Figure 8.12 DTC Operation Timing (Example of Short Address Mode

in Block Transfer Mode with Block Size of 2)....................................................... 315

Figure 8.13 DTC Operation Timing (Example of Short Address Mode in Chain Transfer) ...... 316

Figure 8.14 DTC Operation Timing (Example of Full Address Mode

in Normal Transfer Mode or Repeat Transfer Mode)............................................. 316

Figure 8.15 DTC with Interrupt Activation................................................................................ 319

Figure 8.16 Chain Transfer when Counter = 0 ........................................................................... 322

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Section 10 16-Bit Timer Pulse Unit (TPU)

Figure 10.1 Block Diagram of TPU............................................................................................ 380

Figure 10.2 Example of Counter Operation Setting Procedure .................................................. 416

Figure 10.3 Free-Running Counter Operation............................................................................ 417

Figure 10.4 Periodic Counter Operation..................................................................................... 418

Figure 10.5 Example of Setting Procedure for Waveform Output by Compare Match.............. 418

Figure 10.6 Example of 0-Output/1-Output Operation............................................................... 419

Figure 10.7 Example of Toggle Output Operation ..................................................................... 419

Figure 10.8 Example of Setting Procedure for Input Capture Operation....................................420

Figure 10.9 Example of Input Capture Operation.......................................................................421

Figure 10.10 Example of Synchronous Operation Setting Procedure ........................................422

Figure 10.11 Example of Synchronous Operation...................................................................... 423

Figure 10.12 Compare Match Buffer Operation......................................................................... 424

Figure 10.13 Input Capture Buffer Operation.............................................................................424

Figure 10.14 Example of Buffer Operation Setting Procedure................................................... 425

Figure 10.15 Example of Buffer Operation (1)...........................................................................426

Figure 10.16 Example of Buffer Operation (2)...........................................................................427

Figure 10.17 Example of Cascaded Operation Setting Procedure.............................................. 428

Figure 10.18 Example of Cascaded Operation (1)...................................................................... 429

Figure 10.19 Example of Cascaded Operation (2)...................................................................... 429

Figure 10.20 Example of PWM Mode Setting Procedure ..........................................................432

Figure 10.21 Example of PWM Mode Operation (1)................................................................. 432

Figure 10.22 Example of PWM Mode Operation (2)................................................................. 433

Figure 10.23 Example of PWM Mode Operation (3)................................................................. 434

Figure 10.24 Example of Phase Counting Mode Setting Procedure........................................... 435

Figure 10.25 Example of Phase Counting Mode 1 Operation .................................................... 436

Figure 10.26 Example of Phase Counting Mode 2 Operation .................................................... 437

Figure 10.27 Example of Phase Counting Mode 3 Operation .................................................... 438

Figure 10.28 Example of Phase Counting Mode 4 Operation .................................................... 439

Figure 10.29 Phase Counting Mode Application Example.........................................................440

Figure 10.30 Count Timing in Internal Clock Operation............................................................444

Figure 10.31 Count Timing in External Clock Operation...........................................................444

Figure 10.32 Output Compare Output Timing ...........................................................................445

Figure 10.33 Input Capture Input Signal Timing........................................................................ 445

Figure 10.34 Counter Clear Timing (Compare Match) .............................................................. 446

Figure 10.35 Counter Clear Timing (Input Capture).................................................................. 446

Figure 10.36 Buffer Operation Timing (Compare Match)..........................................................447

Figure 10.37 Buffer Operation Timing (Input Capture) ............................................................. 447

Figure 10.38 TGI Interrupt Timing (Compare Match) ...............................................................448

Figure 10.39 TGI Interrupt Timing (Input Capture)................................................................... 448

Figure 10.40 TCIV Interrupt Setting Timing.............................................................................. 449

Figure 10.41 TCIU Interrupt Setting Timing.............................................................................. 449

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Figure 10.42 Timing for Status Flag Clearing by CPU ..............................................................450

Figure 10.43 Timing for Status Flag Clearing by DTC or DMAC Activation (1)......................450

Figure 10.44 Timing for Status Flag Clearing by DTC or DMAC Activation (2)......................451

Figure 10.45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode................ 451

Figure 10.46 Conflict between TCNT Write and Clear Operations ........................................... 452

Figure 10.47 Conflict between TCNT Write and Increment Operations.................................... 453

Figure 10.48 Conflict between TGR Write and Compare Match ............................................... 453

Figure 10.49 Conflict between Buffer Register Write and Compare Match .............................. 454

Figure 10.50 Conflict between TGR Read and Input Capture.................................................... 455

Figure 10.51 Conflict between TGR Write and Input Capture................................................... 455

Figure 10.52 Conflict between Buffer Register Write and Input Capture .................................. 456

Figure 10.53 Conflict between Overflow and Counter Clearing................................................ 457

Figure 10.54 Conflict between TCNT Write and Overflow ....................................................... 457

Section 11 Programmable Pulse Generator (PPG)

Figure 11.1 Block Diagram of PPG............................................................................................ 459

Figure 11.2 Schematic Diagram of PPG..................................................................................... 470

Figure 11.3 Timing of Transfer and Output of NDR Contents (Example)................................. 470

Figure 11.4 Setup Procedure for Normal Pulse Output (Example) ............................................ 471

Figure 11.5 Normal Pulse Output Example (5-Phase Pulse Output) .......................................... 472

Figure 11.6 Non-Overlapping Pulse Output ............................................................................... 473

Figure 11.7 Non-Overlapping Operation and NDR Write Timing............................................. 474

Figure 11.8 Setup Procedure for Non-Overlapping Pulse Output (Example).............................475

Figure 11.9 Non-Overlapping Pulse Output Example (4-Phase Complementary) ..................... 476

Figure 11.10 Inverted Pulse Output (Example).......................................................................... 478

Figure 11.11 Pulse Output Triggered by Input Capture (Example)............................................ 479

Section 12 8-Bit Timers (TMR)

Figure 12.1 Block Diagram of 8-Bit Timer Module (Unit 0) ..................................................... 482

Figure 12.2 Block Diagram of 8-Bit Timer Module (Unit 1) ..................................................... 483

Figure 12.3 Example of Pulse Output......................................................................................... 495

Figure 12.4 Example of Reset Input ........................................................................................... 496

Figure 12.5 Count Timing for Internal Clock Input (Falling Edge) ........................................... 497

Figure 12.6 Count Timing for External Clock Input (Both Edges) ............................................497

Figure 12.7 Timing of CMF Setting at Compare Match.............................................................498

Figure 12.8 Timing of Toggled Timer Output at Compare Match A ......................................... 498

Figure 12.9 Timing of Counter Clear by Compare Match.......................................................... 499

Figure 12.10 Timing of Clearance by External Reset (Rising Edge) ......................................... 499

Figure 12.11 Timing of Clearance by External Reset (High Level)........................................... 500

Figure 12.12 Timing of OVF Setting ......................................................................................... 500

Figure 12.13 Conflict between TCNT Write and Clear.............................................................. 503

Figure 12.14 Conflict between TCNT Write and Increment ...................................................... 504

Figure 12.15 Conflict between TCOR Write and Compare Match ............................................ 505

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