Renesas H8S Family, R4F2472, R4F2462, H8S/2462, H8S/2400 Series Hardware Manual

REJ09B0403-0100

H8S/2472 Group,H8S/2462 Group

16

Hardware Manual

Renesas 16-Bit Single-Chip Microcomputer

H8S Family / H8S/2400 Series

H8S/2472 R4F2472

H8S/2462 R4F2462

Rev.1.00
Revision Date: Mar. 12, 2008

Rev. 1.00 Mar. 12, 2008 Page ii of xIviii

Notes regarding these materials

1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.

2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.

3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.

4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )

5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.

6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.

7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.

8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.

9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.

10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.

11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.

12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.

13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.

Rev. 1.00 Mar. 12, 2008 Page iii of xIviii

General Precautions on Handling of Product

1. Treatment of NC Pins

Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins

Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass­through current flows internally, and a malfunction may occur.

3. Processing before Initialization

Note: When power is first supplied, the product's state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses

Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.

Rev. 1.00 Mar. 12, 2008 Page iv of xIviii

Configuration of This Manual

This manual comprises the following items:

1. General Precautions on Handling of Product

2. Configuration of This Manual

3. Preface

4. Contents

5. Overview

6. Description of Functional Modules

• CPU and System-Control Modules

• On-Chip Peripheral Modules

The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:

i) Feature

ii) Input/Output Pin

iii) Register Description

iv) Operation

v) Usage Note

When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.

7. List of Registers

8. Electrical Characteristics

9. Appendix

10. Main Revisions and Additions in this Edition (only for revised versions)

The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.

11. Index

Rev. 1.00 Mar. 12, 2008 Page v of xIviii

Preface

The H8S/2472 Group, H8S/2462 Group products are single-chip microcomputers made up of the
high-speed H8S/2600 CPU employing Renesas Technology original architecture as its core, and
the peripheral functions required to configure a system. The H8S/2600 CPU has an instruction set
that is compatible with the H8/300 and H8/300H CPUs.

Target Users: This manual was written for users who will be using the H8S/2472 Group,

H8S/2462 Group in the design of application systems. Target users are expected to
understand the fundamentals of electrical circuits, logical circuits, and
microcomputers.

Objective: This manual was written to explain the hardware functions and electrical

characteristics of the H8S/2472 Group, H8S/2462 Group to the target users.
Refer to the H8S/2600 Series, H8S/2000 Series Software Manual for a
detailed description of the instruction set.

Notes on reading this manual:

• In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.

• In order to understand the details of the CPU’s functions

Read the H8S/2600 Series, H8S/2000 Series Software Manual.

• In order to understand the details of a register when its name is known

Read the index that is the final part of the manual to find the page number of the entry on the

register. The addresses, bits, and initial values of the registers are summarized in section 29,
List of Registers.

Examples: Register name: The following notation is used for cases when the same or a

similar function, e.g. 16-bit timer pulse unit or serial
communication, is implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)

Bit order: The MSB is on the left and the LSB is on the right.

Rev. 1.00 Mar. 12, 2008 Page vi of xIviii

Related Manuals: The latest versions of all related manuals are available from our web site.

Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/

H8S/2472 Group, H8S/2462 Group manuals:

Document Title Document No.

H8S/2472 Group, H8S/2462 Group Hardware Manual This manual

H8S/2600 Series, H8S/2000 Series Software Manual REJ09B0139

User’s manuals for development tools:

Document Title Document No.

H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor
User's Manual

Microcomputer Development Environment System H8S, H8/300 Series
Simulator/Debugger User's Manual

H8S, H8/300 Series High-performance Embedded Workshop 3 Tutorial REJ10B0024

H8S, H8/300 Series High-performance Embedded Workshop 3 User's
Manual

REJ10B0058

ADE-702-282

REJ10B0026

All trademarks and registered trademarks are the property of their respective owners.

Rev. 1.00 Mar. 12, 2008 Page vii of xIviii

Rev. 1.00 Mar. 12, 2008 Page viii of xIviii

Contents

Section 1 Overview................................................................................................1

1.1 Overview................................................................................................................................ 1

1.2 Block Diagram....................................................................................................................... 3

1.3 Pin Description....................................................................................................................... 4

1.3.1 Pin Assignments ....................................................................................................... 4

1.3.2 Pin Assignment in Each Operating Mode................................................................. 6

1.3.3 Pin Functions .......................................................................................................... 13

Section 2 CPU......................................................................................................23

2.1 Features................................................................................................................................ 23

2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU..................................... 24

2.1.2 Differences from H8/300 CPU ...............................................................................25

2.1.3 Differences from H8/300H CPU............................................................................. 25

2.2 CPU Operating Modes......................................................................................................... 26

2.2.1 Normal Mode.......................................................................................................... 26

2.2.2 Advanced Mode...................................................................................................... 28

2.3 Address Space...................................................................................................................... 30

2.4 Registers............................................................................................................................... 31

2.4.1 General Registers.................................................................................................... 32

2.4.2 Program Counter (PC) ............................................................................................ 33

2.4.3 Extended Control Register (EXR) .......................................................................... 33

2.4.4 Condition-Code Register (CCR)............................................................................. 34

2.4.5 Multiply-Accumulate Register (MAC)................................................................... 35

2.4.6 Initial Values of CPU Registers.............................................................................. 35

2.5 Data Formats........................................................................................................................ 36

2.5.1 General Register Data Formats............................................................................... 36

2.5.2 Memory Data Formats ............................................................................................ 38

2.6 Instruction Set ...................................................................................................................... 39

2.6.1 Table of Instructions Classified by Function .......................................................... 40

2.6.2 Basic Instruction Formats ....................................................................................... 50

2.7 Addressing Modes and Effective Address Calculation........................................................ 51

2.7.1 Register DirectRn ............................................................................................... 51

2.7.2 Register Indirect@ERn....................................................................................... 51

2.7.3 Register Indirect with Displacement@(d:16, ERn) or @(d:32, ERn)................. 52

2.7.4 Register Indirect with Post-Increment or Pre-Decrement@ERn+ or @-ERn..... 52

2.7.5 Absolute Address@aa:8, @aa:16, @aa:24, or @aa:32....................................... 52

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2.7.6 Immediate#xx:8, #xx:16, or #xx:32.................................................................... 53

2.7.7 Program-Counter Relative@(d:8, PC) or @(d:16, PC) ...................................... 53

2.7.8 Memory Indirect@@aa:8 ................................................................................... 54

2.7.9 Effective Address Calculation ................................................................................ 55

2.8 Processing States.................................................................................................................. 57

2.9 Usage Note........................................................................................................................... 59

2.9.1 Notes on Using the Bit Operation Instruction......................................................... 59

Section 3 MCU Operating Modes .......................................................................61

3.1 Operating Mode Selection ................................................................................................... 61

3.2 Register Descriptions...........................................................................................................62

3.2.1 Mode Control Register (MDCR) ............................................................................ 62

3.2.2 System Control Register (SYSCR)......................................................................... 63

3.2.3 Serial Timer Control Register (STCR) ................................................................... 64

3.3 Operating Mode Descriptions.............................................................................................. 66

3.3.1 Mode 2.................................................................................................................... 66

3.4 Address Map........................................................................................................................ 67

Section 4 Exception Handling............................................................................. 69

4.1 Exception Handling Types and Priority............................................................................... 69

4.2 Exception Sources and Exception Vector Table.................................................................. 70

4.3 Reset .................................................................................................................................... 72

4.3.1 Reset Exception Handling ...................................................................................... 72

4.3.2 Interrupts after Reset............................................................................................... 73

4.3.3 On-Chip Peripheral Modules after Reset is Cancelled ........................................... 73

4.4 Interrupt Exception Handling .............................................................................................. 74

4.5 Trap Instruction Exception Handling................................................................................... 74

4.6 Stack Status after Exception Handling................................................................................. 75

4.7 Usage Note........................................................................................................................... 76

Section 5 Interrupt Controller.............................................................................. 77

5.1 Features................................................................................................................................ 77

5.2 Input/Output Pins................................................................................................................. 78

5.3 Register Descriptions...........................................................................................................79

5.3.1 Interrupt Control Registers A to D (ICRA to ICRD).............................................. 79

5.3.2 Address Break Control Register (ABRKCR) ......................................................... 80

5.3.3 Break Address Registers A to C (BARA to BARC)............................................... 81

5.3.4 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL)................... 82

5.3.5 IRQ Enable Registers (IER16, IER) ....................................................................... 84

5.3.6 IRQ Status Registers (ISR16, ISR)......................................................................... 85

Rev. 1.00 Mar. 12, 2008 Page x of xIviii

5.4 Interrupt Sources.................................................................................................................. 86

5.4.1 External Interrupts ..................................................................................................86

5.4.2 Internal Interrupts ................................................................................................... 87

5.5 Interrupt Exception Handling Vector Table......................................................................... 88

5.6 Interrupt Control Modes and Interrupt Operation................................................................ 91

5.6.1 Interrupt Control Mode 0........................................................................................ 93

5.6.2 Interrupt Control Mode 1........................................................................................ 95

5.6.3 Interrupt Exception Handling Sequence ................................................................. 98

5.6.4 Interrupt Response Times ....................................................................................... 99

5.6.5 DTC Activation by Interrupt................................................................................. 100

5.7 Usage Notes ....................................................................................................................... 102

5.7.1 Conflict between Interrupt Generation and Disabling .......................................... 102

5.7.2 Instructions that Disable Interrupts....................................................................... 103

5.7.3 Interrupts during Execution of EEPMOV Instruction........................................... 103

5.7.4 IRQ Status Registers (ISR16, ISR)....................................................................... 103

Section 6 Bus Controller (BSC).........................................................................105

6.1 Features.............................................................................................................................. 105

6.2 Input/Output Pins...............................................................................................................108

6.3 Register Descriptions......................................................................................................... 109

6.3.1 Bus Control Register (BCR) ................................................................................. 109

6.3.2 Bus Control Register 2 (BCR2) ............................................................................ 111

6.3.3 Wait State Control Register (WSCR) ................................................................... 112

6.3.4 Wait State Control Register 2 (WSCR2) .............................................................. 114

6.3.5 System Control Register 2 (SYSCR2).................................................................. 115

6.4 Bus Control........................................................................................................................ 116

6.4.1 Bus Specifications................................................................................................. 116

6.4.2 Advanced Mode.................................................................................................... 123

6.4.3 I/O Select Signals.................................................................................................. 124

6.5 Bus Interface ...................................................................................................................... 125

6.5.1 Data Size and Data Alignment.............................................................................. 125

6.5.2 Valid Strobes ........................................................................................................ 127

6.5.3 Valid Strobes (in Glueless Extension) .................................................................. 128

6.5.4 Basic Operation Timing in Normal Extended Mode ............................................ 129

6.5.5 Basic Operation Timing in Address-Data Multiplex Extended Mode.................. 140

6.5.6 Wait Control ......................................................................................................... 148

6.6 Burst ROM Interface.......................................................................................................... 152

6.6.1 Basic Operation Timing........................................................................................ 152

6.6.2 Wait Control ......................................................................................................... 153

6.7 Idle Cycle........................................................................................................................... 154

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6.8 Bus Arbitration .................................................................................................................. 155

6.8.1 Overview .............................................................................................................. 155

6.8.2 Operation .............................................................................................................. 155

6.8.3 Bus Mastership Transfer Timing .......................................................................... 156

Section 7 Data Transfer Controller (DTC)........................................................ 159

7.1 Features.............................................................................................................................. 159

7.2 Register Descriptions......................................................................................................... 161

7.2.1 DTC Mode Register A (MRA) ............................................................................. 162

7.2.2 DTC Mode Register B (MRB).............................................................................. 163

7.2.3 DTC Source Address Register (SAR)................................................................... 163

7.2.4 DTC Destination Address Register (DAR)........................................................... 163

7.2.5 DTC Transfer Count Register A (CRA) ............................................................... 164

7.2.6 DTC Transfer Count Register B (CRB)................................................................ 164

7.2.7 DTC Enable Registers (DTCER).......................................................................... 164

7.2.8 DTC Vector Register (DTVECR)......................................................................... 165

7.2.9 Keyboard Comparator Control Register (KBCOMP)........................................... 166

7.2.10 Event Counter Control Register (ECCR).............................................................. 167

7.2.11 Event Counter Status Register (ECS) ................................................................... 168

7.3 DTC Event Counter ........................................................................................................... 169

7.3.1 Event Counter Handling Priority .......................................................................... 170

7.3.2 Usage Notes.......................................................................................................... 171

7.4 Activation Sources............................................................................................................. 171

7.5 Location of Register Information and DTC Vector Table ................................................. 173

7.6 Operation ........................................................................................................................... 175

7.6.1 Normal Mode........................................................................................................ 176

7.6.2 Repeat Mode......................................................................................................... 177

7.6.3 Block Transfer Mode............................................................................................ 178

7.6.4 Chain Transfer ...................................................................................................... 179

7.6.5 Interrupt Sources................................................................................................... 180

7.6.6 Operation Timing.................................................................................................. 180

7.6.7 Number of DTC Execution States ........................................................................ 182

7.7 Procedures for Using DTC................................................................................................. 183

7.7.1 Activation by Interrupt.......................................................................................... 183

7.7.2 Activation by Software ......................................................................................... 183

7.8 Examples of Use of the DTC ............................................................................................. 184

7.8.1 Normal Mode........................................................................................................ 184

7.8.2 Software Activation .............................................................................................. 185

7.9 Usage Notes ....................................................................................................................... 186

7.9.1 Module Stop Mode Setting................................................................................... 186

Rev. 1.00 Mar. 12, 2008 Page xii of xIviii

7.9.2 On-Chip RAM ...................................................................................................... 186

7.9.3 DTCE Bit Setting.................................................................................................. 186

7.9.4 DTC Activation by Interrupt Sources of SCI, IIC, or A/D Converter ..................186

Section 8 I/O Ports.............................................................................................187

8.1 I/O Ports for the H8S/2472 Group ..................................................................................... 187

8.1.1 Port 1..................................................................................................................... 192

8.1.2 Port 2..................................................................................................................... 195

8.1.3 Port 3..................................................................................................................... 200

8.1.4 Port 4..................................................................................................................... 206

8.1.5 Port 5..................................................................................................................... 214

8.1.6 Port 6..................................................................................................................... 219

8.1.7 Port 7..................................................................................................................... 225

8.1.8 Port 8..................................................................................................................... 229

8.1.9 Port 9..................................................................................................................... 234

8.1.10 Port A.................................................................................................................... 238

8.1.11 Port B .................................................................................................................... 246

8.1.12 Port C .................................................................................................................... 252

8.1.13 Port D.................................................................................................................... 257

8.1.14 Port E .................................................................................................................... 262

8.1.15 Port F .................................................................................................................... 266

8.2 I/O Ports for the H8S/2462 Group ..................................................................................... 270

8.2.1 Port 1..................................................................................................................... 275

8.2.2 Port 2..................................................................................................................... 278

8.2.3 Port 3..................................................................................................................... 283

8.2.4 Port 4..................................................................................................................... 289

8.2.5 Port 5..................................................................................................................... 297

8.2.6 Port 6..................................................................................................................... 302

8.2.7 Port 7..................................................................................................................... 309

8.2.8 Port 8..................................................................................................................... 313

8.2.9 Port 9..................................................................................................................... 318

8.2.10 Port A.................................................................................................................... 322

8.2.11 Port B .................................................................................................................... 330

8.2.12 Port C .................................................................................................................... 336

8.2.13 Port D.................................................................................................................... 341

8.2.14 Port E .................................................................................................................... 346

8.2.15 Port F .................................................................................................................... 351

8.3 Change of Peripheral Function Pins................................................................................... 354

8.3.1 IRQ Sense Port Select Register 16 (ISSR16),

IRQ Sense Port Select Register (ISSR)................................................................. 354

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8.3.2 Port Control Register 0 (PTCNT0)....................................................................... 356

Section 9 14-Bit PWM Timer (PWMX) ...........................................................357

9.1 Features.............................................................................................................................. 357

9.2 Input/Output Pins...............................................................................................................358

9.3 Register Descriptions......................................................................................................... 358

9.3.1 PWMX (D/A) Counter (DACNT) ........................................................................ 359

9.3.2 PWMX (D/A) Data Registers A and B (DADRA and DADRB) ......................... 360

9.3.3 PWMX (D/A) Control Register (DACR) ............................................................. 362

9.3.4 Peripheral Clock Select Register (PCSR) ............................................................. 363

9.4 Bus Master Interface.......................................................................................................... 364

9.5 Operation ........................................................................................................................... 365

Section 10 16-Bit Free-Running Timer (FRT).................................................. 373

10.1 Features.............................................................................................................................. 373

10.2 Register Descriptions......................................................................................................... 375

10.2.1 Free-Running Counter (FRC) ............................................................................... 375

10.2.2 Output Compare Registers A and B (OCRA and OCRB) .................................... 375

10.2.3 Output Compare Registers AR and AF (OCRAR and OCRAF) .......................... 376

10.2.4 Timer Interrupt Enable Register (TIER)............................................................... 377

10.2.5 Timer Control/Status Register (TCSR)................................................................. 378

10.2.6 Timer Control Register (TCR).............................................................................. 379

10.2.7 Timer Output Compare Control Register (TOCR) ............................................... 380

10.3 Operation Timing............................................................................................................... 381

10.3.1 FRC Increment Timing ......................................................................................... 381

10.3.2 Output Compare Output Timing........................................................................... 381

10.3.3 FRC Clear Timing ................................................................................................ 382

10.3.4 Timing of Output Compare Flag (OCF) Setting................................................... 382

10.3.5 Timing of FRC Overflow Flag (OVF) Setting...................................................... 383

10.3.6 Automatic Addition Timing.................................................................................. 384

10.4 Interrupt Sources................................................................................................................ 384

10.5 Usage Notes ....................................................................................................................... 385

10.5.1 Conflict between FRC Write and Clear ................................................................ 385

10.5.2 Conflict between FRC Write and Increment......................................................... 386

10.5.3 Conflict between OCR Write and Compare-Match .............................................. 387

10.5.4 Switching of Internal Clock and FRC Operation.................................................. 388

Section 11 8-Bit Timer (TMR)..........................................................................391

11.1 Features.............................................................................................................................. 391

11.2 Register Descriptions......................................................................................................... 394

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11.2.1 Timer Counter (TCNT)......................................................................................... 394

11.2.2 Time Constant Register A (TCORA).................................................................... 395

11.2.3 Time Constant Register B (TCORB) .................................................................... 395

11.2.4 Timer Control Register (TCR).............................................................................. 396

11.2.5 Timer Control/Status Register (TCSR)................................................................. 399

11.2.6 Timer Connection Register S (TCONRS)............................................................. 403

11.3 Operation Timing............................................................................................................... 404

11.3.1 TCNT Count Timing ............................................................................................ 404

11.3.2 Timing of CMFA and CMFB Setting at Compare-Match .................................... 404

11.3.3 Timing of Counter Clear at Compare-Match ........................................................ 405

11.3.4 Timing of Overflow Flag (OVF) Setting .............................................................. 405

11.4 TMR_0 and TMR_1 Cascaded Connection....................................................................... 406

11.4.1 16-Bit Count Mode ...............................................................................................406

11.4.2 Compare-Match Count Mode ............................................................................... 406

11.5 Interrupt Sources................................................................................................................ 407

11.6 Usage Notes ....................................................................................................................... 408

11.6.1 Conflict between TCNT Write and Counter Clear................................................ 408

11.6.2 Conflict between TCNT Write and Increment...................................................... 409

11.6.3 Conflict between TCOR Write and Compare-Match............................................ 410

11.6.4 Switching of Internal Clocks and TCNT Operation.............................................. 411

11.6.5 Mode Setting with Cascaded Connection ............................................................. 412

Section 12 Watchdog Timer (WDT)..................................................................413

12.1 Features.............................................................................................................................. 413

12.2 Input/Output Pins...............................................................................................................415

12.3 Register Descriptions......................................................................................................... 415

12.3.1 Timer Counter (TCNT)......................................................................................... 415

12.3.2 Timer Control/Status Register (TCSR)................................................................. 416

12.4 Operation ........................................................................................................................... 420

12.4.1 Watchdog Timer Mode ......................................................................................... 420

12.4.2 Interval Timer Mode ............................................................................................. 422

12.4.3 RESO Signal Output Timing ................................................................................ 423

12.5 Interrupt Sources................................................................................................................ 424

12.6 Usage Notes ....................................................................................................................... 425

12.6.1 Notes on Register Access...................................................................................... 425

12.6.2 Conflict between Timer Counter (TCNT) Write and Increment........................... 426

12.6.3 Changing Values of CKS2 to CKS0 Bits.............................................................. 426

12.6.4 Changing Value of PSS Bit................................................................................... 426

12.6.5 Switching between Watchdog Timer Mode and Interval Timer Mode................. 427

12.6.6 System Reset by RESO Signal ............................................................................. 427

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Section 13 Serial Communication Interface (SCI)............................................ 429

13.1 Features.............................................................................................................................. 429

13.2 Input/Output Pins...............................................................................................................432

13.3 Register Descriptions......................................................................................................... 432

13.3.1 Receive Shift Register (RSR) ............................................................................... 433

13.3.2 Receive Data Register (RDR)............................................................................... 433

13.3.3 Transmit Data Register (TDR).............................................................................. 433

13.3.4 Transmit Shift Register (TSR) .............................................................................. 433

13.3.5 Serial Mode Register (SMR) ................................................................................ 434

13.3.6 Serial Control Register (SCR) .............................................................................. 437

13.3.7 Serial Status Register (SSR) ................................................................................. 440

13.3.8 Smart Card Mode Register (SCMR)..................................................................... 444

13.3.9 Bit Rate Register (BRR) ....................................................................................... 445

13.4 Operation in Asynchronous Mode ..................................................................................... 449

13.4.1 Data Transfer Format............................................................................................ 450

13.4.2 Receive Data Sampling Timing and Reception Margin in

Asynchronous Mode............................................................................................. 451

13.4.3 Clock..................................................................................................................... 452

13.4.4 SCI Initialization (Asynchronous Mode) .............................................................. 453

13.4.5 Serial Data Transmission (Asynchronous Mode) ................................................. 454

13.4.6 Serial Data Reception (Asynchronous Mode) ...................................................... 456

13.5 Multiprocessor Communication Function.......................................................................... 460

13.5.1 Multiprocessor Serial Data Transmission ............................................................. 462

13.5.2 Multiprocessor Serial Data Reception .................................................................. 463

13.6 Operation in Clock Synchronous Mode............................................................................. 466

13.6.1 Clock..................................................................................................................... 466

13.6.2 SCI Initialization (Clock Synchronous Mode)...................................................... 467

13.6.3 Serial Data Transmission (Clock Synchronous Mode) ......................................... 468

13.6.4 Serial Data Reception (Clock Synchronous Mode) .............................................. 471

13.6.5 Simultaneous Serial Data Transmission and Reception

(Clock Synchronous Mode).................................................................................. 473

13.7 Smart Card Interface Description ...................................................................................... 475

13.7.1 Sample Connection ............................................................................................... 475

13.7.2 Data Format (Except in Block Transfer Mode) .................................................... 475

13.7.3 Block Transfer Mode ............................................................................................ 477

13.7.4 Receive Data Sampling Timing and Reception Margin ....................................... 478

13.7.5 Initialization .......................................................................................................... 479

13.7.6 Serial Data Transmission (Except in Block Transfer Mode) ................................ 480

13.7.7 Serial Data Reception (Except in Block Transfer Mode) ..................................... 483

13.7.8 Clock Output Control............................................................................................ 485

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13.8 Interrupt Sources................................................................................................................ 487

13.8.1 Interrupts in Normal Serial Communication Interface Mode ............................... 487

13.8.2 Interrupts in Smart Card Interface Mode .............................................................. 488

13.9 Usage Notes ....................................................................................................................... 489

13.9.1 Module Stop Mode Setting ................................................................................... 489

13.9.2 Break Detection and Processing ........................................................................... 489

13.9.3 Mark State and Break Sending.............................................................................. 489

13.9.4 Receive Error Flags and Transmit Operations

(Clock Synchronous Mode Only) ......................................................................... 489

13.9.5 Relation between Writing to TDR and TDRE Flag .............................................. 489

13.9.6 Restrictions on Using DTC ................................................................................... 490

13.9.7 SCI Operations during Mode Transitions ............................................................. 491

13.9.8 Notes on Switching from SCK Pins to Port Pins .................................................. 495

Section 14 CRC Operation Circuit (CRC).........................................................497

14.1 Features.............................................................................................................................. 497

14.2 Register Descriptions......................................................................................................... 498

14.2.1 CRC Control Register (CRCCR) .......................................................................... 498

14.2.2 CRC Data Input Register (CRCDIR).................................................................... 499

14.2.3 CRC Data Output Register (CRCDOR)................................................................ 499

14.3 CRC Operation Circuit Operation...................................................................................... 499

14.4 Note on CRC Operation Circuit......................................................................................... 503

Section 15 Serial Communication Interface with FIFO (SCIF) ........................505

15.1 Features.............................................................................................................................. 505

15.2 Input/Output Pins...............................................................................................................507

15.3 Register Descriptions......................................................................................................... 508

15.3.1 Receive Shift Register (FRSR) ............................................................................. 509

15.3.2 Receive Buffer Register (FRBR) ..........................................................................509

15.3.3 Transmitter Shift Register (FTSR)........................................................................ 509

15.3.4 Transmitter Holding Register (FTHR).................................................................. 510

15.3.5 Divisor Latch H, L (FDLH, FDLL) ...................................................................... 510

15.3.6 Interrupt Enable Register (FIER).......................................................................... 511

15.3.7 Interrupt Identification Register (FIIR)................................................................. 512

15.3.8 FIFO Control Register (FFCR)............................................................................. 514

15.3.9 Line Control Register (FLCR) .............................................................................. 515

15.3.10 Modem Control Register (FMCR)........................................................................ 516

15.3.11 Line Status Register (FLSR)................................................................................. 518

15.3.12 Modem Status Register (FMSR)........................................................................... 522

15.3.13 Scratch Pad Register (FSCR)................................................................................ 523

Rev. 1.00 Mar. 12, 2008 Page xvii of xIviii

15.3.14 SCIF Control Register (SCIFCR)......................................................................... 524

15.4 Operation ........................................................................................................................... 526

15.4.1 Baud Rate ............................................................................................................. 526

15.4.2 Operation in Asynchronous Communication........................................................ 527

15.4.3 Initialization of the SCIF ...................................................................................... 528

15.4.4 Data Transmission/Reception with Flow Control................................................. 531

15.4.5 Data Transmission/Reception Through the LPC Interface ................................... 537

15.5 Interrupt Sources................................................................................................................ 539

15.6 Usage Note......................................................................................................................... 539

15.6.1 Power-Down Mode When LCLK is Selected for SCLK ...................................... 539

Section 16 Serial Pin Multiplexed Modes......................................................... 541

16.1 Features.............................................................................................................................. 541

16.2 Input/Output Pins...............................................................................................................542

16.3 Register Descriptions......................................................................................................... 543

16.3.1 Serial Multiplexed Mode Register 0 (SMR0) ....................................................... 543

16.3.2 Serial Multiplexed Mode Register 1 (SMR1) ....................................................... 544

16.4 Operation of Serial Pin Multiplexed Modes ...................................................................... 545

16.4.1 Serial Pin Multiplexed Mode 0

(Default; SMR0 Register [bits SM2, SM1, SM0] = [0 0 0])................................. 545

16.4.2 Serial Pin Multiplexed Mode 1

(SMR0 Register [bits SM2, SM1, SM0] = [0 0 1])............................................... 546

16.4.3 Serial Pin Multiplexed Mode 2

(SMR0 Register [bits SM2, SM1, SM0] = [0 1 0])............................................... 547

16.4.4 Serial Pin Multiplexed Mode 3

(SMR0 Register [bits SM2, SM1, SM0] = [0 1 1])............................................... 548

16.4.5 Serial Pin Multiplexed Mode 4

(SMR0 Register [bits SM2, SM1, SM0] = [1 0 0])............................................... 549

16.5 Serial Port Pin Configuration............................................................................................. 550

Section 17 Synchronous Serial Communication Unit (SSU)............................551

17.1 Features.............................................................................................................................. 551

17.2 Input/Output Pins...............................................................................................................553

17.3 Register Descriptions......................................................................................................... 553

17.3.1 SS Control Register H (SSCRH) .......................................................................... 554

17.3.2 SS Control Register L (SSCRL) ........................................................................... 556

17.3.3 SS Mode Register (SSMR) ................................................................................... 557

17.3.4 SS Enable Register (SSER) .................................................................................. 558

17.3.5 SS Status Register (SSSR) .................................................................................... 559

17.3.6 SS Control Register 2 (SSCR2) ............................................................................ 561

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17.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)................................... 562

17.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3).................................... 563

17.3.9 SS Shift Register (SSTRSR) ................................................................................. 563

17.4 Operation ........................................................................................................................... 564

17.4.1 Transfer Clock ...................................................................................................... 564

17.4.2 Relationship of Clock Phase, Polarity, and Data .................................................. 564

17.4.3 Relationship between Data Input/Output Pins and Shift Register ........................ 565

17.4.4 Communication Modes and Pin Functions ........................................................... 566

17.4.5 SSU Mode............................................................................................................. 568

17.4.6 SCS Pin Control and Conflict Error...................................................................... 576

17.4.7 Clock Synchronous Communication Mode .......................................................... 577

17.5 Interrupt Requests ..............................................................................................................583

17.6 Usage Note......................................................................................................................... 583

17.6.1 Setting of Module Stop Mode............................................................................... 583

Section 18 I2C Bus Interface (IIC) .....................................................................585

18.1 Features.............................................................................................................................. 585

18.2 Input/Output Pins...............................................................................................................588

18.3 Register Descriptions......................................................................................................... 589

18.3.1 I2C Bus Data Register (ICDR) .............................................................................. 589

18.3.2 Slave Address Register (SAR).............................................................................. 590

18.3.3 Second Slave Address Register (SARX) .............................................................. 591

18.3.4 I2C Bus Mode Register (ICMR)............................................................................ 593

18.3.5 I2C Bus Transfer Rate Select Register (IICX3)..................................................... 595

18.3.6 I2C Bus Control Register (ICCR).......................................................................... 598

18.3.7 I2C Bus Status Register (ICSR)............................................................................. 607

18.3.8 I2C Bus Extended Control Register (ICXR).......................................................... 611

18.3.9 I2C SMBus Control Register (ICSMBCR)............................................................ 615

18.4 Operation ........................................................................................................................... 617

18.4.1 I2C Bus Data Format ............................................................................................. 617

18.4.2 Initialization .......................................................................................................... 619

18.4.3 Master Transmit Operation ................................................................................... 619

18.4.4 Master Receive Operation..................................................................................... 623

18.4.5 Slave Receive Operation....................................................................................... 632

18.4.6 Slave Transmit Operation ..................................................................................... 640

18.4.7 IRIC Setting Timing and SCL Control .................................................................643

18.4.8 Operation Using the DTC ..................................................................................... 646

18.4.9 Noise Canceler ...................................................................................................... 648

18.4.10 Initialization of Internal State ............................................................................... 648

18.5 Interrupt Source ................................................................................................................. 650

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18.6 Usage Notes ....................................................................................................................... 651

Section 19 LPC Interface (LPC)........................................................................665

19.1 Features.............................................................................................................................. 665

19.2 Input/Output Pins...............................................................................................................668

19.3 Register Descriptions......................................................................................................... 669

19.3.1 Host Interface Control Registers 0 and 1 (HICR0 and HICR1)............................ 671

19.3.2 Host Interface Control Registers 2 and 3 (HICR2 and HICR3)............................ 679

19.3.3 Host Interface Control Register 4 (HICR4) .......................................................... 682

19.3.4 Host Interface Control Register 5 (HICR5) .......................................................... 683

19.3.5 Pin Function Control Register (PINFNCR) .......................................................... 684

19.3.6 LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L)..................... 684

19.3.7 LPC Channel 3 Address Register H, L (LADR3H, LADR3L)............................. 686

19.3.8 Input Data Registers 1 to 3 (IDR1 to IDR3) ......................................................... 689

19.3.9 Output Data Registers 0 to 3 (ODR1 to ODR3) ................................................... 689

19.3.10 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15)..................................... 690

19.3.11 Status Registers 1 to 3 (STR1 to STR3) ............................................................... 691

19.3.12 SERIRQ Control Register 0 (SIRQCR0).............................................................. 699

19.3.13 SERIRQ Control Register 1 (SIRQCR1).............................................................. 703

19.3.14 SERIRQ Control Register 2 (SIRQCR2).............................................................. 707

19.3.15 SERIRQ Control Register 3 (SIRQCR3).............................................................. 708

19.3.16 SERIRQ Control Register 4 (SIRQCR4).............................................................. 709

19.3.17 SERIRQ Control Register 5 (SIRQCR5).............................................................. 710

19.3.18 Host Interface Select Register (HISEL)................................................................ 711

19.3.19 SCIF Address Register (SCIFADRH, SCIFADRL)............................................. 712

19.3.20 SMIC Flag Register (SMICFLG) ......................................................................... 713

19.3.21 SMIC Control Status Register (SMICCSR).......................................................... 714

19.3.22 SMIC Data Register (SMICDTR) ........................................................................ 714

19.3.23 SMIC Interrupt Register 0 (SMICIR0) ................................................................. 715

19.3.24 SMIC Interrupt Register 1 (SMICIR1) ................................................................. 717

19.3.25 BT Status Register 0 (BTSR0).............................................................................. 718

19.3.26 BT Status Register 1 (BTSR1).............................................................................. 721

19.3.27 BT Control Status Register 0 (BTCSR0).............................................................. 724

19.3.28 BT Control Status Register 1 (BTCSR1).............................................................. 725

19.3.29 BT Control Register (BTCR)................................................................................ 727

19.3.30 BT Data Buffer (BTDTR)..................................................................................... 730

19.3.31 BT Interrupt Mask Register (BTIMSR)................................................................ 730

19.3.32 BT FIFO Valid Size Register 0 (BTFVSR0)........................................................ 732

19.3.33 BT FIFO Valid Size Register 1 (BTFVSR1)........................................................ 732

19.4 Operation ........................................................................................................................... 733

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19.4.1 LPC interface Activation ...................................................................................... 733

19.4.2 LPC I/O Cycles ..................................................................................................... 733

19.4.3 SMIC Mode Transfer Flow................................................................................... 735

19.4.4 BT Mode Transfer Flow ....................................................................................... 738

19.4.5 Gate A20 ............................................................................................................... 740

19.4.6 LPC Interface Shutdown Function (LPCPD)........................................................ 743

19.4.7 LPC Interface Serialized Interrupt Operation (SERIRQ) ..................................... 747

19.4.8 LPC Interface Clock Start Request ....................................................................... 749

19.4.9 SCIF Control from LPC Interface......................................................................... 749

19.5 Interrupt Sources................................................................................................................ 750

19.5.1 IBFI1, IBFI2, IBFI3, and ERRI ............................................................................ 750

19.5.2 SMI, HIRQ1, HIRQ3, HIRQ4, HIRQ5, HIRQ6, HIRQ7, HIRQ8, HIRQ9,

HIRQ10, HIRQ11, HIRQ12, HIRQ13, HIRQ14, and HIRQ15............................ 751

19.6 Usage Note......................................................................................................................... 754

19.6.1 Data Conflict......................................................................................................... 754

Section 20 Ethernet Controller (EtherC)............................................................757

20.1 Features.............................................................................................................................. 757

20.2 Input/Output Pins...............................................................................................................759

20.3 Register Description........................................................................................................... 760

20.3.1 EtherC Mode Register (ECMR)............................................................................ 761

20.3.2 EtherC Status Register (ECSR) ............................................................................ 764

20.3.3 EtherC Interrupt Permission Register (ECSIPR) .................................................. 766

20.3.4 PHY Interface Register (PIR) ............................................................................... 767

20.3.5 MAC Address High Register (MAHR) ................................................................ 768

20.3.6 MAC Address Low Register (MALR).................................................................. 768

20.3.7 Receive Frame Length Register (RFLR) .............................................................. 769

20.3.8 PHY Status Register (PSR)................................................................................... 770

20.3.9 Transmit Retry Over Counter Register (TROCR) ................................................ 770

20.3.10 Delayed Collision Detect Counter Register (CDCR)............................................ 771

20.3.11 Lost Carrier Counter Register (LCCR)................................................................. 771

20.3.12 Carrier Not Detect Counter Register (CNDCR) ................................................... 771

20.3.13 CRC Error Frame Counter Register (CEFCR)...................................................... 772

20.3.14 Frame Receive Error Counter Register (FRECR)................................................. 772

20.3.15 Too-Short Frame Receive Counter Register (TSFRCR)....................................... 772

20.3.16 Too-Long Frame Receive Counter Register (TLFRCR)....................................... 773

20.3.17 Residual-Bit Frame Counter Register (RFCR) ..................................................... 773

20.3.18 Multicast Address Frame Counter Register (MAFCR)......................................... 773

20.3.19 IPG Register (IPGR)............................................................................................. 774

20.3.20 Automatic PAUSE Frame Set Register (APR)..................................................... 774

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20.3.21 Manual PAUSE Frame Set Register (MPR)......................................................... 775

20.3.22 Automatic PAUSE Frame Retransmission Count Set Register (TPAUSER)....... 775

20.4 Operation ........................................................................................................................... 776

20.4.1 Transmission......................................................................................................... 776

20.4.2 Reception .............................................................................................................. 779

20.4.3 RMII Frame Timing ............................................................................................. 780

20.4.4 Accessing MII Registers ....................................................................................... 782

20.4.5 Magic Packet Detection ........................................................................................ 785

20.4.6 Operation by IPG Setting...................................................................................... 786

20.4.7 Flow Control ......................................................................................................... 786

20.5 Usage Notes ....................................................................................................................... 788

20.5.1 Conditions for Setting LCHNG Bit ...................................................................... 788

20.5.2 Flow Control Defect 1 .......................................................................................... 788

20.5.3 Flow Control Defect 2 .......................................................................................... 788

20.5.4 Operation Seed...................................................................................................... 789

Section 21 Ethernet Controller Direct Memory Access Controller

(E-DMAC)....................................................................................... 791

21.1 Features.............................................................................................................................. 791

21.2 Register Descriptions......................................................................................................... 792

21.2.1 E-DMAC Mode Register (EDMR) ....................................................................... 794

21.2.2 E-DMAC Transmit Request Register (EDTRR) .................................................. 795

21.2.3 E-DMAC Receive Request Register (EDRRR).................................................... 796

21.2.4 Transmit Descriptor List Address Register (TDLAR).......................................... 797

21.2.5 Receive Descriptor List Address Register (RDLAR) ........................................... 797

21.2.6 EtherC/E-DMAC Status Register (EESR)............................................................ 798

21.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR)....................... 803

21.2.8 Transmit/Receive Status Copy Enable Register (TRSCER)................................. 806

21.2.9 Receive Missed-Frame Counter Register (RMFCR) ............................................ 808

21.2.10 Transmit FIFO Threshold Register (TFTR).......................................................... 808

21.2.11 FIFO Depth Register (FDR) ................................................................................. 810

21.2.12 Receiving method Control Register (RMCR)....................................................... 811

21.2.13 Receiving-Buffer Write Address Register (RBWAR).......................................... 812

21.2.14 Receiving-Descriptor Fetch Address Register (RDFAR)..................................... 812

21.2.15 Transmission-Buffer Read Address Register (TBRAR)....................................... 812

21.2.16 Transmission-Descriptor Fetch Address Register (TDFAR)................................ 813

21.2.17 Flow Control FIFO Threshold Register (FCFTR) ................................................ 813

21.2.18 Bit Rate Setting Register (ECBRR)...................................................................... 815

21.2.19 Transmit Interrupt Register (TRIMD) .................................................................. 815

21.3 Operation ........................................................................................................................... 816

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21.3.1 Descriptor List and Data Buffers ..........................................................................816

21.3.2 Transmission ......................................................................................................... 826

21.3.3 Reception .............................................................................................................. 828

21.3.4 Multi-Buffer Frame Transmit/Receive Processing ............................................... 830

Section 22 USB Function Module (USB)..........................................................833

22.1 Features.............................................................................................................................. 833

22.2 Input/Output Pins...............................................................................................................834

22.3 Register Descriptions......................................................................................................... 835

22.3.1 Interrupt Flag Register 0 (IFR0) ........................................................................... 836

22.3.2 Interrupt Flag Register 1 (IFR1) ........................................................................... 838

22.3.3 Interrupt Flag Register 2 (IFR2) ........................................................................... 839

22.3.4 Interrupt Select Register 0 (ISR0)......................................................................... 840

22.3.5 Interrupt Select Register 1 (ISR1)......................................................................... 841

22.3.6 Interrupt Select Register 2 (ISR2)......................................................................... 841

22.3.7 Interrupt Enable Register 0 (IER0) ....................................................................... 842

22.3.8 Interrupt Enable Register 1 (IER1) ....................................................................... 842

22.3.9 Interrupt Enable Register 2 (IER2) ....................................................................... 843

22.3.10 EP0i Data Register (EPDR0i)............................................................................... 843

22.3.11 EP0o Data Register (EPDR0o) ............................................................................. 844

22.3.12 EP0s Data Register (EPDR0s).............................................................................. 844

22.3.13 EP1 Data Register (EPDR1) ................................................................................. 845

22.3.14 EP2 Data Register (EPDR2) ................................................................................. 845

22.3.15 EP3 Data Register (EPDR3) ................................................................................. 845

22.3.16 EP0o Receive Data Size Register (EPSZ0o) ........................................................846

22.3.17 EP1 Receive Data Size Register (EPSZ1) ............................................................ 846

22.3.18 Trigger Register (TRG)......................................................................................... 846

22.3.19 Data Status Register (DASTS).............................................................................. 848

22.3.20 FIFO Clear Register (FCLR) ................................................................................ 849

22.3.21 DTC Transfer Setting Register (DMA) ................................................................ 850

22.3.22 Endpoint Stall Register (EPSTL).......................................................................... 853

22.3.23 Configuration Value Register (CVR) ................................................................... 854

22.3.24 Control Register (CTLR) ...................................................................................... 854

22.3.25 Endpoint Information Register (EPIR) ................................................................. 856

22.3.26 Transceiver Test Register 0 (TRNTREG0)........................................................... 860

22.3.27 Transceiver Test Register 1 (TRNTREG1)........................................................... 861

22.4 Interrupt Sources................................................................................................................ 863

22.5 Operation ........................................................................................................................... 865

22.5.1 Operation at Cable Connection ............................................................................. 865

22.5.2 Operation at Cable Disconnection ........................................................................ 866

Rev. 1.00 Mar. 12, 2008 Page xxiii of xIviii

22.5.3 Suspend and Resume Operations.......................................................................... 867

22.5.4 Control Transfer.................................................................................................... 872

22.5.5 EP1 Bulk-Out Transfer (Dual FIFOs)................................................................... 878

22.5.6 EP2 Bulk-In Transfer (Dual FIFOs) ..................................................................... 879

22.5.7 EP3 Interrupt-In Transfer...................................................................................... 881

22.6 Processing of USB Standard Commands and Class/Vendor Commands .......................... 882

22.6.1 Processing of Commands Transmitted by Control Transfer................................. 882

22.7 Stall Operations.................................................................................................................. 883

22.7.1 Overview .............................................................................................................. 883

22.7.2 Forcible Stall by Application ................................................................................ 883

22.7.3 Automatic Stall by USB Function Module ........................................................... 885

22.8 DTC Transfer..................................................................................................................... 886

22.8.1 Overview .............................................................................................................. 886

22.8.2 DTC Transfer for Endpoint 1................................................................................ 887

22.8.3 DTC Transfer for Endpoint 2................................................................................ 888

22.8.4 DTC Transfer End Interrupt ................................................................................. 889

22.9 Example of USB External Circuitry .................................................................................. 890

22.10 Usage Notes....................................................................................................................... 892

22.10.1 Receiving Setup Data ........................................................................................... 892

22.10.2 Clearing the FIFO................................................................................................. 892

22.10.3 Overreading and Overwriting the Data Registers................................................. 892

22.10.4 Assigning Interrupt Sources to EP0...................................................................... 893

22.10.5 Clearing the FIFO When DTC Transfer is Enabled.............................................. 893

22.10.6 Notes on TR Interrupt........................................................................................... 893

22.10.7 Restrictions on Peripheral Module Clock (φ) Operating Frequency..................... 894

Section 23 A/D Converter ................................................................................. 895

23.1 Features.............................................................................................................................. 895

23.2 Input/Output Pins...............................................................................................................897

23.3 Register Descriptions......................................................................................................... 898

23.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .............................................. 898

23.3.2 A/D Control/Status Register (ADCSR) ................................................................ 899

23.3.3 A/D Control Register (ADCR) ............................................................................. 901

23.4 Operation ........................................................................................................................... 902

23.4.1 Single Mode.......................................................................................................... 902

23.4.2 Scan Mode ............................................................................................................ 903

23.4.3 Input Sampling and A/D Conversion Time .......................................................... 905

23.4.4 Timing of External Trigger Input ......................................................................... 908

23.5 Interrupt Source ................................................................................................................. 909

23.6 A/D Conversion Accuracy Definitions.............................................................................. 909

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23.7 Usage Notes ....................................................................................................................... 911

23.7.1 Setting of Module Stop Mode............................................................................... 911

23.7.2 Permissible Signal Source Impedance .................................................................. 911

23.7.3 Influences on Absolute Accuracy ......................................................................... 912

23.7.4 Setting Range of Analog Power Supply and Other Pins....................................... 912

23.7.5 Notes on Board Design ......................................................................................... 912

23.7.6 Notes on Noise Countermeasures .........................................................................913

23.7.7 Note on the Usage in Software Standby Mode ..................................................... 914

Section 24 RAM ................................................................................................915

Section 25 Flash Memory ..................................................................................917

25.1 Features.............................................................................................................................. 917

25.1.1 Operating Mode ....................................................................................................919

25.1.2 Mode Comparison................................................................................................. 920

25.1.3 Flash Memory MAT Configuration ...................................................................... 921

25.1.4 Block Division ...................................................................................................... 921

25.1.5 Programming/Erasing Interface ............................................................................ 923

25.2 Input/Output Pins...............................................................................................................925

25.3 Register Descriptions......................................................................................................... 926

25.3.1 Programming/Erasing Interface Register.............................................................. 928

25.3.2 Programming/Erasing Interface Parameter ........................................................... 936

25.4 On-Board Programming Mode ..........................................................................................947

25.4.1 Boot Mode ............................................................................................................ 948

25.4.2 USB Boot Mode.................................................................................................... 952

25.4.3 User Program Mode.............................................................................................. 956

25.4.4 User Boot Mode.................................................................................................... 967

25.4.5 Procedure Program and Storable Area for Programming Data............................. 972

25.5 Protection........................................................................................................................... 982

25.5.1 Hardware Protection ............................................................................................. 982

25.5.2 Software Protection............................................................................................... 984

25.5.3 Error Protection..................................................................................................... 984

25.6 Switching between User MAT and User Boot MAT......................................................... 986

25.7 Programmer Mode ............................................................................................................. 987

25.8 Serial Communication Interface Specification for Boot Mode.......................................... 988

25.9 Usage Notes ..................................................................................................................... 1016

Section 26 Boundary Scan (JTAG) .................................................................1019

26.1 Features............................................................................................................................ 1019

26.2 Input/Output Pins............................................................................................................. 1021

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26.3 Register Descriptions....................................................................................................... 1022

26.3.1 Instruction Register (SDIR) ................................................................................ 1023

26.3.2 Bypass Register (SDBPR) .................................................................................. 1024

26.3.3 Boundary Scan Register (SDBSR) ..................................................................... 1024

26.3.4 ID Code Register (SDIDR)................................................................................. 1042

26.4 Operation ......................................................................................................................... 1043

26.4.1 TAP Controller State Transitions........................................................................ 1043

26.4.2 JTAG Reset......................................................................................................... 1044

26.5 Boundary Scan................................................................................................................. 1044

26.5.1 Supported Instructions ........................................................................................ 1044

26.6 Usage Notes ..................................................................................................................... 1047

Section 27 Clock Pulse Generator................................................................... 1051

27.1 Oscillator.......................................................................................................................... 1052

27.1.1 Connecting Crystal Resonator ............................................................................ 1052

27.1.2 External Clock Input Method ............................................................................. 1053

27.2 PLL Multiplier Circuit ..................................................................................................... 1054

27.3 Medium-Speed Clock Divider......................................................................................... 1054

27.4 Bus Master Clock Select Circuit...................................................................................... 1054

27.5 Subclock Input Circuit ..................................................................................................... 1054

27.6 Subclock Waveform Shaping Circuit .............................................................................. 1054

27.7 Clock Select Circuit ......................................................................................................... 1055

27.8 Usage Notes ..................................................................................................................... 1056

27.8.1 Note on Resonator .............................................................................................. 1056

27.8.2 Notes on Board Design ....................................................................................... 1056

27.8.3 Note on Operation Check ................................................................................... 1056

Section 28 Power-Down Modes...................................................................... 1057

28.1 Register Descriptions....................................................................................................... 1058

28.1.1 Standby Control Register (SBYCR) ................................................................... 1058

28.1.2 Low-Power Control Register (LPWRCR) .......................................................... 1061

28.1.3 Module Stop Control Registers H, L, and A

(MSTPCRH, MSTPCRL, MSTPCRA) .............................................................. 1062

28.1.4 Sub-Chip Module Stop Control Registers BH, BL

(SUBMSTPBH, SUBMSTPBL)......................................................................... 1064

28.2 Mode Transitions and LSI States..................................................................................... 1065

28.3 Medium-Speed Mode ...................................................................................................... 1067

28.4 Sleep Mode ...................................................................................................................... 1068

28.5 Software Standby Mode................................................................................................... 1069

28.6 Hardware Standby Mode ................................................................................................. 1071

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28.7 Module Stop Mode .......................................................................................................... 1072

28.8 Usage Notes ..................................................................................................................... 1072

28.8.1 I/O Port Status..................................................................................................... 1072

28.8.2 Current Consumption when Waiting for Oscillation Settling ............................. 1072

28.8.3 DTC Module Stop Mode .................................................................................... 1072

28.8.4 Notes on Subclock Usage ................................................................................... 1072

Section 29 List of Registers .............................................................................1073

29.1 Register Addresses (Address Order)................................................................................ 1074

29.2 Register Bits..................................................................................................................... 1088

29.3 Register States in Each Operating Mode ......................................................................... 1106

Section 30 Platform Environment Control Interface (PECI)...........................1119

Section 31 Electrical Characteristics ...............................................................1121

31.1 Absolute Maximum Ratings ............................................................................................ 1121

31.2 DC Characteristics ........................................................................................................... 1122

31.3 AC Characteristics ........................................................................................................... 1127

31.3.1 Clock Timing ...................................................................................................... 1127

31.3.2 Control Signal Timing ........................................................................................ 1132

31.3.3 Bus Timing ......................................................................................................... 1134

31.3.4 Multiplex Bus Timing......................................................................................... 1143

31.3.5 Timing of On-Chip Peripheral Modules ............................................................. 1146

31.4 A/D Conversion Characteristics....................................................................................... 1162

31.5 Flash Memory Characteristics ......................................................................................... 1163

31.6 Usage Notes ..................................................................................................................... 1164

Appendix .......................................................................................................1165

A. I/O Port States in Each Processing State.......................................................................... 1165

B. Product Lineup................................................................................................................. 1168

C. Package Dimensions ........................................................................................................ 1169

Index .......................................................................................................1171

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Figures

Section 1 Overview

Figure 1.1 Internal Block Diagram................................................................................................. 3

Figure 1.2 Pin Assignments (H8S/2472 Group)............................................................................. 4

Figure 1.3 Pin Assignments (H8S/2462 Group)............................................................................. 5

Section 2 CPU

Figure 2.1 Exception Vector Table (Normal Mode)..................................................................... 27

Figure 2.2 Stack Structure in Normal Mode................................................................................. 27

Figure 2.3 Exception Vector Table (Advanced Mode)................................................................. 28

Figure 2.4 Stack Structure in Advanced Mode............................................................................. 29

Figure 2.5 Memory Map............................................................................................................... 30

Figure 2.6 CPU Registers .............................................................................................................31

Figure 2.7 Usage of General Registers .........................................................................................32

Figure 2.8 Stack............................................................................................................................ 33

Figure 2.9 General Register Data Formats (1).............................................................................. 36

Figure 2.9 General Register Data Formats (2).............................................................................. 37

Figure 2.10 Memory Data Formats...............................................................................................38

Figure 2.11 Instruction Formats (Examples) ................................................................................50

Figure 2.12 Branch Address Specification in Memory Indirect Mode......................................... 54

Figure 2.13 State Transitions........................................................................................................ 58

Section 3 MCU Operating Modes

Figure 3.1 Address Map ...............................................................................................................67

Section 4 Exception Handling

Figure 4.1 Reset Sequence............................................................................................................ 73

Figure 4.2 Stack Status after Exception Handling........................................................................ 75

Figure 4.3 Operation When SP Value is Odd ............................................................................... 76

Section 5 Interrupt Controller

Figure 5.1 Block Diagram of Interrupt Controller........................................................................ 78

Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0.............................................................. 87

Figure 5.3 Block Diagram of Interrupt Control Operation ........................................................... 91

Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0.......94

Figure 5.5 State Transition in Interrupt Control Mode 1 ..............................................................95

Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1..... 97

Figure 5.7 Interrupt Exception Handling...................................................................................... 98

Figure 5.8 Interrupt Control for DTC ......................................................................................... 100

Figure 5.9 Conflict between Interrupt Generation and Disabling............................................... 102

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Section 6 Bus Controller (BSC)

Figure 6.1 Block Diagram of Bus Controller..............................................................................107

Figure 6.2 IOS Signal Output Timing ........................................................................................124

Figure 6.3 Access Sizes and Data Alignment Control (8-bit Access Space).............................. 125

Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space)............................ 126

Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space............................................................. 129

Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space............................................................. 130

Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access)........................... 131

Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access)............................ 132

Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access).................................. 133

Figure 6.10 Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access)......................... 134

Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access).......................... 135

Figure 6.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access)................................ 136

Figure 6.13 Glueless Extension Even Byte Access (ADMXE = 0)............................................ 137

Figure 6.14 Glueless Extension Odd Byte Access (ADMXE = 0) ............................................. 138

Figure 6.15 Glueless Extension Word Access (ADMXE = 0) ................................................... 139

Figure 6.16 Bus Timing for 8-Bit, 2-State Access Space........................................................... 140

Figure 6.17 Bus Timing for 8-Bit, 2-State Access Space........................................................... 141

Figure 6.18 Bus Timing for 8-Bit, 3-State Access Space........................................................... 141

Figure 6.19 Bus Timing for 16-Bit, 2-State Access Space (1) (Even Byte Access)................... 142

Figure 6.20 Bus Timing for 16-Bit, 2-State Access Space (2) (Even Byte Access)................... 143

Figure 6.21 Bus Timing for 16-Bit, 2-State Access Space (3) (Odd Byte Access) .................... 143

Figure 6.22 Bus Timing for 16-Bit, 2-State Access Space (4) (Odd Byte Access) .................... 144

Figure 6.23 Bus Timing for 16-Bit, 2-State Access Space (5) (Word Access)........................... 145

Figure 6.24 Bus Timing for 16-Bit, 2-State Access Space (6) (Word Access)........................... 145

Figure 6.25 Bus Timing for 16-Bit, 3-State Access Space (1) (Even Byte Access)................... 146

Figure 6.26 Bus Timing for 16-Bit, 3-State Access Space (2) (Odd Byte Access) .................... 147

Figure 6.27 Bus Timing for 16-Bit, 3-State Access Space (3) (Word Access)........................... 147

Figure 6.28 Example of Wait State Insertion Timing (Pin Wait Mode)..................................... 149

Figure 6.29 Example of Wait State Insertion Timing................................................................. 151

Figure 6.30 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 1).................... 152

Figure 6.31 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0).................... 153

Figure 6.32 Examples of Idle Cycle Operation .......................................................................... 154

Section 7 Data Transfer Controller (DTC)

Figure 7.1 Block Diagram of DTC............................................................................................. 160

Figure 7.2 Block Diagram of DTC Activation Source Control .................................................. 172

Figure 7.3 DTC Register Information Location in Address Space............................................. 173

Figure 7.4 DTC Operation Flowchart......................................................................................... 175

Figure 7.5 Memory Mapping in Normal Mode.......................................................................... 176

Figure 7.6 Memory Mapping in Repeat Mode ...........................................................................177

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Figure 7.7 Memory Mapping in Block Transfer Mode...............................................................178

Figure 7.8 Chain Transfer Operation.......................................................................................... 179

Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode)......................180

Figure 7.10 DTC Operation Timing (Example of Block Transfer Mode,

with Block Size of 2) ..............................................................................................181

Figure 7.11 DTC Operation Timing (Example of Chain Transfer) ............................................ 181

Section 8 I/O Ports

Figure 8.1 Noise Canceler Circuit ..............................................................................................203

Figure 8.2 Noise Canceler Operation.......................................................................................... 204

Figure 8.3 Noise Canceler Circuit ..............................................................................................210

Figure 8.4 Noise Canceler Operation.......................................................................................... 210

Figure 8.5 Noise Canceler Circuit ..............................................................................................249

Figure 8.6 Noise Canceler Operation.......................................................................................... 250

Figure 8.7 Noise Canceler Circuit ..............................................................................................286

Figure 8.8 Noise Canceler Operation.......................................................................................... 287

Figure 8.9 Noise Canceler Circuit ..............................................................................................293

Figure 8.10 Noise Canceler Operation........................................................................................ 293

Figure 8.11 Noise Canceler Circuit ............................................................................................333

Figure 8.12 Noise Canceler Operation........................................................................................ 334

Section 9 14-Bit PWM Timer (PWMX)

Figure 9.1 PWMX (D/A) Block Diagram...................................................................................357

Figure 9.2 PWMX (D/A) Operation ........................................................................................... 365

Figure 9.3 Output Waveform (OS = 0, DADR corresponds to TL) ............................................368

Figure 9.4 Output Waveform (OS = 1, DADR corresponds to TH) ............................................369

Figure 9.5 D/A Data Register Configuration when CFS = 1...................................................... 369

Figure 9.6 Output Waveform when DADR = H'0207 (OS = 1) ................................................. 370

Section 10 16-Bit Free-Running Timer (FRT)

Figure 10.1 Block Diagram of 16-Bit Free-Running Timer .......................................................374

Figure 10.2 Increment Timing with Internal Clock Source........................................................ 381

Figure 10.3 Timing of Output Compare A Output .....................................................................381

Figure 10.4 Clearing of FRC by Compare-Match A Signal .......................................................382

Figure 10.5 Timing of Output Compare Flag (OCFA or OCFB) Setting................................... 382

Figure 10.6 Timing of Overflow Flag (OVF) Setting................................................................. 383

Figure 10.7 OCRA Automatic Addition Timing ........................................................................384

Figure 10.8 Conflict between FRC Write and Clear................................................................... 385

Figure 10.9 Conflict between FRC Write and Increment ........................................................... 386

Figure 10.10 Conflict between OCR Write and Compare-Match

(When Automatic Addition Function is Not Used) ..............................................387

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Figure 10.11 Conflict between OCR Write and Compare-Match

(When Automatic Addition Function is Used) ..................................................... 388

Section 11 8-Bit Timer (TMR)

Figure 11.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1)............................................ 392

Figure 11.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X).......................................... 393

Figure 11.3 Count Timing for Internal Clock Input ...................................................................404

Figure 11.4 Timing of CMF Setting at Compare-Match............................................................ 404

Figure 11.5 Timing of Counter Clear by Compare-Match ......................................................... 405

Figure 11.6 Timing of OVF Flag Setting ................................................................................... 405

Figure 11.7 Conflict between TCNT Write and Counter Clear.................................................. 408

Figure 11.8 Conflict between TCNT Write and Increment ........................................................409

Figure 11.9 Conflict between TCOR Write and Compare-Match.............................................. 410

Section 12 Watchdog Timer (WDT)

Figure 12.1 Block Diagram of WDT.......................................................................................... 414

Figure 12.2 Watchdog Timer Mode (RST/NMI = 1) Operation................................................. 421

Figure 12.3 Interval Timer Mode Operation............................................................................... 422

Figure 12.4 OVF Flag Set Timing.............................................................................................. 422

Figure 12.5 Output Timing of RESO signal ............................................................................... 423

Figure 12.6 Writing to TCNT and TCSR (WDT_0)................................................................... 425

Figure 12.7 Conflict between TCNT Write and Increment ........................................................426

Figure 12.8 Sample Circuit for Resetting the System by the RESO Signal................................ 427

Section 13 Serial Communication Interface (SCI)

Figure 13.1 Block Diagram of SCI_1 and SCI_3....................................................................... 431

Figure 13.2 Data Format in Asynchronous Communication

(Example with 8-Bit Data, Parity, Two Stop Bits)..................................................449

Figure 13.3 Receive Data Sampling Timing in Asynchronous Mode ........................................ 451

Figure 13.4 Relation between Output Clock and Transmit Data Phase

(Asynchronous Mode)............................................................................................. 452

Figure 13.5 Sample SCI Initialization Flowchart ....................................................................... 453

Figure 13.6 Example of Operation in Transmission in Asynchronous Mode

(Example with 8-Bit Data, Parity, One Stop Bit).................................................... 454

Figure 13.7 Sample Serial Transmission Flowchart ................................................................... 455

Figure 13.8 Example of SCI Operation in Reception

(Example with 8-Bit Data, Parity, One Stop Bit).................................................... 456

Figure 13.9 Sample Serial Reception Flowchart (1)................................................................... 458

Figure 13.9 Sample Serial Reception Flowchart (2)................................................................... 459

Figure 13.10 Example of Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Station A)............................................ 461

Figure 13.11 Sample Multiprocessor Serial Transmission Flowchart........................................ 462

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Figure 13.12 Example of SCI Operation in Reception

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) .............................463

Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 464

Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 465

Figure 13.14 Data Format in Synchronous Communication (LSB-First)................................... 466

Figure 13.15 Sample SCI Initialization Flowchart ..................................................................... 467

Figure 13.16 Sample SCI Transmission Operation in Clock Synchronous Mode...................... 469

Figure 13.17 Sample Serial Transmission Flowchart................................................................. 470

Figure 13.18 Example of SCI Receive Operation in Clock Synchronous Mode........................ 471

Figure 13.19 Sample Serial Reception Flowchart ......................................................................472

Figure 13.20 Sample Flowchart of Simultaneous Serial Transmission and Reception ..............474

Figure 13.21 Pin Connection for Smart Card Interface ..............................................................475

Figure 13.22 Data Formats in Normal Smart Card Interface Mode............................................ 476

Figure 13.23 Direct Convention (SDIR = SINV = O/E = 0) ...................................................... 476

Figure 13.24 Inverse Convention (SDIR = SINV = O/E = 1)..................................................... 476

Figure 13.25 Receive Data Sampling Timing in Smart Card Interface Mode

(When Clock Frequency is 372 Times the Bit Rate)............................................. 479

Figure 13.26 Data Re-transfer Operation in SCI Transmission Mode........................................ 481

Figure 13.27 TEND Flag Set Timings during Transmission...................................................... 481

Figure 13.28 Sample Transmission Flowchart ........................................................................... 482

Figure 13.29 Data Re-transfer Operation in SCI Reception Mode............................................. 483

Figure 13.30 Sample Reception Flowchart................................................................................. 484

Figure 13.31 Clock Output Fixing Timing ................................................................................. 485

Figure 13.32 Clock Stop and Restart Procedure......................................................................... 486

Figure 13.33 Sample Transmission using DTC in Clock Synchronous Mode ...........................490

Figure 13.34 Sample Flowchart for Mode Transition during Transmission............................... 492

Figure 13.35 Pin States during Transmission in Asynchronous Mode (Internal Clock)............. 492

Figure 13.36 Pin States during Transmission in Clock Synchronous Mode (Internal Clock) .... 493

Figure 13.37 Sample Flowchart for Mode Transition during Reception.................................... 494

Figure 13.38 Switching from SCK Pins to Port Pins.................................................................. 495

Figure 13.39 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins..........496

Section 14 CRC Operation Circuit (CRC)

Figure 14.1 Block Diagram of CRC Operation Circuit .............................................................. 497

Figure 14.2 LSB-First Data Transmission .................................................................................. 499

Figure 14.3 MSB-First Data Transmission................................................................................. 500

Figure 14.4 LSB-First Data Reception .......................................................................................501

Figure 14.5 MSB-First Data Reception ...................................................................................... 502

Figure 14.6 LSB-First and MSB-First Transmit Data ................................................................ 503

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Section 15 Serial Communication Interface with FIFO (SCIF)

Figure 15.1 Block Diagram of SCIF........................................................................................... 506

Figure 15.2 Data Format in Serial Transmission/Reception

(Example with 8-Bit Data, Parity and 2 Stop Bits) ................................................. 527

Figure 15.3 Example of Initialization Flowchart........................................................................ 528

Figure 15.4 Example of Data Transmission Flowchart ..............................................................529

Figure 15.5 Example of Data Reception Flowchart....................................................................530

Figure 15.6 Example of Initialization Flowchart........................................................................ 531

Figure 15.7 Example of Data Transmission/Reception Standby Flowchart ............................... 532

Figure 15.8 Example of Data Transmission Flowchart ..............................................................533

Figure 15.9 Example of Data Transmission Suspension Flowchart ........................................... 534

Figure 15.10 Example of Data Reception Flowchart.................................................................. 535

Figure 15.11 Example of Data Reception Suspension Flowchart...............................................536

Section 16 Serial Pin Multiplexed Modes

Figure 16.1 Serial Pin Multiplexed Mode 0 ...............................................................................545

Figure 16.2 Serial Pin Multiplexed Mode 1 ...............................................................................546

Figure 16.3 Serial Pin Multiplexed Mode 2 ...............................................................................547

Figure 16.4 Serial Pin Multiplexed Mode 3 ...............................................................................548

Figure 16.5 Serial Pin Multiplexed Mode 4 ...............................................................................549

Section 17 Synchronous Serial Communication Unit (SSU)

Figure 17.1 Block Diagram of SSU............................................................................................ 552

Figure 17.2 Relationship of Clock Phase, Polarity, and Data..................................................... 564

Figure 17.3 Relationship between Data Input/Output Pins and the Shift Register ..................... 565

Figure 17.4 Example of Initial Settings in SSU Mode ...............................................................568

Figure 17.5 Example of Transmission Operation (SSU Mode).................................................. 570

Figure 17.6 Flowchart Example of Data Transmission (SSU Mode) ......................................... 571

Figure 17.7 Example of Reception Operation (SSU Mode)....................................................... 573

Figure 17.8 Flowchart Example of Data Reception (SSU Mode) ..............................................574

Figure 17.9 Flowchart Example of Simultaneous Transmission/Reception (SSU Mode).......... 575

Figure 17.10 Conflict Error Detection Timing (Before Transfer) ..............................................576

Figure 17.11 Conflict Error Detection Timing (After Transfer End) ......................................... 576

Figure 17.12 Example of Initial Settings in Clock Synchronous Communication Mode........... 577

Figure 17.13 Example of Transmission Operation

(Clock Synchronous Communication Mode)........................................................578

Figure 17.14 Flowchart Example of Transmission Operation

(Clock Synchronous Communication Mode)........................................................579

Figure 17.15 Example of Reception Operation (Clock Synchronous Communication Mode)... 580
Figure 17.16 Flowchart Example of Data Reception

(Clock Synchronous Communication Mode)........................................................ 581

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Figure 17.17 Flowchart Example of Simultaneous Transmission/Reception

(Clock Synchronous Communication Mode)........................................................ 582

Section 18 I2C Bus Interface (IIC)

Figure 18.1 Block Diagram of I

Figure 18.2 I2C Bus Interface Connections (Example: This LSI as Master) .............................. 587

Figure 18.3 I2C Bus Data Formats (I2C Bus Formats)................................................................ 617

Figure 18.4 I2C Bus Data Formats (Serial Formats)................................................................... 617

Figure 18.5 I2C Bus Timing........................................................................................................ 618

Figure 18.6 Sample Flowchart for IIC Initialization................................................................... 619

Figure 18.7 Sample Flowchart for Operations in Master Transmit Mode.................................. 620

Figure 18.8 Operation Timing Example in Master Transmit Mode (MLS = WAIT = 0)........... 622

Figure 18.9 Stop Condition Issuance Operation Timing Example in Master Transmit Mode

(MLS = WAIT = 0)................................................................................................. 623

Figure 18.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1) ............. 624

Figure 18.11 Master Receive Mode Operation Timing Example

(MLS = WAIT = 0, HNDS = 1)............................................................................ 626

Figure 18.12 Stop Condition Issuance Timing Example in Master Receive Mode

(MLS = WAIT = 0, HNDS = 1)............................................................................ 626

Figure 18.13 Sample Flowchart for Operations in Master Receive Mode

(receiving multiple bytes) (WAIT = 1) .................................................................627

Figure 18.14 Sample Flowchart for Operations in Master Receive Mode

(receiving a single byte) (WAIT = 1).................................................................... 628

Figure 18.15 Master Receive Mode Operation Timing Example

(MLS = ACKB = 0, WAIT = 1)............................................................................ 631

Figure 18.16 Stop Condition Issuance Timing Example in Master Receive Mode

(MLS = ACKB = 0, WAIT = 1)............................................................................ 631

Figure 18.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1) ...............633

Figure 18.18 Slave Receive Mode Operation Timing Example (1) (MLS = 0, HNDS= 1)........ 635

Figure 18.19 Slave Receive Mode Operation Timing Example (2) (MLS = 0, HNDS= 1)........ 635

Figure 18.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0) ...............636

Figure 18.21 Slave Receive Mode Operation Timing Example (1)

(MLS = ACKB = 0, HNDS = 0) ...........................................................................638

Figure 18.22 Slave Receive Mode Operation Timing Example (2)

(MLS = ACKB = 0, HNDS = 0) ...........................................................................639

Figure 18.23 Sample Flowchart for Slave Transmit Mode......................................................... 640

Figure 18.24 Slave Transmit Mode Operation Timing Example (MLS = 0).............................. 642

Figure 18.25 IRIC Setting Timing and SCL Control (1) ............................................................ 643

Figure 18.26 IRIC Setting Timing and SCL Control (2) ............................................................ 644

Figure 18.27 IRIC Setting Timing and SCL Control (3) ............................................................ 645

Figure 18.28 Block Diagram of Noise Canceler......................................................................... 648

2

C Bus Interface........................................................................ 586

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Figure 18.29 Notes on Reading Master Receive Data................................................................ 656

Figure 18.30 Flowchart for Start Condition Issuance Instruction

for Retransmission and Timing............................................................................. 657

Figure 18.31 Stop Condition Issuance Timing ........................................................................... 658

Figure 18.32 IRIC Flag Clearing Timing When WAIT = 1 ....................................................... 659

Figure 18.33 ICDR Register Read and ICCR Register Access Timing in

Slave Transmit Mode ............................................................................................660

Figure 18.34 TRS Bit Set Timing in Slave Mode....................................................................... 661

Figure 18.35 Diagram of Erroneous Operation when Arbitration Lost ...................................... 663

Section 19 LPC Interface (LPC)

Figure 19.1 Block Diagram of LPC............................................................................................ 667

Figure 19.2 Typical LFRAME Timing....................................................................................... 735

Figure 19.3 Abort Mechanism.................................................................................................... 735

Figure 19.4 SMIC Write Transfer Flow .....................................................................................736

Figure 19.5 SMIC Read Transfer Flow ......................................................................................737

Figure 19.6 BT Write Transfer Flow.......................................................................................... 738

Figure 19.7 BT Read Transfer Flow........................................................................................... 739

Figure 19.8 GA20 Output........................................................................................................... 741

Figure 19.9 Power-Down State Termination Timing ................................................................. 746

Figure 19.10 SERIRQ Timing....................................................................................................747

Figure 19.11 Clock Start Request Timing .................................................................................. 749

Figure 19.12 HIRQ Flowchart (Example of Channel 1)............................................................. 753

Section 20 Ethernet Controller (EtherC)

Figure 20.1 Configuration of EtherC.......................................................................................... 758

Figure 20.2 EtherC Transmitter State Transitions...................................................................... 777

Figure 20.3 EtherC Receiver State Transmissions .....................................................................779

Figure 20.4 RMII Frame Transmit Timing (Normal Transmission)........................................... 780

Figure 20.5 RMII Frame Receive Timing (Normal Reception) ................................................. 780

Figure 20.6 RMII Frame Receive Timing (Reception with False Carrier)................................. 781

Figure 20.7 MII Management Frame Format ............................................................................. 782

Figure 20.8 1-Bit Data Write Flowchart..................................................................................... 783

Figure 20.9 Bus Release Flowchart (TA in Read in Figure 20.7)...............................................783

Figure 20.10 1-Bit Data Read Flowchart.................................................................................... 784

Figure 20.11 Independent Bus Release Flowchart (IDLE in Write in Figure 20.7) ...................784

Figure 20.12 Changing IPG and Transmission Efficiency ......................................................... 786

Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Figure 21.1 Configuration of E-DMAC, and Descriptors and Buffers....................................... 792

Figure 21.2 Relationship between Transmit Descriptor and Transmit Buffer............................ 817

Figure 21.3 Relationship between Receive Descriptor and Receive Buffer ............................... 821

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Figure 21.4 Sample Transmission Flowchart .............................................................................827

Figure 21.5 Sample Reception Flowchart................................................................................... 829

Figure 21.6 E-DMAC Operation after Transmit Error ...............................................................830

Figure 21.7 E-DMAC Operation after Receive Error................................................................. 831

Section 22 Ethernet Controller (EtherC)

Figure 22.1 Block Diagram of USB ...........................................................................................834

Figure 22.2 Operation at Cable Connection ............................................................................... 865

Figure 22.3 Operation at Cable Disconnection........................................................................... 866

Figure 22.4 Suspend Operation ..................................................................................................867

Figure 22.5 Resume Operation from Up-Stream........................................................................ 868

Figure 22.6 Flow of Transition to and Canceling Software Standby Mode................................869

Figure 22.7 Timing of Transition to and Canceling Software Standby Mode............................ 870

Figure 22.8 Remote-Wakeup...................................................................................................... 871

Figure 22.9 Transfer Stages in Control Transfer ........................................................................ 872

Figure 22.10 Setup Stage Operation ........................................................................................... 873

Figure 22.11 Data Stage (Control-In) Operation........................................................................ 874

Figure 22.12 Data Stage (Control-Out) Operation......................................................................875

Figure 22.13 Status Stage (Control-In) Operation...................................................................... 876

Figure 22.14 Status Stage (Control-Out) Operation ................................................................... 877

Figure 22.15 EP1 Bulk-Out Transfer Operation......................................................................... 878

Figure 22.16 EP2 Bulk-In Transfer Operation............................................................................879

Figure 22.17 Operation of EP3 Interrupt-In Transfer................................................................. 881

Figure 22.18 Forcible Stall by Application................................................................................. 884

Figure 22.19 Automatic Stall by USB Function Module............................................................885

Figure 22.20 RDFN Bit Operation for EP1 ................................................................................887

Figure 22.21 PKTE Bit Operation for EP2................................................................................. 888

Figure 22.22 Example of Circuitry in Self-Powered Mode........................................................ 891

Figure 22.23 TR Interrupt Flag Set Timing................................................................................ 893

Section 23 A/D Converter

Figure 23.1 Block Diagram of the A/D Converter......................................................................896

Figure 23.2 Example of A/D Converter Operation

(When Channel 1 is Selected in Single Mode)........................................................ 903

Figure 23.3 Example of A/D Converter Operation

(When Channels AN0 to AN3 are Selected in Scan Mode).................................... 904

Figure 23.4 A/D Conversion Timing.......................................................................................... 906

Figure 23.5 Timing of External Trigger Input ............................................................................ 908

Figure 23.6 A/D Conversion Accuracy Definitions....................................................................910

Figure 23.7 A/D Conversion Accuracy Definitions....................................................................910

Figure 23.8 Example of Analog Input Circuit ............................................................................911

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Figure 23.9 Example of Analog Input Protection Circuit........................................................... 913

Figure 23.10 Analog Input Pin Equivalent Circuit ..................................................................... 914

Section 25 Flash Memory

Figure 25.1 Block Diagram of Flash Memory............................................................................ 918

Figure 25.2 Mode Transition of Flash Memory.......................................................................... 919

Figure 25.3 Flash Memory Configuration .................................................................................. 921

Figure 25.4 Block Division of User MAT.................................................................................. 922

Figure 25.5 Overview of User Procedure Program .................................................................... 923

Figure 25.6 System Configuration in Boot Mode....................................................................... 948

Figure 25.7 Automatic-Bit-Rate Adjustment Operation of SCI ................................................. 949

Figure 25.8 Overview of Boot Mode State Transition Diagram................................................. 951

Figure 25.9 System Configuration in USB Boot Mode.............................................................. 952

Figure 25.10 USB Boot Mode State Transition Diagram........................................................... 954

Figure 25.11 Programming/Erasing Overview Flow.................................................................. 956

Figure 25.12 RAM Map When Programming/Erasing is Executed ........................................... 957

Figure 25.13 Programming Procedure........................................................................................ 958

Figure 25.14 Erasing Procedure .................................................................................................963

Figure 25.15 Repeating Procedure of Erasing and Programming............................................... 965

Figure 25.16 Procedure for Programming User MAT in User Boot Mode ................................968

Figure 25.17 Procedure for Erasing User MAT in User Boot Mode.......................................... 970

Figure 25.18 Transitions to Error-Protection State..................................................................... 985

Figure 25.19 Switching between the User MAT and User Boot MAT ...................................... 986

Figure 25.20 Boot Program States..............................................................................................989

Figure 25.21 Bit-Rate-Adjustment Sequence ............................................................................. 990

Figure 25.22 Communication Protocol Format.......................................................................... 991

Figure 25.23 New Bit-Rate Selection Sequence....................................................................... 1002

Figure 25.24 Programming Sequence....................................................................................... 1006

Figure 25.25 Erasure Sequence ................................................................................................ 1009

Section 26 Boundary Scan (JTAG)

Figure 26.1 JTAG Block Diagram............................................................................................ 1020

Figure 26.2 TAP Controller State Transitions.......................................................................... 1043

Figure 26.3 Reset Signal Circuit Without Reset Signal Interference........................................ 1047

Figure 26.4 Serial Data Input/Output (1).................................................................................. 1048

Figure 26.5 Serial Data Input/Output (2).................................................................................. 1049

Section 27 Clock Pulse Generator

Figure 27.1 Block Diagram of Clock Pulse Generator ............................................................. 1051

Figure 27.2 Typical Connection to Crystal Resonator.............................................................. 1052

Figure 27.3 Equivalent Circuit of Crystal Resonator................................................................ 1052

Figure 27.4 Example of External Clock Input.......................................................................... 1053

Rev. 1.00 Mar. 12, 2008 Page xxxviii of xIviii

Figure 27.5 Note on Board Design of Oscillation Circuit Section............................................1056

Section 28 Power-Down Modes

Figure 28.1 Mode Transition Diagram .....................................................................................1065

Figure 28.2 Medium-Speed Mode Timing ............................................................................... 1068

Figure 28.3 Software Standby Mode Application Example ..................................................... 1070

Figure 28.4 Hardware Standby Mode Timing ..........................................................................1071

Section 31 Electrical Characteristics

Figure 31.1 Darlington Transistor Drive Circuit (Example)..................................................... 1125

Figure 31.2 LED Drive Circuit (Example) ...............................................................................1126

Figure 31.3 Output Load Circuit............................................................................................... 1127

Figure 31.4 System Clock Timing............................................................................................ 1129

Figure 31.5 Oscillation Stabilization Timing............................................................................ 1129

Figure 31.6 Oscillation Stabilization Timing (Exiting Software Standby Mode)..................... 1129

Figure 31.7 External Clock Input Timing................................................................................. 1130

Figure 31.8 Timing of External Clock Output Stabilization Delay Time................................. 1130

Figure 31.9 Subclock Input Timing.......................................................................................... 1131

Figure 31.10 Reset Input Timing.............................................................................................. 1132

Figure 31.11 Interrupt Input Timing......................................................................................... 1133

Figure 31.12 Basic Bus Timing/2-State Access........................................................................1135

Figure 31.13 Basic Bus Timing/3-State Access........................................................................1136

Figure 31.14 Basic Bus Timing/3-State Access with One Wait State ......................................1137

Figure 31.15 Even Byte Access (ADMXE = 0) .......................................................................1138

Figure 31.16 Odd Byte Access (ADMXE = 0)......................................................................... 1139

Figure 31.17 Word Access (ADMXE = 0)............................................................................... 1140

Figure 31.18 Burst ROM Access Timing/2-State Access......................................................... 1141

Figure 31.19 Burst ROM Access Timing/1-State Access......................................................... 1142

Figure 31.20 Multiplex Bus Timing/Data 2-State Access ........................................................ 1144

Figure 31.21 Multiplex Bus Timing/Data 3-State Access ........................................................ 1145

Figure 31.22 I/O Port Input/Output Timing.............................................................................. 1148

Figure 31.23 PWMX Output Timing........................................................................................ 1148

Figure 31.24 SCK Clock Input Timing.....................................................................................1148

Figure 31.25 SCI Input/Output Timing (Clock Synchronous Mode) .......................................1148

Figure 31.26 A/D Converter External Trigger Input Timing.................................................... 1149

Figure 31.27 WDT Output Timing (RESO) .............................................................................1149

Figure 31.28 SSU Timing (Master, CPHS = 1)........................................................................ 1149

Figure 31.29 SSU Timing (Master, CPHS = 0)........................................................................ 1150

Figure 31.30 SSU Timing (Slave, CPHS = 1) .......................................................................... 1150

Figure 31.31 SSU Timing (Slave, CPHS = 0) .......................................................................... 1151

Figure 31.32 I2C Bus Interface Input/Output Timing............................................................... 1153

Rev. 1.00 Mar. 12, 2008 Page xxxix of xIviii

Figure 31.33 LPC Interface (LPC) Timing............................................................................... 1154

Figure 31.34 Timing of RM_REF-CLK and RMII Signals...................................................... 1155

Figure 31.35 RMII Transmit Timing........................................................................................ 1156

Figure 31.36 RMII Receive Timing (Normal Operation)......................................................... 1156

Figure 31.37 RMII Receive Timing (When an Error is Detected) ...........................................1156

Figure 31.38 MDIO Input Timing............................................................................................ 1157

Figure 31.39 MDIO Output Timing ......................................................................................... 1157

Figure 31.40 WOL Output Timing........................................................................................... 1157

Figure 31.41 Data Signal Timing ............................................................................................. 1159

Figure 31.42 Load Condition.................................................................................................... 1159

Figure 31.43 JTAG ETCK Timing........................................................................................... 1160

Figure 31.44 Reset Hold Timing .............................................................................................. 1161

Figure 31.45 JTAG Input/Output Timing................................................................................. 1161

Figure 31.46 Connecting Capacitors to VCC and VCL Pins.................................................... 1164

Appendix

Figure C.1 Package Dimensions (PLBGA0176GA-A) ............................................................ 1169

Figure C.2 Package Dimensions (PLQP0144KA-A)................................................................ 1170

Rev. 1.00 Mar. 12, 2008 Page xl of xIviii

Tables

Section 1 Overview

Table 1.1

Table 1.2 Pin Functions ..........................................................................................................13

Section 2 CPU

Table 2.1

Table 2.2 Operation Notation .................................................................................................40

Table 2.3 Data Transfer Instructions.......................................................................................41

Table 2.4 Arithmetic Operations Instructions (1) ...................................................................42

Table 2.4 Arithmetic Operations Instructions (2) ...................................................................43

Table 2.5 Logic Operations Instructions................................................................................. 44

Table 2.6 Shift Instructions..................................................................................................... 44

Table 2.7 Bit Manipulation Instructions (1)............................................................................ 45

Table 2.7 Bit Manipulation Instructions (2)............................................................................ 46

Table 2.8 Branch Instructions................................................................................................. 47

Table 2.9 System Control Instructions....................................................................................48

Table 2.10 Block Data Transfer Instructions............................................................................ 49

Table 2.11 Addressing Modes ..................................................................................................51

Table 2.12 Absolute Address Access Ranges........................................................................... 53

Table 2.13 Effective Address Calculation (1)........................................................................... 55

Table 2.13 Effective Address Calculation (2)........................................................................... 56

Pin Assignments in Each Operating Mode ...............................................................6

Instruction Classification ........................................................................................39

Section 3 MCU Operating Modes

Table 3.1

Section 4 Exception Handling

Table 4.1

Table 4.2 Exception Handling Vector Table...........................................................................70

Table 4.3 Status of CCR after Trap Instruction Exception Handling ..................................... 74

Section 5 Interrupt Controller

Table 5.1

Table 5.2 Correspondence between Interrupt Source and ICR............................................... 80

Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities.................................88

Table 5.4 Interrupt Control Modes ......................................................................................... 91

Table 5.5 Interrupts Selected in Each Interrupt Control Mode............................................... 92

Table 5.6 Operations and Control Signal Functions in Each Interrupt Control Mode............ 93

Table 5.7 Interrupt Response Times ....................................................................................... 99

Table 5.8 Number of States in Interrupt Handling Routine Execution Status ........................99

MCU Operating Mode Selection ............................................................................ 61

Exception Types and Priority.................................................................................. 69

Pin Configuration.................................................................................................... 78

Rev. 1.00 Mar. 12, 2008 Page xli of xIviii

Table 5.9 Interrupt Source Selection and Clearing Control.................................................. 101

Section 6 Bus Controller (BSC)

Table 6.1

Table 6.2 Address Ranges and External Address Spaces ..................................................... 117

Table 6.3 Bit Settings and Bus Specifications of Basic Bus Interface.................................. 118

Table 6.4 Bus Specifications for Basic Extended Area/Basic Bus Interface ........................ 118

Table 6.5 Bus Specifications for 256-Kbyte Extended Area/Basic Bus Interface................ 119

Table 6.6 Address-Data Multiplex Address Spaces.............................................................. 121

Table 6.7 Bit Settings and Bus Specifications of Basic Bus Interface.................................. 122

Table 6.8 Bus Specifications for IOS Extended Area/Multiplex Bus Interface

Table 6.9 Bus Specifications for IOS Extended Area/Multiplex Bus Interface

Table 6.10 Bus Specifications for 256-Kbyte Extended Area/Multiplex Bus Interface

Table 6.11 Bus Specifications for 256-Kbyte Extended Area/Multiplex Bus Interface

Table 6.12 Address Range for IOS Signal Output.................................................................. 124

Table 6.13 Data Buses Used and Valid Strobes...................................................................... 127

Table 6.14 Data Buses Used and Valid Strobes (Gluless Extension) ..................................... 128

Table 6.15 Pin States in Idle Cycle......................................................................................... 155

Section 7 Data Transfer Controller (DTC)

Table 7.1

Table 7.2 DTC Event Counter Conditions............................................................................ 169

Table 7.3 Flag Status/Address Code ..................................................................................... 170

Table 7.4 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs .............. 174

Table 7.5 Register Functions in Normal Mode..................................................................... 176

Table 7.6 Register Functions in Repeat Mode ...................................................................... 177

Table 7.7 Register Functions in Block Transfer Mode .........................................................178

Table 7.8 DTC Execution Status .......................................................................................... 182

Table 7.9 Number of States Required for Each Execution Status ........................................ 182

Pin Configuration.................................................................................................. 108

(Address Cycle) .................................................................................................... 122

(Data Cycle) ......................................................................................................... 122

(Address Cycle).................................................................................................... 123

(Data Cycle) ......................................................................................................... 123

Correspondence between Interrupt Sources and DTCER..................................... 165

Section 8 I/O Ports

Table 8.1

Table 8.2 Port 1 Input Pull-Up MOS States.......................................................................... 194

Table 8.3 Port 2 Input Pull-Up MOS States.......................................................................... 199

Table 8.4 Port 3 Input Pull-Up MOS States.......................................................................... 205

Table 8.5 Port 4 Input Pull-Up MOS States.......................................................................... 213

Table 8.6 Port 6 Input Pull-Up MOS States.......................................................................... 224

Table 8.7 Input Pull-Up MOS States ....................................................................................245

Rev. 1.00 Mar. 12, 2008 Page xlii of xIviii

Port Functions....................................................................................................... 188

Table 8.8 Port D Input Pull-Up MOS States......................................................................... 261

Table 8.9 Port Functions .......................................................................................................271

Table 8.10 Port 1 Input Pull-Up MOS States.......................................................................... 277

Table 8.11 Port 2 Input Pull-Up MOS States.......................................................................... 282

Table 8.12 Port 3 Input Pull-Up MOS States.......................................................................... 288

Table 8.13 Port 4 Input Pull-Up MOS States.......................................................................... 296

Table 8.14 Port 6 Input Pull-Up MOS States.......................................................................... 308

Table 8.15 Input Pull-Up MOS States ....................................................................................329

Table 8.16 Port D Input Pull-Up MOS States......................................................................... 345

Section 9 14-Bit PWM Timer (PWMX)

Table 9.1

Table 9.2 Clock Select of PWMX_1 and PWMX_0 ............................................................363

Table 9.3 Settings and Operation (Examples when φ = 34 MHz)......................................... 366

Table 9.4 Locations of Additional Pulses Added to Base Pulse (When CFS = 1)................ 371

Section 10 16-Bit Free-Running Timer (FRT)

Table 10.1

Table 10.2 Switching of Internal Clock and FRC Operation.................................................. 389

Section 11 8-Bit Timer (TMR)

Table 11.1 (1)

Table 11.1 (2) Clock Input to TCNT and Count Condition (TMR_1) ................................. 398

Table 11.1 (3) Clock Input to TCNT and Count Condition (TMR_X, TMR_Y) .................398

Table 11.2 Registers Accessible by TMR_X/TMR_Y ...........................................................403

Table 11.3 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X ....... 407

Table 11.4 Switching of Internal Clocks and TCNT Operation..............................................411

Pin Configuration.................................................................................................. 358

FRT Interrupt Sources ..........................................................................................384

Clock Input to TCNT and Count Condition (TMR_0) .................................397

Section 12 Watchdog Timer (WDT)

Table 12.1

Table 12.2 WDT Interrupt Source ..........................................................................................424

Section 13 Serial Communication Interface (SCI)

Table 13.1

Table 13.2 Relationships between N Setting in BRR and Bit Rate B..................................... 445

Table 13.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode)............ 446

Table 13.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) ..........................446

Table 13.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................446

Table 13.6 BRR Settings for Various Bit Rates (Clock Synchronous Mode)......................... 447

Table 13.7 Maximum Bit Rate with External Clock Input (Clock Synchronous Mode) ........448

Table 13.8 BRR Settings for Various Bit Rates

Pin Configuration.................................................................................................. 415

Pin Configuration.................................................................................................. 432

(Smart Card Interface Mode, n = 0, s = 372)........................................................ 448

Rev. 1.00 Mar. 12, 2008 Page xliii of xIviii

Table 13.9 Maximum Bit Rate for Each Frequency

(Smart Card Interface Mode, S = 372) ................................................................. 448

Table 13.10 Serial Transfer Formats (Asynchronous Mode)................................................ 450

Table 13.11 SSR Status Flags and Receive Data Handling .................................................. 457

Table 13.12 SCI Interrupt Sources........................................................................................ 487

Table 13.13 SCI Interrupt Sources........................................................................................ 488

Section 15 Serial Communication Interface with FIFO (SCIF)

Table 15.1

Table 15.2 Register Access..................................................................................................... 508

Table 15.3 Interrupt Control Function.................................................................................... 513

Table 15.4 SCIF Output Setting ............................................................................................. 525

Table 15.5 Example of Baud Rate Settings ............................................................................ 526

Table 15.6 Correspondence Between LPC Interface I/O Address and the SCIF Registers .... 537

Table 15.7 Register States ......................................................................................................538

Table 15.8 Interrupt Sources................................................................................................... 539

Table 15.9 Interrupt Source, Vector Address, and Interrupt Priority...................................... 539

Section 16 Serial Pin Multiplexed Modes

Table 16.1

Section 17 Synchronous Serial Communication Unit (SSU)

Table 17.1

Table 17.2 Communication Modes and Pin States of SSI and SSO Pins ............................... 566

Table 17.3 Communication Modes and Pin States of SSCK Pin............................................ 567

Table 17.4 Communication Modes and Pin States of SCS Pin............................................... 567

Table 17.5 Interrupt Sources................................................................................................... 583

Pin Configuration.................................................................................................. 507

Pin Configuration.................................................................................................. 542

Pin Configuration.................................................................................................. 553

Section 18 I2C Bus Interface (IIC)

Table 18.1

Table 18.2 Transfer Format .................................................................................................... 592

Table 18.3 I2C bus Transfer Rate (1)...................................................................................... 596

Table 18.3 I2C bus Transfer Rate (2)...................................................................................... 597

Table 18.4 Flags and Transfer States (Master Mode)............................................................. 604

Table 18.5 Flags and Transfer States (Slave Mode) ............................................................... 605

Table 18.6 Output Data Hold Time ........................................................................................ 616

Table 18.7 ISCMBCR Setting ................................................................................................ 616

Table 18.8 I2C Bus Data Format Symbols.............................................................................. 618

Table 18.9 Examples of Operation Using the DTC................................................................ 647

Table 18.10 IIC Interrupt Source .......................................................................................... 650

Table 18.11 I2C Bus Timing (SCL and SDA Outputs)......................................................... 651

Table 18.12 Permissible SCL Rise Time (tsr) Values ...........................................................652

Rev. 1.00 Mar. 12, 2008 Page xliv of xIviii

Pin Configuration.................................................................................................. 588

Table 18.13 I2C Bus Timing (with Maximum Influence of tSr/tSf)........................................ 654

Section 19 LPC Interface (LPC)

Table 19.1

Table 19.2 LADR1, LADR2 Initial Values ............................................................................ 684

Table 19.3 Host Register Selection......................................................................................... 685

Table 19.4 Slave Selection Internal Registers.........................................................................685

Table 19.5 LPC I/O Cycle ...................................................................................................... 734

Table 19.6 GA20 Setting/Clearing Timing............................................................................. 740

Table 19.7 Fast Gate A20 Output Signals............................................................................... 742

Table 19.8 Scope of LPC Interface Pin Shutdown .................................................................744

Table 19.9 Scope of Initialization in Each LPC interface Mode.............................................745

Table 19.10 Serialized Interrupt Transfer Cycle Frame Configuration ................................ 748

Table 19.11 Receive Complete Interrupts and Error Interrupt.............................................. 750

Table 19.12 HIRQ Setting and Clearing Conditions when LPC Channels are Used............ 752

Table 19.13 HIRQ Setting and Clearing Conditions when SCIF Channels are Used........... 753

Table 19.14 Host Address Example...................................................................................... 755

Section 20 Ethernet Controller (EtherC)

Table 20.1

Section 22 Ethernet Controller (EtherC)

Table 22.1

Table 22.2 Example of Limitations for Setting Values........................................................... 858

Table 22.3 Example of Setting................................................................................................859

Table 22.4 Relationship between TRNTREG0 Setting and Pin Output .................................861

Table 22.5 Relationship between Pin Input and TRNTREG1 Monitoring Value................... 862

Table 22.6 Interrupt Sources................................................................................................... 863

Table 22.7 Command Decoding on Application Side............................................................. 882

Table 22.8 Selection of Peripheral Module Clock (φ) when USB Connection is Made .........894

Pin Configuration.................................................................................................. 668

Pin Configuration.................................................................................................. 759

Pin Configuration.................................................................................................. 834

Section 23 A/D Converter

Table 23.1

Table 23.2 Analog Input Channels and Corresponding ADDR Registers .............................. 899

Table 23.3 A/D Conversion Characteristics (Single Mode).................................................... 907

Table 23.4 A/D Conversion Characteristics (Scan Mode)...................................................... 907

Table 23.5 A/D Converter Interrupt Source............................................................................909

Table 23.6 Standard of Analog Pins .......................................................................................913

Section 25 Flash Memory

Table 25.1

Table 25.2 Pin Configuration.................................................................................................. 925

Table 25.3 Register/Parameter and Target Mode ...................................................................927

Pin Configuration.................................................................................................. 897

Comparison of Programming Modes.................................................................... 920

Rev. 1.00 Mar. 12, 2008 Page xlv of xIviii

Table 25.4 Parameters and Target Modes............................................................................... 937

Table 25.5 Setting On-Board Programming Mode................................................................. 947

Table 25.6 System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI......... 949

Table 25.7 Enumeration Information...................................................................................... 953

Table 25.8 Executable MAT................................................................................................... 973

Table 25.9 (1) Useable Area for Programming in User Program Mode............................... 974

Table 25.9 (2) Useable Area for Erasure in User Program Mode ........................................ 976

Table 25.9 (3) Useable Area for Programming in User Boot Mode..................................... 978

Table 25.9 (4) Useable Area for Erasure in User Boot Mode .............................................. 980

Table 25.10 Hardware Protection .........................................................................................983

Table 25.11 Software Protection........................................................................................... 984

Table 25.12 Inquiry and Selection Commands..................................................................... 992

Table 25.13 Programming/Erasing Command.................................................................... 1005

Table 25.14 Status Code ..................................................................................................... 1014

Table 25.15 Error Code ...................................................................................................... 1015

Section 26 Boundary Scan (JTAG)

Table 26.1

Table 26.2 JTAG Register Serial Transfer............................................................................1022

Table 26.3 Correspondence between Pins and Boundary Scan Register

Table 26.4 Correspondence between Pins and Boundary Scan Register

Pin Configuration................................................................................................ 1021

(H8S/2472 Group) ..............................................................................................1025

(H8S/2462 Group) .............................................................................................. 1034

Section 27 Clock Pulse Generator

Table 27.1

Table 27.2 Crystal Resonator Parameters ............................................................................. 1053

Table 27.3 Ranges of Multiplied Clock Frequency ..............................................................1054

Section 28 Power-Down Modes

Table 28.1

Table 28.2 LSI Internal States in Each Mode ....................................................................... 1066

Section 31 Electrical Characteristics

Table 31.1

Table 31.2 DC Characteristics (1) ........................................................................................ 1122

Table 31.2 DC Characteristics (2) ........................................................................................ 1124

Table 31.3 Permissible Output Currents ............................................................................... 1125

Table 31.4 Clock Timing ...................................................................................................... 1127

Table 31.5 External Clock Input Conditions ........................................................................ 1128

Table 31.6 Subclock Input Conditions.................................................................................. 1128

Table 31.7 Control Signal Timing ........................................................................................1132

Rev. 1.00 Mar. 12, 2008 Page xlvi of xIviii

Damping Resistance Values ............................................................................... 1052

Operating Frequency and Wait Time.................................................................. 1060

Absolute Maximum Ratings............................................................................... 1121

Table 31.8 Bus Timing ......................................................................................................... 1134

Table 31.9 Multiplex Bus Timing......................................................................................... 1143

Table 31.10 Timing of On-Chip Peripheral Modules .........................................................1146

Table 31.11 Timing of On-Chip Peripheral Modules (2).................................................... 1147

Table 31.12 I2C Bus Timing ...............................................................................................1152

Table 31.13 LPC Module Timing .......................................................................................1153

Table 31.14 Ethernet Controller Signal Timing.................................................................. 1155

Table 31.15 USB Characteristics when On-Chip USB Transceiver is Used

(USD+, USD− pin characteristics)..................................................................1158

Table 31.16 JTAG Timing .................................................................................................. 1160

Table 31.17 A/D Conversion Characteristics

(AN7 to AN0 Input: 80/160-State Conversion).............................................. 1162

Table 31.18 Flash Memory Characteristics ........................................................................ 1163

Appendix

Table A.1

I/O Port States in Each Processing State............................................................. 1165

Rev. 1.00 Mar. 12, 2008 Page xlvii of xIviii

Rev. 1.00 Mar. 12, 2008 Page xlviii of xIviii

Section 1 Overview

Section 1 Overview

1.1 Overview

• High-speed H8S/2600 central processing unit with an internal 16-bit architecture

Upward-compatible with H8/300 and H8/300H CPUs on an object level

Sixteen 16-bit general registers

69 basic instructions

Multiplication and accumulation instructions

• Various peripheral functions

Data transfer controller (DTC)

14-bit PWM timer (PWMX)

16-bit free-running timer (FRT)

8-bit timer (TMR)

Watchdog timer (WDT)

Asynchronous or synchronous serial communication interface (SCI)

CRC operation circuit (CRC)

Serial communication interface with FIFO (SCIF)

Synchronous serial communication unit (SSU)

2

I

C bus interface (IIC)

LPC interface (LPC)

Ethernet controller (EtherC)

Direct memory access controller for Ethernet controller (E-DMAC)

USB function module (USB)

10-bit A/D converter

Platform Environment Control Interface (PECI)

Boundary scan (JTAG)

Clock pulse generator

• On-chip memory

ROM Type Model ROM RAM Remarks

Flash memory
Version

R4F2472 512 Kbytes 40 Kbytes 176 pins,

USB incorporated

R4F2462 512 Kbytes 40 Kbytes 144 pins,

USB not incorporated

Rev. 1.00 Mar. 12, 2008 Page 1 of 1178

REJ09B0403-0100

Section 1 Overview

• Reprogramming count: 1000 times (Tpy.)

• General I/O ports

I/O pins: 110 (for 176-pin), 106 (for 144-pin)

Input-only pins: 9

• Supports various power-down states

• Compact package

Package (code) Body Size Pin Pitch

PLBG0176GA-A 13 × 13 mm 0.8 mm

PLQP0144KA-A 20 × 20 mm 0.5 mm

Rev. 1.00 Mar. 12, 2008 Page 2 of 1178

REJ09B0403-0100

1.2 Block Diagram

Section 1 Overview

Clock pulse

generator

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

[Legend]

CPU: Central processing unit
DTC: Data transfer controller
EVC: Event counter
SCI: Serial communication interface
SCIF: Serial communication interface with FIFO

2

C bus interface

IIC: I
EtherC: Ethernet controller
E-DMAC: Direct memory access controller for Ethernet controller
SSU: Synchronous serial communication unit
USB: USB function module
FRT: 16-bit free running timer
PWM: 14-bit PWM timer
LPC: LPC interface
WDT: Watchdog timer
JTAG: Boundary scan
PECI: PECI interface

EtherC

E-DMAC

EVC

Interrupt controller

SCI_1, SCI_3

S

C

IF

SSU

FRT

IIC_0 to IIC_5

Port 7

DTC

Port 8

H8S/2600

CPU

Bus controller

ROM

RAM

(Flash)

512K

40K

(+16K UB)

LPC

WDT × 2

A/D converter

J

T

AG

8-bit timer ×

C

RC calculator

USB

PECI

4

4

14-bit PWM ×

(only in the H8S/2472)

Port 9

Port F

E

Port

ort D
P

ort C
P

B

Port

A

Port

Figure 1.1 Internal Block Diagram

Rev. 1.00 Mar. 12, 2008 Page 3 of 1178

REJ09B0403-0100

Section 1 Overview

1.3 Pin Description

1.3.1 Pin Assignments

PD5

PD4

PD6

PD7

P30

1110

PD2

PD1

PD3

PD0

PB3

NC

AVSS

P70

P72

P63

VCC

NC

ETMS

ETRST

NC

P22

P15

P71

P73

P77

P60

P65

DrVCC

DrVSS

ETDO

PF2

VSS

P25

P17

P74

P75

AVref

P62

P66

USD+

VBUS

ETCK

PF0

P26

P23

P20

P76

AVCC

P61

P64

P67

USD-

PUPDPLS

ETDI

PF1

P27

P24

P21

R

P

N

M

L

K

J

H

G

F

E

D

91415131287654321

NC

R

PA4

P

PA6

N

NC

M

PC2

L

PC4

K

NC

J

NC

H

P96

G

MD2

F

STBY

E

MD1

D

NC

PA3

VCC

PC0

NC

PC3

PC7

P92

P95

P51

NMI

VSS

PA0

PA1

PA2

PA7

NC

PC5

P90

P93

P97

VCL

PF6

P56

NC

NC

NC

PA5

PC1

PC6

P91

P94

P50

NC

RES

PF3

P85

P86

P87

VSS

UXSEL

P82

P81

P83

P84

PE7

NC

NC

P80

PE4

PE3

PE5

PE6

H8S/2472 Group
PLBG0176GA-A

BP-176V

(Top view)

FWE

PEVref

P40

PE0

VCC

PE1

PE2

P34

P57

P46

VCC

P47

EXTAL

XTAL

C

B

A

P45

RESO

VSS

NC

PF4

PF5

VCC

UEXTAL

UXTAL

P54

P44

P55

PECI

P53

P52

P41

P43

P42

P35

P37

P36

91415131287654321

: NC pin

Figure 1.2 Pin Assignments (H8S/2472 Group)

Rev. 1.00 Mar. 12, 2008 Page 4 of 1178

REJ09B0403-0100

P31

P33

P32

10

PB1

PB0

VCC

11

PB6

PB4

PB2

VSS

PB7

PB5

P14

P12

P10

P16

P13

P11

C

B

A

G

P11/A1/AD1

VSS

P10/A0/AD0

PB7/EVENT15/RM_RX-ER

PB6/EVENT14/RM_CRS-DV

PB5/EVENT13/RM_REF-CLK

PB4/EVENT12/RM_TX-EN

PB3/EVENT11/DB3/RM_RXD1

PB2/EVENT10/DB2/RM_RXD0

PB1/EVENT9/DB1/RM_TXD1

PB0/EVENT8/DB0/RM_TXD0

P40/IRQ0/RS0/HC0/D4
P41/IRQ1/RS1/HC1/D5
P42/IRQ2/RS2/HC2/D6
P43/IRQ3/RS3/HC3/D7

P44/IRQ4/RS4/DB4/HC4/A12/AD12

VCC

P30/ExDB0/D8

P31/ExDB1/D9

P32/EAxDB2/D10

P33/ExDB3/D11

P34/ExDB4/D12

P35/ExDB5/D13

P36/ExDB6/D14

P37/ExDB7/D15

PEVref

PECI

P52/IRQ10/TxD1
P53/IRQ11/RxD1

FWE

P54/IRQ12/SSO

P55/IRQ13/SSI

VSS

RESO

XTAL

EXTAL

P12/A2/AD2

P13/A3/AD3

P14/A4/AD4

P15/A5/AD5

P16/A6/AD6

P17/A7/AD7

P20/A8/AD8

P21/A9/AD9

P22/A10/AD10

P23/A11/AD11

P24/DCD

P25/RI

P26/DSR

P27/DTR

VSS

PF0/RS8/MDIO

PF1/RS9/MDC

ETRST

ETCK

ETDI

ETDO

ETMS

VCC

P67/ExIRQ8/SSCK

P66/ExIRQ9/SCS

P65/ExIRQ10/RTS

P64/ExIRQ11/CTS

P63/PWX3/D3

P62/PWX2/D2

P61/IRQ15/PWX1/D1

P60/IRQ14/PWX0/D0

PC4/SCL4

PC3/SDA3

PC2/SCL3

PC1/SDA2

AVref

PC0/SCL2

108 107 106 105 104 103 102 101 100

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

VCC

P56/EXCL/φ

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73

H8S/2462 Group
PLQP0144KA-A

FP-144L

(Top view)

MD2

P51/IRQ9/RxDF

P50/IRQ8/TxDF

P97/CS256/WAIT

P96

P95/AS/IOS

P94/ExPWX1

P91/AH

P92/HBE

P93/ExPWX0

P90/LBE

PC7/RD

PC6/LWR

PC5/SDA4

P57/WR/HWR

VSS

RES

NMI

MD1

STBY

PF6/ExPWX2/RS14

VCL

Section 1 Overview

AVCC

P77/AN7

P76/AN6

P75/AN5

72

P74/AN4

71

P73/AN3

70

P72/AN2

69

P71/AN1

68

P70/AN0

67

AVSS

66

PD0/LSCI

65

PD1/LSMI

64

PD2/PME

63

PD3/GA20

62

PD4/CLKRUN

61

PD5/LPCPD

60

PD6/SCL5

59

PD7/SDA5

58

PE0/LAD0

57

PE1/LAD1

56

PE2/LAD2

55

PE3/LAD3

54

PE4/LFRAME

53

PE5/LRESET

52

PE6/LCLK

51

PE7/SERIRQ

50

P80/SCL0

49

P81/SDA0

48

P82/SCL1

47

P83/SDA1

46

P84/ExIRQ12/SCK3

45

P85/ExIRQ13/SCK1

44

P86/ExIRQ14/RxD3

43

P87/ExIRQ15/TxD3/ADTR

42

VSS

41

PA0/ExIRQ0/EVENT0/A16

40

PA1/ExIRQ1/EVENT1/A17

39

PA2/ExIRQ2/EVENT2/A18

38

PA3/ExIRQ3/EVENT3/A19

37

PA4/ExIRQ4/EVENT4/A20

VCC

PA5/ExIRQ5/EVENT5/WOL/A21

P45/IRQ5/RS5/DB5/HC5/A13/AD13

P46/IRQ6/RS6/DB6/HC6/A14/AD14

P47/IRQ7/RS7/DB7/HC7/A15/AD15

PA7/ExIRQ7/EVENT7/EXOUT/A23

PA6/ExIRQ6/EVENT6/LNKSTA/A22

Figure 1.3 Pin Assignments (H8S/2462 Group)

Rev. 1.00 Mar. 12, 2008 Page 5 of 1178

REJ09B0403-0100

Section 1 Overview

1.3.2 Pin Assignment in Each Operating Mode

Table 1.1 Pin Assignments in Each Operating Mode

Pin No. Pin Name

Flash
Memory

176-

144-

Pin

Extended Mode

Pin

(EXPE = 1)

Single-Chip Mode
(EXPE = 0)

A01 1 VCC VCC VCC
C03 2 P45/IRQ5/RS5/DB5/HC5/A13/AD13 P45/IRQ5/RS5/DB5/HC5 FA13
B01 3 P46/IRQ6/RS6/DB6/HC6/A14/AD14 P46/IRQ6/RS6/DB6/HC6 FA14
C02 4 P47/IRQ7/RS7/DB7/HC7/A15/AD15 P47/IRQ7/RS7/DB7/HC7 FA15

D03 5 P56/EXCL/phi P56/EXCL/phi NC
C01 6 WR/HWR P57 NC

D02 7 VSS VSS VSS
E04 8 RES RES RES

D01 9 MD1 MD1 VSS

E03 10 PF6/ExPWX2/RS14 PF6/ExPWX2/RS14 VSS

E02 11 NMI NMI FA9
E01 12 STBY STBY VCC

F04  NC NC NC

F03 13 VCL VCL VCL
F01 14 MD2 MD2 VCC
F02 15 P51/IRQ9/RxDF P51/IRQ9/RxDF NC
G04 16 P50/IRQ8/TxDF P50/IRQ8/TxDF NC
G03 17 CS256/WAIT P97 NC

G01 18 P96 P96 NC
G02 19 AS/IOS P95 NC

H04 20 P94/ExPWX1 P94/ExPWX1 NC

H03 21 P93/ExPWX0 P93/ExPWX0 NC

H01  NC NC NC
H02 22 P92/HBE P92 NC
J04 23 P91/AH P91 NC

Programmer
Mode

Rev. 1.00 Mar. 12, 2008 Page 6 of 1178

REJ09B0403-0100

Section 1 Overview

Pin No. Pin Name

Flash

Memory
176­Pin

144-

Extended Mode

Pin

(EXPE = 1)

Single-Chip Mode
(EXPE = 0)

Programmer

Mode

J03 24 P90/LBE P90 NC

J01  NC NC NC
J02 25 RD PC7 WE
K04 26 PC6/LWR PC6 NC

K03 27 PC5/SDA4 PC5/SDA4 NC

K01 28 PC4/SCL4 PC4/SCL4 NC

K02 29 PC3/SDA3 PC3/SDA3 NC

L03  NC NC NC

L01 30 PC2/SCL3 PC2/SCL3 NC

L02  NC NC NC

L04 31 PC1/SDA2 PC1/SDA2 NC

M01  NC NC NC

M02 32 PC0/SCL2 PC0/SCL2 NC
M03 33 PA7/ExIRQ7/EVENT7/EXOUT/A23 PA7/ExIRQ7/EVENT7/EXOUT VCC
N01 34 PA6/ExIRQ6/EVENT6/LNKSTA/A22 PA6/ExIRQ6/EVENT6/LNKSTA VCC
M04 35 PA5/ExIRQ5/EVENT5/WOL/A21 PA5/ExIRQ5/EVENT5/WOL VSS

N02 36 VCC VCC VCC
P01 37 PA4/ExIRQ4/EVENT4/A20 PA4/ExIRQ4/EVENT4 CE
P02 38 PA3/ExIRQ3/EVENT3/A19 PA3/ExIRQ3/EVENT3 FA19

R01  NC NC NC
N03 39 PA2/ExIRQ2/EVENT2/A18 PA2/ExIRQ2/EVENT2 FA18

R02  NC NC NC
P03 40 PA1/ExIRQ1/EVENT1/A17 PA1/ExIRQ1/EVENT1 FA17

N04  NC NC NC
R03 41 PA0/ExIRQ0/EVENT0/A16 PA0/ExIRQ0/EVENT0 FA16

P04  NC NC NC

M05 42 VSS VSS VSS

R04  NC NC NC

Rev. 1.00 Mar. 12, 2008 Page 7 of 1178

REJ09B0403-0100

Section 1 Overview

Pin No. Pin Name

Flash

Memory
176­Pin

144-

Extended Mode

Pin

(EXPE = 1)

Single-Chip Mode
(EXPE = 0)

Programmer

Mode

N05 43 P87/ExIRQ15/TxD3/ADTRG P87/ExIRQ15/TxD3/ADTRG NC
P05 44 P86/ExIRQ14/RxD3 P86/ExIRQ14/RxD3 NC
R05 45 P85/ExIRQ13/SCK1 P85/ExIRQ13/SCK1 NC
M06 46 P84/ExIRQ12/SCK3 P84/ExIRQ12/SCK3 NC

N06 47 P83/SDA1 P83/SDA1 NC

R06 48 P82/SCL1 P82/SCL1 NC

P06 49 P81/SDA0 P81/SDA0 NC

M07 50 P80/SCL0 P80/SCL0 NC

N07  NC NC NC

R07 51 PE7/SERIRQ PE7/SERIRQ NC

P07  NC NC NC

M08 52 PE6/LCLK PE6/LCLK NC
N08 53 PE5/LRESET PE5/LRESET NC
R08 54 PE4/LFRAME PE4/LFRAME NC

P08 55 PE3/LAD3 PE3/LAD3 NC

M09 56 PE2/LAD2 PE2/LAD2 NC

N09 57 PE1/LAD1 PE1/LAD1 NC

R09 58 PE0/LAD0 PE0/LAD0 NC

P09  VCC VCC NC

M10 59 PD7/SDA5 PD7/SDA5 NC

N10 60 PD6/SCL5 PD6/SCL5 NC
R10 61 PD5/LPCPD PD5/LPCPD NC
P10 62 PD4/CLKRUN PD4/CLKRUN NC

N11 63 PD3/GA20 PD3/GA20 NC
R11 64 PD2/PME PD2/PME NC
P11 65 PD1/LCMI PD1/LCMI NC

M11 66 PD0/LSCI PD0/LSCI NC

R12  NC NC NC

Rev. 1.00 Mar. 12, 2008 Page 8 of 1178

REJ09B0403-0100

Section 1 Overview

Pin No. Pin Name

Flash

Memory
176­Pin

144-

Extended Mode

Pin

(EXPE = 1)

Single-Chip Mode
(EXPE = 0)

Programmer

Mode

P12 67 AVSS AVSS VSS

N12 68 P70/AN0 P70/AN0 NC

R13 69 P71/AN1 P71/AN1 NC

M12 70 P72/AN2 P72/AN2 NC

P13 71 P73/AN3 P73/AN3 NC

R14 72 P74/AN4 P74/AN4 NC

P14 73 P75/AN5 P75/AN5 NC

R15 74 P76/AN6 P76/AN6 NC

N13 75 P77/AN7 P77/AN7 NC

P15 76 AVCC AVCC VCC

N14 77 AVref AVref VCC
M13 78 P60/IRQ14/PWX0/D0 P60/IRQ14/PWX0 NC
N15 79 P61/IRQ15/PWX1/D1 P61/IRQ15/PWX1 NC

M14 80 P62/PWX2/D2 P62/PWX2 NC

L12 81 P63/PWX3/D3 P63/PWX3 NC
M15 82 P64/ExIRQ11/CTS P64/ExIRQ11/CTS NC
L13 83 P65/ExIRQ10/RTS P65/ExIRQ10/RTS NC
L14 84 P66/ExIRQ9/SCS P66/ExIRQ9/SCS NC
L15 85 P67/ExIRQ8/SSCK P67/ExIRQ8/SSCK NC

K12 86 VCC VCC VCC

K13  DrVCC DrVCC VCC

K15  USD− USD− NC

K14  USD+ USD+ NC

J12  NC NC NC

J13  DrVSS DrVSS VSS

J15  PUPDPLS PUPDPLS NC

J14  VBUS VBUS NC

H12 87 ETMS ETMS NC

Rev. 1.00 Mar. 12, 2008 Page 9 of 1178

REJ09B0403-0100

Section 1 Overview

Pin No. Pin Name

Flash

Memory
176­Pin

144-

Extended Mode

Pin

(EXPE = 1)

Single-Chip Mode
(EXPE = 0)

Programmer

Mode

H13 88 ETDO ETDO NC

H15 89 ETDI ETDI NC

H14 90 ETCK ETCK NC
G12 91 ETRST ETRST RES

G13  PF2/RS10 PF2/RS10 NC

G15 92 PF1/RS9/MDC PF1/RS9/MDC NC

G14 93 PF0/RS8/MDIO PF0/RS8/MDIO NC

F12  NC NC NC

F13 94 VSS VSS VSS
F15 95 P27/DTR P27/DTR NC
F14 96 P26/DSR P26/DSR NC
E13 97 P25/RI P25/RI NC
E15 98 P24/DCD P24/DCD NC

E14 99 P23/A11/AD11 P23 FA11

E12 100 P22/A10/AD10 P22 FA10
D15 101 P21/A9/AD9 P21 OE

D14 102 P20/A8/AD8 P20 FA8

D13 103 P17/A7/AD7 P17 FA7

C15 104 P16/A6/AD6 P16 FA6

D12 105 P15/A5/AD5 P15 FA5

C14 106 P14/A4/AD4 P14 FA4

B15 107 P13/A3/AD3 P13 FA3

B14 108 P12/A2/AD2 P12 FA2

A15 109 P11/A1/AD1 P11 FA1

C13 110 VSS VSS VSS

A14 111 P10/A0/AD0 P10 FA0

B13 112 PB7/EVENT15/RM_RX-ER PB7/EVENT15/RM_RX-ER NC

C12 113 PB6/EVENT14/RM_CRS-DV PB6/EVENT14/RM_CRS-DV NC

Rev. 1.00 Mar. 12, 2008 Page 10 of 1178

REJ09B0403-0100

Section 1 Overview

Pin No. Pin Name

Flash

Memory
176­Pin

144-

Extended Mode

Pin

(EXPE = 1)

Single-Chip Mode
(EXPE = 0)

Programmer

Mode

A13 114 PB5/EVENT13/RM_REF-CLK PB5/EVENT13/RM_REF-CLK NC

B12 115 PB4/EVENT12/RM_TX-EN PB4/EVENT12/RM_TX-EN NC

D11 116 PB3/EVENT11/DB3/RM_RXD1 PB3/EVENT11/DB3/RM_RXD1 NC

A12 117 PB2/EVENT10/DB2/RM_RXD0 PB2/EVENT10/DB2/RM_RXD0 NC

C11 118 PB1/EVENT9/DB1/RM_TXD1 PB1/EVENT9/DB1/RM_TXD1 NC

B11 119 PB0/EVENT8/DB0/RM_TXD0 PB0/EVENT8/DB0/RM_TXD0 NC

A11 120 VCC VCC VCC

D10 121 D8 P30/ExDB0 FO0

C10 122 D9 P31/ExDB1 FO1

A10 123 D10 P32/ExDB2 FO2

B10 124 D11 P33/ExDB3 FO3

D09 125 D12 P34/ExDB4 FO4

C09 126 D13 P35/ExDB5 FO5

A09 127 D14 P36/ExDB6 FO6

B09 128 D15 P37/ExDB7 FO7
D08 129 P40/IRQ0/RS0/HC0/D4 P40/IRQ0/RS0/HC0 NC
C08 130 P41/IRQ1/RS1/HC1/D5 P41/IRQ1/RS1/HC1 NC
A08 131 P42/IRQ2/RS2/HC2/D6 P42/IRQ2/RS2/HC2 NC
B08 132 P43/IRQ3/RS3/HC3/D7 P43/IRQ3/RS3/HC3 NC

D07 133 PEVref PEVref VSS

C07 134 PECI PECI NC
A07 135 P52/IRQ10/TxD1 P52/IRQ10/TxD1 VCC
B07 136 P53/IRQ11/RxD1 P53/IRQ11/RxD1 VSS

D06 137 FWE FWE FWE
C06 138 P54/IRQ12/SSO P54/IRQ12/SSO NC
A06 139 P55/IRQ13/SSI P55/IRQ13/SSI NC
B06 140 P44/IRQ4/RS4/DB4/HC4/A12/AD12 P44/IRQ4/RS4/DB4/HC4 FA12

C05  VCC VCC VCC

Rev. 1.00 Mar. 12, 2008 Page 11 of 1178

REJ09B0403-0100

Section 1 Overview

Pin No. Pin Name

Flash

Memory
176­Pin

144-

Extended Mode

Pin

(EXPE = 1)

Single-Chip Mode
(EXPE = 0)

Programmer

Mode

A05  UXTAL UXTAL NC

B05  UEXTAL UEXTAL NC

D05  UXSEL UXSEL NC

A04  PF5/RS13 PF5/RS13 NC

B04  PF4/RS12 PF4/RS12 NC

C04  NC NC NC

A03 141 VSS VSS VSS

D04  PF3/ExPWX3/RS11 PF3/ExPWX3/RS11 NC
B03 142 RESO RESO NC

A02 143 XTAL XTAL XTAL

B02 144 EXTAL EXTAL EXTAL

Rev. 1.00 Mar. 12, 2008 Page 12 of 1178

REJ09B0403-0100

Section 1 Overview

1.3.3 Pin Functions

Table 1.2 Pin Functions

Pin No.

Type Symbol 176-Pin 144-Pin I/O Name and Function

Power
supply

Clock

VCC A1, N2,

P9, K12,
A11, C5

VCL F3 13 Input External capacitance pin for internal step-

VSS D2, M5,

F13, C13,
A3

XTAL A2 143 Input

EXTAL B2 144 Input

UXTAL A5  Input

UEXTAL B5  Input

UXSEL D5  Input USB clock source select pin

φ D3 5 Output Supplies the system clock to external

EXCL D3 5 Input 32.768-kHz external clock for sub clock

1, 36, 86,
120

7, 42, 94,
110, 141

Input Power supply pins. Connect all these pins

to the system power supply. Connect the
bypass capacitor between VCC and VSS
(near VCC).

down power. Connect this pin to Vss
through an external capacitor (that is
located near this pin) to stabilize internal
step-down power.

Input Ground pins. Connect all these pins to the

system power supply (0V).

For connection to a crystal resonator. An
external clock can be supplied from the
EXTAL pin. For an example of crystal
resonator connection, see section 27,
Clock Pulse Generator.

For connection to a crystal resonator for
USB

devices.

should be supplied.

Operating
mode control

MD2

MD1

F1
D1

14
9

Input These pins set the operating mode.

Inputs at these pins should not be
changed during operation.

System
control

RES E4 8 Input Reset pin. When this pin is low, the chip

is reset.

RESO B3 142 Output Outputs a reset signal to an external

device.

STBY E1 12 Input When this pin is low, a transition is made

to hardware standby mode.

FWE D6 137 Input Pin for use by flash memory.

Rev. 1.00 Mar. 12, 2008 Page 13 of 1178

REJ09B0403-0100

Section 1 Overview

Pin No.

Type Symbol 176-Pin 144-Pin I/O Name and Function

Address bus

A23 to A16 M3, N1,

M4, P1,

33 to 35,
37 to 41

Output Address output pins

P2, N3,
P3, R3

A15 to A0 C2, B1,

C3, B6,
E14, E12,
D15,

4 to 2,
140,
99 to 109,

111
D14,
D13,
C15,
D12,
C14, B15,
B14, A15,
A14

Data bus

D15 to D8 B9, A9,

C9, D9,

128 to

121

Input/
Output

Upper 8 bits of bidirectional bus

B10, A10,
C10, D10

D7 to D0 B8, A8,

C8, D8,
L12, M14,

132 to

129,

81 to 78

Lower 8 bits of bidirectional bus

N15, M13

Address­data
multiplex bus

AD15 to AD8 C2, B1,

C3, B6,
E14, E12,

4 to 2,

140,

99 to 102

Input/
Output

8 bit bus or upper 8 bits of 16-bit bus

D15, D14

AD7 to AD0 D13,

C15,

103 to

109, 111

Lower 8 bits of 16-bit bus

D12,
C14, B15,
B14, A15,
A14

Rev. 1.00 Mar. 12, 2008 Page 14 of 1178

REJ09B0403-0100

Section 1 Overview

Pin No.

Type Symbol 176-Pin 144-Pin I/O Name and Function

Interrupts

NMI E2 11 Input Nonmaskable interrupt request input pin

IRQ15 to
IRQ0

N15,
M13, A6,
C6, B7,
D6, F2,
G4, C2,
B1, C3,
B6, B8,
A8, C8,

79, 78,
139, 138,
136, 135,
15, 16,
4 to 2,
140,
132 to
129

Input These pins are used to request maskable

interrupts.
Either IRQn or ExIRQn can be selected

as the IRQn interrupt signal input pin.

D8

ExIRQ15 to
ExIRQ0

N5, P5,
R5, M6,
M15, L13,
L14, L15,
M3, N1,

43 to 46,
82 to 85,
33 to 35,
37 to 41

Input These pins are used to request maskable

interrupts.
Either IRQn or ExIRQn can be selected

as the IRQn interrupt signal input pin.

M4, P1,
P2, N3,
P3, R3

Bus control

WAIT G3

17 Input

Requests wait state insertion to bus
cycles when an external tri-state address
space is accessed.

RD J2

25 Output

Low level on this pin indicates that the
MCU is reading from an external address
space.

HWR C1

6 Output

Low level on this pin indicates that the
MCU is writing to an external address
space.
The upper byte of the data bus is valid.

LWR K4

26 Output

Low level on this pin indicates that the
MCU is writing to an external address
space.
The lower byte of the data bus is valid.

AS/IOS G2

19 Output

Low level on this pin indicates that the
address output on the address bus is
valid.

CS256 G3

17 Output

Indicates access to the 256-Kbyte area of
H’F80000 to H’FBFFFF.

Rev. 1.00 Mar. 12, 2008 Page 15 of 1178

REJ09B0403-0100

Section 1 Overview

Pin No.

Type Symbol 176-Pin 144-Pin I/O Name and Function

Bus control

WR C1

6 Output

Low level on this pin indicates that the
MCU is writing to an external address
space.

HBE H2

22 Output

Low level on this pin indicates that the
MCU is accessing an external address
space.
The upper byte of the data bus is valid.

LBE J3

24 Output

Low level on this pin indicates that the
MCU is accessing an external address
space.
The lower byte of the data bus is valid.

AH J4

23 Output

Address latch signal for the address-data
multiplex bus

Boundary
scan

ETRST G12 91 Input

ETMS H12 87 Input

Boundary scan interface pins

ETDO H13 88 Output

ETDI H15 89 Input

ETCK H14 90 Input

14-bit PWM
timer
(PWMX)

PWX0 to
PWX3
ExPWX0 to
ExPWX2

M13,
N15,
M14, L12,
H3, H4,

78 to 81,

21, 20, 10

Output PWM D/A pulse output pins

E3

Serial
communi­cation
interface
(SCI_1 and

TxD1, TxD3 A7, N5 135, 43 Output Transmit data output pins

RxD1, RxD3 B7, P5 136, 44 Input Receive data input pins

SCK1, SCK3 R5, M6 45, 46

Input/

Clock input/output pins.

Output

SCI_3)

Serial
communi­cation
interface
with FIFO
(SCIF)

TxDF G4 16 Output Transmit data output pin

RxDF F2 15 Input Receive data input pin

CTS M15 82 Input Transmit grant input pin
RTS L13 83 Output Transmit request output pin
DTR F15 95 Output Data terminal ready output pin
DSR F14 96 Input Data set ready input pin
RI E13 97 Input Ring indicator input pin
DCD E15 98 Input Data carrier detection input pin

Rev. 1.00 Mar. 12, 2008 Page 16 of 1178

REJ09B0403-0100

Section 1 Overview

Pin No.

Type Symbol 176-Pin 144-Pin I/O Name and Function

Synchronous
serial
communi­cation unit
(SSU)

SSCK L15 85

Input/
Output

SSI A6 84

Input/
Output

SSO C6 138

Input/

SSU clock I/O pin

SSU data I/O pin

SSU data I/O pin

Output

SCS L14 139

Input/

SSU chip select I/O pin

Output

I2C bus
interface
(IIC)

A/D
converter

SCL0 to SCL5

M7, R6,
M2, L1,
K1, N10

SDA0 to
SDA5

P6, N6,
L4, K2,
K3, M10

AN7 to AN0 N13,

R15, P14,

50, 48,
32, 30,
28, 60

49, 47,
31, 29,
27, 59

75 to 68 Input Analog input pins

Input/
Output

Input/
Output

IIC clock input/output pins. These pins
can drive a bus directly with the NMOS
open drain output.

IIC data input/output pins. These pins can
drive a bus directly with the NMOS open
drain output.

R14, P13,
M12,
R13, N12

AVCC P15 76 Input

Analog power supply pins. When the A/D
converter is not used, these pins should
be connected to the system power supply
(+3.3 V).

AVref N14 77 Input

Analog reference voltage input pin. When
the A/D converter is not used, this pin
should be connected to the system power
supply (+3.3 V).

AVSS P12 67 Input

Analog ground pins. These pins should
be connected to the system power supply
(0 V).

ADTRG N5 43 Input

External trigger input pin to start A/D
conversion

Rev. 1.00 Mar. 12, 2008 Page 17 of 1178

REJ09B0403-0100

Section 1 Overview

Pin No.

Type Symbol 176-Pin 144-Pin I/O Name and Function

LPC
Interface
(LPC)

LAD3 to LAD0

P8, M9,
N9, R9

55 to 58

Input/
Output

LFRAME R8 54 Input

Transfer cycle type/address/data I/O pins

Input pin indicating transfer cycle start
and forced termination

LRESET N8 53 Input

LPC reset pin. When this pin is low, a
reset state is entered.

LCLK M8 52 Input PCI clock input pin

SERIRQ R7 51

LSCI,

LSMI,
PME

M11
P11
R11

66

65

64

GA20 N11 63

Input/
Output

Input/
Output

Input/
Output

LPC serialized host interrupt request
signal

LPC auxiliary output. Their functions are
general I/O port.

GATE A20 control signal output pin; also
used as the input pin for monitoring the
output state.

CLKRUN P10 62

Input/
Output

Input/output pin used to request starting
the LCLK operation while LCLK is
stopped.

LPCPD R10 61 Input

Input pin used to control shutdown of the
LCP module

Ethernet
controller
(EtherC)

RM_REF-CLK A13

RM_TX-EN B12

RM_TXD1
RM_TXD0

C11
B11

RM_CRS-DV C12

RM_RXD1
RM_RXD0

D11
A12

RM_RX-ER B13

MDC G15

MDIO G14

114 Input

115 Output

118

119

Output
Output

113 Input

116

117

Input
Input

112 Input

92 Input

93

Input/

Transmit/receive Clock

Transmit enable

Transmit data

Carrier detection/receive data valid

Receive data

Receive error

Management data clock

Management data I/O

Output

LNKSTA N1 34 Input Link status

EXOUT M3 33 Output General-purpose external output

WOL M4 35 Output Wake-on-LAN

Rev. 1.00 Mar. 12, 2008 Page 18 of 1178

REJ09B0403-0100

Section 1 Overview

Pin No.

Type Symbol 176-Pin 144-Pin I/O Name and Function

USB function
module
(USB)

VBUS J14

USD+ K14

USD− K15

 Input USB cable connection monitor pin



Input/

USB data I/O pin

Output



Input/

USB data I/O pin

Output

DrVcc K13

 Input

Power supply pin for USB built-in
transceiver

 Input

 Output

112 to

Input Event counter input pins

Ground pin for USB built-in transceiver

USB+ pull-up control pin

119,
33 to 35,
37 to 41

Event
Counter

DrVss J13

PUPDPLS J15

EVENT15 to
EVENT0

B13, C12,
A13, B12,
D11, A12,
C11, B11,
M3, N1,
M4, P1,
P2, N3,
P3, R3

Retain state
output pins

RS14,
RS13 to
RS10,
RS9 to RS0

E3 10

A4, B4,



D4, G13

G15,
G14, C2,
B1, C3,
B6, B8,
A8, C8,

92, 93,
4 to 2,
140,
132 to
129

Output Retain state output pins.

The outputs on these pins are only
initialized by a system reset.
Pins RS13 to RS10 are available only in
the H8S/2472 Group.

D8

Debounced
input pins

DB7 to DB0

C2, B1,
C3, B6,
D11, A12,

4 to 2,
140, 116
to 119

Input Pins with noise eliminating functions.

C11, B11

ExDB7 to
ExDB0

B9, A9,
C9, D9,

128 to

121
B10, A10,
C10, D10

Large
current
output pins

HC7 to HC0 C2, B1,

C3, B6,
B8, A8,

4 to 2,

140, 132

to 129

Output These pins can be used to drive LEDs or

for other purposes where large currents
are required.

C8, D8

Rev. 1.00 Mar. 12, 2008 Page 19 of 1178

REJ09B0403-0100

Section 1 Overview

Pin No.

Type Symbol 176-Pin 144-Pin I/O Name and Function

I/O ports

P17 to P10 D13,

C15,

103 to
109, 111

Input/
Output

8-bit input/output pins

D12,
C14, B15,
B14, A15

P27 to P20 F15, F14,

E13, E15,

95 to 102 Input/

Output

8-bit input/output pins

E14, E12,
D15, D14

P37 to P30 B9, A9,

C9, D9,

128 to
121

Input/
Output

8-bit input/output pins

B10, A10,
C10, D10

P47 to P40 C2, B1,

C3, B6,
B8, A8,

4 to 2,
140, 132
to 129

Input/
Output

8-bit input/output pins

C8, D8

P57 to P50 C1, D3,

A6, C6,
B7, A7,
F2, G4

P67 to P60 L15, L14,

L13, M15,

6, 5, 139,
138, 136,

Input/

Output
135, 15,
16

85 to 78 Input/

Output

8-bit input/output pins

8-bit input/output pins

L12, M14,
N15, M13

P77 to P70 N13,

75 to 68 Input 8-bit input pins

R15, P14,
R14, P13,
M12,
R13, N12

P87 to P80 N5, P5,

R5, M6,

43 to 50 Input/

Output

8-bit input/output pins

N6, R6,
P6, M7

P97 to P90 G3, G1,

G2, H4,

17 to 24 Input/

Output

8-bit input/output pins

H3, H2,
J4, J3

Rev. 1.00 Mar. 12, 2008 Page 20 of 1178

REJ09B0403-0100

Section 1 Overview

Pin No.

Type Symbol 176-Pin 144-Pin I/O Name and Function

I/O ports

PA7 to PA0 M3, N1,

M4, P1,

33 to 35,
37 to 41

Input/
Output

8-bit input/output pins

P2, N3,
P3, R3

PB7 to PB0 B13, C12,

A13, B12,

112 to
119

Input/
Output

8-bit input/output pins

D11, A12,
C11, B11

PC7 to PC0 J2, K4,

K3, K1,

25 to 32 Input/

Output

8-bit input/output pins

K2, L1,
L4, M2

PD7 to PD0 M10,

N10,

59 to 66 Input/

Output

8-bit input/output pins

R10, P10,
N11,
R11, P11,
M11

PE7 to PE0 R7, M8,

N8, R8,

51 to 58 Input/

Output

8-bit input/output pins

P8, M9,
N9, R9

PF6, PF5 to
PF2, PF1,
PF0

E3 10

A4, B4,



Input/
Output

7-bit input/output pins.
Pins PF5 to PF2 are available only in the
H8S/2472 Group.

D4, G13

G15, G14 92, 93

Rev. 1.00 Mar. 12, 2008 Page 21 of 1178

REJ09B0403-0100

Section 1 Overview

Rev. 1.00 Mar. 12, 2008 Page 22 of 1178

REJ09B0403-0100

Section 2 CPU

Section 2 CPU

The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit
general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
This section describes the H8S/2600 CPU. The usable modes and address spaces differ depending
on the product. For details on each product, refer to section 3, MCU Operating Modes.

2.1 Features

• Upward-compatible with H8/300 and H8/300H CPUs

 Can execute H8/300 and H8/300H CPUs object programs

• General-register architecture

 Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers

• Sixty-nine basic instructions

 8/16/32-bit arithmetic and logic instructions

 Multiply and divide instructions

 Powerful bit-manipulation instructions

 Multiply-and-accumulate instruction

• Eight addressing modes

 Register direct [Rn]

 Register indirect [@ERn]

 Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]

 Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]

 Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]

 Immediate [#xx:8, #xx:16, or #xx:32]

 Program-counter relative [@(d:8,PC) or @(d:16,PC)]

 Memory indirect [@@aa:8]

• 16-Mbyte address space

 Program: 16 Mbytes

 Data: 16 Mbytes

• High-speed operation

 All frequently-used instructions execute in one or two states

 8/16/32-bit register-register add/subtract: 1 state

 8 × 8-bit register-register multiply: 2 states

Rev. 1.00 Mar. 12, 2008 Page 23 of 1178

REJ09B0403-0100

Section 2 CPU

 16 ÷ 8-bit register-register divide: 12 states

 16 × 16-bit register-register multiply: 3 states

 32 ÷ 16-bit register-register divide: 20 states

• Two CPU operating modes

 Normal mode*

 Advanced mode

• Power-down state

 Transition to power-down state by the SLEEP instruction

 CPU clock speed selection

Note: * Normal mode is not available in this LSI.

2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU

The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below.

• Register configuration

The MAC register is supported by the H8S/2600 CPU only.

• Basic instructions

The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported by the H8S/2600
CPU only.

• The number of execution states of the MULXU and MULXS instructions;

Execution States
Instruction Mnemonic H8S/2600 H8S/2000

MULXU.B Rs, Rd 2* 12 MULXU

MULXU.W Rs, ERd 2* 20

MULXS.B Rs, Rd 3* 13 MULXS

MULXS.W Rs, ERd 3* 21

CLRMAC CLRMAC 1*

LDMAC ERs,MACH 1* LDMAC

LDMAC ERs,MACL 1*

STMAC MACH,ERd 1* STMAC

STMAC MACl,ERd 1*

Note: * This becomes one state greater immediately after a MAC instruction.
In addition, there are differences in address space, CCR and EXR register functions,

and power-down modes, etc., depending on the model.

Not supported

Rev. 1.00 Mar. 12, 2008 Page 24 of 1178

REJ09B0403-0100

Section 2 CPU

2.1.2 Differences from H8/300 CPU

In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements:

• More general registers and control registers

 Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been

added.

• Expanded address space

 Normal mode supports the same 64-kbyte address space as the H8/300 CPU.

 Advanced mode supports a maximum 16-Mbyte address space.

• Enhanced addressing

 The addressing modes have been enhanced to make effective use of the 16-Mbyte address

space.

• Enhanced instructions

 Addressing modes of bit-manipulation instructions have been enhanced.

 Signed multiply and divide instructions have been added.

 A multiply-and-accumulate instruction has been added.

 Two-bit shift instructions have been added.

 Instructions for saving and restoring multiple registers have been added.

 A test and set instruction has been added.

• Higher speed

 Basic instructions execute twice as fast.

2.1.3 Differences from H8/300H CPU

In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements:

• More control registers

 One 8-bit and two 32-bit control registers have been added.

• Enhanced instructions

 Addressing modes of bit-manipulation instructions have been enhanced.

 A multiply-and-accumulate instruction has been added.

 Two-bit shift instructions have been added.

 Instructions for saving and restoring multiple registers have been added.

 A test and set instruction has been added.

• Higher speed

 Basic instructions execute twice as fast.

Rev. 1.00 Mar. 12, 2008 Page 25 of 1178

REJ09B0403-0100

Section 2 CPU

2.2 CPU Operating Modes

The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address
space. The mode is selected by the mode pins.

2.2.1 Normal Mode

The exception vector table and stack have the same structure as in the H8/300 CPU.

• Address Space

Linear access to a 64-kbyte maximum address space is provided.

• Extended Registers (En)

The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even
when the corresponding general register (Rn) is used as an address register. If the general
register is referenced in the register indirect addressing mode with pre-decrement (@–Rn) or
post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding
extended register (En) will be affected.

• Instruction Set

All instructions and addressing modes can be used. Only the lower 16 bits of effective
addresses (EA) are valid.

• Exception Vector Table and Memory Indirect Branch Addresses

In normal mode the top area starting at H'0000 is allocated to the exception vector table. One
branch address is stored per 16 bits. The exception vector table structure in normal mode is
shown in figure 2.1. For details of the exception vector table, see section 4, Exception
Handling.

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In normal mode the operand is a 16-bit word operand,
providing a 16-bit branch address. Branch addresses can be stored in the area from H'0000 to
H'00FF. Note that the first part of this range is also used for the exception vector table.

• Stack Structure

When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC,
condition-code register (CCR), and extended control register (EXR) are pushed onto the stack
in exception handling, they are stored as shown in figure 2.2. EXR is not pushed onto the stack
in interrupt control mode 0. For details, see section 4, Exception Handling.

Note: Normal mode is not available in this LSI.

Rev. 1.00 Mar. 12, 2008 Page 26 of 1178

REJ09B0403-0100

Section 2 CPU

H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B

Exception vector 1

Exception vector 2

Exception vector 3

Exception vector 4

Exception vector 5

Exception vector 6

Figure 2.1 Exception Vector Table (Normal Mode)

SP SP

PC

(16 bits)

(SP

Exception
vector table

1

EXR*

2

*

)

Reserved*

CCR

CCR*

(16 bits)

PC

1

,

3

*

3

(b) Exception Handling(a) Subroutine Branch

1. When EXR is not used it is not stored on the stack.

Notes:

2. SP when EXR is not used.

3. lgnored when returning.

Figure 2.2 Stack Structure in Normal Mode

Rev. 1.00 Mar. 12, 2008 Page 27 of 1178

REJ09B0403-0100

Section 2 CPU

2.2.2 Advanced Mode

• Address Space

Linear access to a 16-Mbyte maximum address space is provided.

• Extended Registers (En)

The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers or address registers.

• Instruction Set

All instructions and addressing modes can be used.

• Exception Vector Table and Memory Indirect Branch Addresses

In advanced mode, the top area starting at H'00000000 is allocated to the exception vector
table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is
stored in the lower 24 bits (figure 2.3). For details of the exception vector table, see section 4,
Exception Handling.

H'00000000

H'00000003

H'00000004

H'00000007

H'00000008

H'0000000B

H'0000000C

H'00000010

Reserved

Exception vector 1

Reserved

Exception vector 2

Reserved

Exception vector 3

Reserved

Exception vector 4

Reserved

Exception vector 5

Exception vector table

Figure 2.3 Exception Vector Table (Advanced Mode)

Rev. 1.00 Mar. 12, 2008 Page 28 of 1178

REJ09B0403-0100

Section 2 CPU

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In advanced mode the operand is a 32-bit longword operand,
providing a 32-bit branch address. The upper 8 bits of these 32 bits is a reserved area that is
regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF.
Note that the first part of this range is also used for the exception vector table.

• Stack Structure

In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine
call, and the PC, condition-code register (CCR), and extended control register (EXR) are
pushed onto the stack in exception handling, they are stored as shown in figure 2.4. When
EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4,
Exception Handling.

1

EXR*

Reserved*

CCR

PC

(24 bits)

1

,

3

*

SP

Reserved

PC

(24 bits)

SP

(SP

2

*

)

(a) Subroutine Branch (b) Exception Handling

Notes: 1. When EXR is not used it is not stored on the stack.

2. SP when EXR is not used.

3. Ignored when returning.

Figure 2.4 Stack Structure in Advanced Mode

Rev. 1.00 Mar. 12, 2008 Page 29 of 1178

REJ09B0403-0100

Section 2 CPU

2.3 Address Space

Figure 2.5 shows a memory map for the H8S/2600 CPU. The H8S/2600 CPU provides linear
access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte
(architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces
differ depending on the product. For details on each product, refer to section 3, MCU Operating
Modes.

H'0000

H'FFFF

H'00000000

64-kbyte 16-Mbyte

H'00FFFFFF

Cannot be
used in this LSI

H'FFFFFFFF

(b) Advanced Mode(a) Normal Mode

Figure 2.5 Memory Map

Program area

Data area

Rev. 1.00 Mar. 12, 2008 Page 30 of 1178

REJ09B0403-0100

Section 2 CPU

2.4 Registers

The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers;
general registers and control registers. The control registers are a 24-bit program counter (PC), an
8-bit extended control register (EXR), an 8-bit condition code register (CCR), and a 64-bit
multiply-accumulate register (MAC).

General Registers (Rn) and Extended Registers (En)

15 0 7 0 7 0

ER0

ER1

ER2

ER3

ER4

ER5

ER6

ER7 (SP)

E0

E1

E2

E3

E4

E5

E6

E7

R0H

R1H

R2H

R3H

R4H

R5H

R6H

R7H

R0L

R1L

R2L

R3L

R4L

R5L

R6L

R7L

Control Registers (CR)

63 3241

MAC

31 0

[Legend]

SP:

Stack pointer

PC:

Program counter

EXR:

Extended control register

T:

Trace bit
Interrupt mask bits

I2 to I0:
CCR:

Condition-code register

I:

Interrupt mask bit

UI:

User bit or interrupt mask bit

23

Sign extension

MACL

PC

Half-carry flag

H:

User bit

U:

Negative flag

N:

Zero flag

Z:

Overflow flag

V:

Carry flag

C:

Multiply-accumulate register

MAC:

Figure 2.6 CPU Registers

76543210

TI2I1I0

EXR

----

76543210

CCR

IUIHUNZVC

MACH

0

Rev. 1.00 Mar. 12, 2008 Page 31 of 1178

REJ09B0403-0100

Section 2 CPU

2.4.1 General Registers

The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally
identical and can be used as both address registers and data registers. When a general register is
used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates
the usage of the general registers. When the general registers are used as 32-bit registers or address
registers, they are designated by the letters ER (ER0 to ER7).

The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.

The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8­bit registers.

The usage of each register can be selected independently.

General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the
stack.

• Address registers

• 32-bit registers

ER registers

(ER0 to ER7)

• 16-bit registers • 8-bit registers

E registers (extended registers)

(E0 to E7)

R registers

(R0 to R7)

Figure 2.7 Usage of General Registers

Rev. 1.00 Mar. 12, 2008 Page 32 of 1178

REJ09B0403-0100

RH registers

(R0H to R7H)

RL registers
(R0L to R7L)

Section 2 CPU

Free area

SP (ER7)

Stack area

Figure 2.8 Stack

2.4.2 Program Counter (PC)

This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched, the least significant PC bit is regarded as 0).

2.4.3 Ext e nded Control Register (EXR)

EXR is an 8-bit register that manipulates the LDC, STC, ANDC, ORC, and XORC instructions.
When these instructions, except for the STC instruction, are executed, all interrupts including NMI
will be masked for three states after execution is completed.

Initial

Bit Bit Name

Value

7 T 0 R/W Trace Bit

6 to 3  All 1  Reserved

2

1

0

I2

I1

I0

1

1

1

Rev. 1.00 Mar. 12, 2008 Page 33 of 1178

REJ09B0403-0100

R/W Description

When this bit is set to 1, a trace exception is generated
each time an instruction is executed. When this bit is
cleared to 0, instructions are executed in sequence.

These bits are always read as 1.

R/W

These bits designate the interrupt mask level (0 to 7).
For details, refer to section 5, Interrupt Controller.

R/W

R/W

Section 2 CPU

2.4.4 Condition-Code Register (CCR)

This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.

Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.

Initial

Bit Bit Name

7 I 1 R/W Interrupt Mask Bit

6 UI Undefined R/W User Bit or Interrupt Mask Bit

5 H Undefined R/W Half-Carry Flag

4 U Undefined R/W User Bit

3 N Undefined R/W Negative Flag

2 Z Undefined R/W Zero Flag

Value

R/W Description

Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set to
1 at the start of an exception-handling sequence. For
details, refer to section 5, Interrupt Controller.

Can be read or written by software using the LDC, STC,
ANDC, ORC, and XORC instructions. This bit cannot be
used as an interrupt mask bit in this LSI.

When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B,
or NEG.B instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or
NEG.W instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 11, and cleared to 0
otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 27, and cleared to 0 otherwise.

Can be read or written by software using the LDC, STC,
ANDC, ORC, and XORC instructions.

Stores the value of the most significant bit of data as a
sign bit.

Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.

Rev. 1.00 Mar. 12, 2008 Page 34 of 1178

REJ09B0403-0100

Section 2 CPU

Initial

Bit Bit Name

1 V Undefined R/W Overflow Flag

0 C Undefined R/W Carry Flag

Value

R/W Description

Set to 1 when an arithmetic overflow occurs, and
cleared to 0 at other times.

Set to 1 when a carry occurs, and cleared to 0
otherwise. Used by:

• Add instructions, to indicate a carry

• Subtract instructions, to indicate a borrow

• Shift and rotate instructions, to indicate a carry

The carry flag is also used as a bit accumulator by bit
manipulation instructions.

2.4.5 Multiply-Accumulate Register (MAC)

This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32­bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are
a sign extension.

2.4.6 Initial Values of CPU Registers

Reset exception handling loads the CPU’s program counter (PC) from the vector table, clears the
trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits
and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized.
The stack pointer should therefore be initialized by an MOV.L instruction executed immediately
after a reset.

Rev. 1.00 Mar. 12, 2008 Page 35 of 1178

REJ09B0403-0100

Section 2 CPU

2.5 Data Formats

The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.

2.5.1 General Register Data Formats

Figure 2.9 shows the data formats in general registers.

Data Type Register Number Data Format

70

Don't care

6543271

0

1-bit data

RnH

1-bit data

4-bit BCD data

4-bit BCD data

Byte data

Byte data

RnL

RnH

RnL

RnH

RnL

Don't care

7 04 3

Upper Lower

Don't care

7 0

MSB LSB

Don't care

7

65432710

Don't care

704 3

Upper Lower

7

MSB LSB

Figure 2.9 General Register Data Formats (1)

0

Don't care

0

Rev. 1.00 Mar. 12, 2008 Page 36 of 1178

REJ09B0403-0100

Data Type Data FormatRegister Number

Section 2 CPU

Word data

Word data

15 0

MSB LSB

Longword data

31 16

MSB

Rn

En

ERn

En Rn

[Legend]

ERn:

En:

Rn:

RnH:

RnL:

MSB:

LSB:

General register ER

General register E

General register R

General register RH

General register RL

Most significant bit

Least significant bit

Figure 2.9 General Register Data Formats (2)

15 0

MSB LSB

15 0

LSB

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Section 2 CPU

2.5.2 Memory Data Formats

Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and
longword data in memory, however word or longword data must begin at an even address. If an
attempt is made to access word or longword data at an odd address, an address error does not
occur, however the least significant bit of the address is regarded as 0, so access begins the
preceding address. This also applies to instruction fetches.

When ER7 is used as an address register to access the stack, the operand size should be word or
longword.

Data Type Address

70

1-bit data

Byte data

Word data

Longword data Address 2N

Address L

Address L

Address 2M

Address 2M+1

Address 2N+1

Address 2N+2

Address 2N+3

76 543210

MSB

MSB

MSB

Figure 2.10 Memory Data Formats

Data Format

LSB

LSB

LSB

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Section 2 CPU

2.6 Instruction Set

The H8S/2600 CPU has 69 instructions. The instructions are classified by function in table 2.1.

Table 2.1 Instruction Classification

Function Instructions Size Types

Data transfer MOV B/W/L 5

POP*1, PUSH*1 W/L

LDM, STM L

MOVFPE*3, MOVTPE*3 B

ADD, SUB, CMP, NEG B/W/L 23 Arithmetic

operation

INC, DEC B/W/L

ADDS, SUBS L

MULXU, DIVXU, MULXS, DIVXS B/W

EXTU, EXTS W/L

TAS*4 B

MAC, LDMAC, STMAC, CLRMAC 

Logic operations AND, OR, XOR, NOT B/W/L 4

Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR B/W/L 8

Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,

Branch Bcc*2, JMP, BSR, JSR, RTS  5

System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP  9

Block data transfer EEPMOV  1

Notes: B-byte; W-word; L-longword.

1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+,Rn and MOV.W Rn,@-SP.
POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+,ERn and
MOV.L ERn,@-SP.

2. Bcc is the general name for conditional branch instructions.

3. Cannot be used in this LSI.

4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

ADDX, SUBX, DAA, DAS B

B 14

BIAND, BOR, BIOR, BXOR, BIXOR

Total: 69

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Section 2 CPU

2.6.1 Table of Instructions Classif ied by Function

Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in
tables 2.3 to 2.10 is defined below.

Table 2.2 Operation Notation

Symbol Description

Rd General register (destination)*

Rs General register (source)*

Rn General register*

ERn General register (32-bit register)

MAC Multiply-accumulate register (32-bit register)

(EAd) Destination operand

(EAs) Source operand

EXR Extended control register

CCR Condition-code register

N N (negative) flag in CCR

Z Z (zero) flag in CCR

V V (overflow) flag in CCR

C C (carry) flag in CCR

PC Program counter

SP Stack pointer

#IMM Immediate data

disp Displacement

+ Addition

– Subtraction

× Multiplication

÷ Division

∧ Logical AND

∨ Logical OR

⊕ Logical XOR

→ Move

∼ NOT (logical complement)

:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length

Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0

to R7, E0 to E7), and 32-bit registers (ER0 to ER7).

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Table 2.3 Data Transfer Instructions

Instruction Size* Function

MOV B/W/L (EAs) → Rd, Rs → (EAd)

Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.

MOVFPE B Cannot be used in this LSI.

MOVTPE B Cannot be used in this LSI.

POP W/L @SP+ → Rn

Pops a general register from the stack. POP.W Rn is identical to
MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.

PUSH W/L Rn → @–SP

Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP.

LDM L @SP+ → Rn (register list)

Pops two or more general registers from the stack.

STM L Rn (register list) → @–SP

Pushes two or more general registers onto the stack.

Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword

Section 2 CPU

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Section 2 CPU

Table 2.4 Arithmetic Operations Instructions (1)

Instruction Size* Function

ADD
SUB

ADDX
SUBX

INC
DEC

ADDS
SUBS

DAA
DAS

MULXU B/W Rd × Rs → Rd

MULXS B/W Rd × Rs → Rd

DIVXU B/W Rd ÷ Rs → Rd

Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword

B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd

Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register (immediate byte data
cannot be subtracted from byte data in a general register. Use the SUBX
or ADD instruction.)

B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd

Performs addition or subtraction with carry on byte data in two general
registers, or on immediate data and data in a general register.

B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd

Increments or decrements a general register by 1 or 2. (Byte operands
can be incremented or decremented by 1 only.)

L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd

Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.

B Rd decimal adjust → Rd

Decimal-adjusts an addition or subtraction result in a general register by
referring to the CCR to produce 4-bit BCD data.

Performs unsigned multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

Performs signed multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

Performs unsigned division on data in two general registers: either 16
bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.

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Section 2 CPU

Table 2.4 Arithmetic Operations Instructions (2)

Instruction Size*1 Function

DIVXS B/W Rd ÷ Rs → Rd

Performs signed division on data in two general registers: either 16 bits
÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.

CMP B/W/L Rd – Rs, Rd – #IMM

Compares data in a general register with data in another general
register or with immediate data, and sets CCR bits according to the
result.

NEG B/W/L 0 – Rd → Rd

Takes the two’s complement (arithmetic complement) of data in a
general register.

EXTU W/L Rd (zero extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by padding with zeros on the
left.

EXTS W/L Rd (sign extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by extending the sign bit.

TAS*2 B @ERd – 0, 1 → (<bit 7> of @ERd)

Tests memory contents, and sets the most significant bit (bit 7) to 1.

MAC  (EAs) × (EAd) + MAC → MAC

Performs signed multiplication on memory contents and adds the result
to the multiply-accumulate register. The following operations can be
performed:
16 bits × 16 bits + 32 bits → 32 bits, saturating
16 bits × 16 bits + 42 bits → 42 bits, non-saturating

CLRMAC  0 → MAC

Clears the multiply-accumulate register to zero.

LDMAC
STMAC

Note: 1. Refers to the operand size.
B: Byte
W: Word
L: Longword

2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

L Rs → MAC, MAC → Rd

Transfers data between a general register and a multiply-accumulate
register.

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Section 2 CPU

Table 2.5 Logic Operations Instructions

Instruction Size* Function

AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd

Performs a logical AND operation on a general register and another
general register or immediate data.

OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd

Performs a logical OR operation on a general register and another
general register or immediate data.

XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logical exclusive OR operation on a general register and
another general register or immediate data.

NOT B/W/L ∼(Rd) → (Rd)

Takes the one’s complement (logical complement) of general register
contents.

Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword

Table 2.6 Shift Instructions

Instruction Size* Function

SHAL
SHAR

B/W/L Rd (shift) → Rd

Performs an arithmetic shift on general register contents.
1-bit or 2-bit shifts are possible.

SHLL
SHLR

B/W/L Rd (shift) → Rd

Performs a logical shift on general register contents.
1-bit or 2-bit shifts are possible.

ROTL
ROTR

B/W/L Rd (rotate) → Rd

Rotates general register contents.
1-bit or 2-bit rotations are possible.

ROTXL
ROTXR

B/W/L Rd (rotate) → Rd

Rotates general register contents through the carry flag.
1-bit or 2-bit rotations are possible.

Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword

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Table 2.7 Bit Manipulation Instructions (1)

Instruction Size* Function

BSET B 1 → (<bit-No.> of <EAd>)

Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.

BCLR B 0 → (<bit-No.> of <EAd>)

Clears a specified bit in a general register or memory operand to 0. The
bit number is specified by 3-bit immediate data or the lower three bits of
a general register.

BNOT B ∼(<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)

Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.

BTST B ∼(<bit-No.> of <EAd>) → Z

Tests a specified bit in a general register or memory operand and sets
or clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.

BAND

BIAND

BOR

BIOR

Note: * Refers to the operand size.
B: Byte

B

B

B

B

C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.

∼(<bit-No.> of <EAd>)] → C

C ∧ [
ANDs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.

C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.

C ∨ [

∼(<bit-No.> of <EAd>)] → C

ORs the carry flag with the inverse of a specified bit in a general register
or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.

Section 2 CPU

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Section 2 CPU

Table 2.7 Bit Manipulation Instructions (2)

Instruction Size*1 Function

BXOR

BIXOR

BLD

BILD

BST

BIST

Note: * Refers to the operand size.
B: Byte

B

B

B

B

B

B

C ⊕ (<bit-No.> of <EAd>) → C
XORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.

∼(<bit-No.> of <EAd>)] → C

C ⊕ [
XORs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.

(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to the
carry flag.

∼(<bit-No.> of <EAd>) → C

Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.

C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.

∼C → (<bit-No.> of <EAd>)

Transfers the inverse of the carry flag value to a specified bit in a
general register or memory operand.
The bit number is specified by 3-bit immediate data.

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Section 2 CPU

Table 2.8 Branch Instructions

Instruction Size Function

Bcc  Branches to a specified address if a specified condition is true. The

branching conditions are listed below.

Mnemonic Description Condition

BRA(BT) Always (true) Always

BRN(BF) Never (false) Never

BHI High C ∨ Z = 0

BLS Low or same C ∨ Z = 1

BCC(BHS) Carry clear

(high or same)

BCS(BLO) Carry set (low) C = 1

BNE Not equal Z = 0

BEQ Equal Z = 1

BVC Overflow clear V = 0

BVS Overflow set V = 1

BPL Plus N = 0

BMI Minus N = 1

BGE Greater or equal N ⊕ V = 0

BLT Less than N ⊕ V = 1

BGT Greater than Z∨(N ⊕ V) = 0

BLE Less or equal Z∨(N ⊕ V) = 1

JMP  Branches unconditionally to a specified address.

BSR  Branches to a subroutine at a specified address.

JSR  Branches to a subroutine at a specified address.

RTS  Returns from a subroutine

C = 0

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Section 2 CPU

Table 2.9 System Control Instructions

Instruction Size* Function

TRAPA  Starts trap-instruction exception handling.

RTE  Returns from an exception-handling routine.

SLEEP  Causes a transition to a power-down state.

LDC B/W (EAs) → CCR, (EAs) → EXR

Moves general register or memory contents or immediate data to CCR
or EXR. Although CCR and EXR are 8-bit registers, word-size transfers
are performed between them and memory. The upper 8 bits are valid.

STC B/W CCR → (EAd), EXR → (EAd)

Transfers CCR or EXR contents to a general register or memory.
Although CCR and EXR are 8-bit registers, word-size transfers are
performed between them and memory. The upper 8 bits are valid.

ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR

Logically ANDs the CCR or EXR contents with immediate data.

ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR

Logically ORs the CCR or EXR contents with immediate data.

XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR

Logically XORs the CCR or EXR contents with immediate data.

NOP  PC + 2 → PC

Only increments the program counter.

Note: * Refers to the operand size.
B: Byte
W: Word

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Table 2.10 Block Data Transfer Instructions

Instruction Size Function

EEPMOV.B

EEPMOV.W





if R4L ≠ 0 then
Repeat @ER5+ → @ER6+
R4L–1 → R4L
Until R4L = 0
else next;

if R4 ≠ 0 then
Repeat @ER5+ → @ER6+
R4–1 → R4
Until R4 = 0
else next;

Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location set
in ER6.

Execution of the next instruction begins as soon as the transfer is
completed.

Section 2 CPU

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Section 2 CPU

2.6.2 Basic Instruction Formats

The H8S/2600 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op field), a register field (r field), an effective address extension (EA field), and a
condition field (cc).

Figure 2.11 shows examples of instruction formats.

• Operation Field

Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.

• Register Field

Specifies a general register. Address registers are specified by 3 bits, and data registers by 3
bits or 4 bits. Some instructions have two register fields. Some have no register field.

• Effective Address Extension

8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.

• Condition Field

Specifies the branching condition of Bcc instructions.

(1) Operation field only

op

(2) Operation field and register fields

op

(3) Operation field, register fields, and effective address extension

op

EA(disp)

(4) Operation field, effective address extension, and condition field

op cc EA(disp) BRA d:16, etc.

rn

rn rm

rm

Figure 2.11 Instruction Formats (Examples)

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NOP, RTS, etc.

ADD.B Rn, Rm, etc.

MOV.B @(d:16, Rn), Rm, etc.

Section 2 CPU

2.7 Addressing Modes and Effective Address Calculation

The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes. Arithmetic and logic instructions can use the register direct
and immediate modes. Data transfer instructions can use all addressing modes except program­counter relative and memory indirect. Bit manipulation instructions use register direct, register
indirect, or the absolute addressing mode to specify an operand, and register direct (BSET, BCLR,
BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in
the operand.

Table 2.11 Addressing Modes

No. Addressing Mode Symbol

1 Register direct Rn

2 Register indirect @ERn

3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn)

4 Register indirect with post-increment

Register indirect with pre-decrement

5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32

6 Immediate #xx:8/#xx:16/#xx:32

7 Program-counter relative @(d:8,PC)/@(d:16,PC)

8 Memory indirect @@aa:8

@ERn+
@–ERn

2.7.1 Register DirectRn

The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the
operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7
can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.

2.7.2 Register Indirect@ERn

The register field of the instruction code specifies an address register (ERn) which contains the
address of the operand on memory. If the address is a program instruction address, the lower 24
bits are valid and the upper 8 bits are all assumed to be 0 (H'00).

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2.7.3 Register Indirect with Displacement@(d:16, ERn) or @(d:32, ERn)

A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn)
specified by the register field of the instruction, and the sum gives the address of a memory
operand. A 16-bit displacement is sign-extended when added.

2.7.4 Register Indirect with Post-Increment or Pre-Decrement@ERn+ or @-ERn

Register indirect with post-increment@ERn+: The register field of the instruction code

specifies an address register (ERn) which contains the address of a memory operand. After the
operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the
address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for
longword transfer instruction. For the word or longword transfer instructions, the register value

should be even.

Register indirect with pre-decrement@-ERn: The value 1, 2, or 4 is subtracted from an

address register (ERn) specified by the register field in the instruction code, and the result is the
address of a memory operand. The result is also stored in the address register. The value
subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer
instruction. For the word or longword transfer instructions, the register value should be even.

2.7.5 Absolute Address@aa:8, @aa:16, @aa:24, or @aa:32

The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long
(@aa:32). Table 2.12 indicates the accessible absolute address ranges.

To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF).
For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can
access the entire address space.

A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8

bits are all assumed to be 0 (H'00).

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