Realtek Semiconductor RTL8197D 11AC User Manual
RTL8197D-11AC
AP/Router User’s Manual
Rev. 1.0
04 Dec 2012
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
RTL8197D-11AC
AP/Router User's Manual
COPYRIGHT
©2012 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document provides detailed user guidelines to achieve the best performance when implementing the
Realtek 11n AP/Routers.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
ii
Rev.1.0
RTL8197D-11AC
AP/Router User's Manual
Table of Contents
1. GENERAL D ESCR I PTIO N................................................................................................................................................0
2. FEATURES....................................................................................................................... ....................................................2
3. SYSTEM APPLICA TIONS.................................................................................................................................................4
4. PRODUCT SPECIFICATIONS..........................................................................................................................................5
4.1. ENVIRONMENTAL.........................................................................................................................................................5
4.1.1. Operating................................................................................................................................................................5
4.1.2. Storage....................................................................................................................................................................5
4.2. FUNCTIONAL SPECIFICATIONS......................................................................................................................................5
4.3. WARNING.....................................................................................................................................................................7
4.3.1 Federal Communication Commission Interference Statement.......................................................................................7
4.3.2 Industry Canada Statement.........................................................................................................................................8
4.3.3 NCC
警語
.................................................................................................................................................................12
List of Tables
TABLE 1. FUNCTIONAL SPECIFICATIONS ....................................................................................................................................5
List of Figures
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Rev.1.0
RTL8197D-11AC
AP/Router User's Manual
1. General Description
The RTL8197D is an integrated System-on-a-Chip (SoC) Application Specific Integrated Circuit (ASIC)
L2 5-Port Ethernet switch. An RLX5281 CPU is embedded and the clock rate can be up to 660MHz. To
improve computational performance, a 64Kbyte I-Cache, 32Kbyte D-Cache, 16Kbyte I-MEM, and
8Kbyte D-MEM are provided. A standard 5-signal P1149.1 compliant EJTAG test interface is supported
for CPU testing and software development.
The RTL8197D provides five ports (ports 0~4), integrated with five physical layer transceivers for
10Base-T and 100Base-TX. Each port of the RTL8197D may be configured as a LAN or WAN port. Port
0 supports an external MAC interface that could be an GMII/RGMII/MII interface type to work with an
external MAC or PHY transceiver.
The RTL8197D supports flexible IEEE 802.3x full-duplex flow control and optional half-duplex
backpressure control. For full-duplex, standard IEEE 803.3x flow control will enable pause ability only
when both sides of UTP have auto-negotiation ability and have enabled pause ability. The RTL8197D
also provides optional forced mode IEEE 802.3x full-duplex flow control. Based on optimized packet
memory management, the RTL8197D is capable of Head-Of-Line blocking prevention.
L2 Switch Features: The RTL8197D contains a 1024-entry address look-up table with a 10-bit 4-way
XOR hashing algorithm for address searching and learning. Auto-aging of each entry is provided and the
aging time is around 300~450 seconds.
The RTL8197D supports IEEE 802.3az, also known as Energy Efficient Ethernet (EEE). IEEE 802.3az
operates with the IEEE 802.3 Media Access Control (MAC) Sublayer to support operation in Low Power
Idle mode. When the Ethernet network is in low link utilization, EEE allows systems on both sides of the
link to save power. Green Ethernet power saving provides: link-on and dynamic detection of cable length,
and dynamic adjustment of power required for the detected cable length. This feature provides high
performance with minimum power consumption. The RTL8197D also implements link-down power
saving on a per-port basis, greatly cutting power consumption when the network cable is disconnected.
For peripheral interfaces, two 16550-compatible UARTs are supported, and a 16-byte FIFO buffer is
provided. Both USB 2.0 host and USB OTG (On-The-Go) controllers are embedded in the RTL8197D to
provide EHCI and OHCI 1.1 compliant host and OTG functionality. In addition, two USB PHYs are
embedded in the RTL8197D.
An MDI/MDIX auto crossover function is supported. For accessing high-speed devices, the RTL8197D
provides two PCI Express hosts to access a PCI Express interface. Up to two PCI Express devices are
supported via this interface on the RTL8197D.
The RTL8197D requires only a single 25MHz crystal or 40MHz clock input for the system PLL. The
RTL8197D also has two hardware timers and one watchdog timer to provide accurate timing and
watchdog functionality. For extension and flexibility, the RTL8197D supports up to 46 GPIO pins.
5-Port 10/100M Ethernet Router Network Processor 0 Track ID: JATR-3375-16 Rev. 1.1
RTL8197D-11AC
AP/Router User's Manual
The RTL8197D is provided in a Thermally Enhanced Thin Profile Plastic Quad Flat Package, 176-Lead
(TQFP176 E-PAD) package. It requires a 3.3V and 1.0V external power supply.
5-Port 10/100M Ethernet Router Network Processor 1 Track ID: JATR-3375-16 Rev. 1.1
2. Features
RTL8197D-11AC
AP/Router User's Manual
SOC
Embedded RISC CPU, RLX5281 with
64Kbyte I-Cache, 32Kbyte D-Cache,
16Kbyte I-MEM, 8Kbyte D-MEM
Supports MIPS-1 ISA, MIPS16 ISA
Clock Rate: 500MHz~660MHz
Provides a standard 5-signal P1149.1
EJTAG test port
Supports RLX5281 CPU suspend mode
L2 Capabilities
Five Ethernet MAC switch with five
IEEE 802.3 10/100M physical layer
transceivers
Supports one GMII/RGMII/MII port to
connect to an external MAC or PHY
(supports both PHY mode and MAC
mode) for HomePlug or HomePNA
applications on RTL8197D
Non-blocking wire-speed reception and
transmission and
non-head-of-line-blocking/forwarding
Internal 256Kbit SRAM for packet
buffering
The NIC DMA supports
multiple-descriptor-ring architecture for
QoS applications
Peripheral Interfaces
Supports PCI Express Host with
integrated PHY to connect up to two
master devices
Two PCI Express PHY embedded
Supports two-port USB
One is USB 2.0 host
One is USB 2.0 Host or Device
Two USB PHYs are embedded
Supports one I2S interface
Supports two 16550 UARTs
Supports up to 46 GPIO pins
Memory Interfaces
Serial Flash (SPI Type)
Supports two banks and dual I/O
channels for SPI Flash application
Each Flash bank could be configured
as 256K/512K/1M/2M/4M/8M/16M
Bytes
Boot up from SPI flash is supported
Internal 1024 entry 4-way hash L2
look-up table
Supports source and destination MAC
address filtering
Bi-color LED display mode
CPU Interface (NIC)
NAND Flash
System supports up to 4 Gigabyte
Flash memory space
SDR DRAM
Supports two SDR DRAM banks;
each can be configured as
2M/4M/8M/16M/32M/64Mbyte
16-bit SDR DRAM data bus
Supports BSD mbuf-like packet structure
with adjustable cluster size (128-byte to
2Kbyte) to provide optimum memory
supported. System totally supports up
to 128Mbyte SDR DRAM memory
space
utilization
5-Port 10/100M Ethernet Router Network Processor 2 Track ID: JATR-3375-16 Rev. 1.1
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