RTL8187L
802.11b/g RTL8187 miniCard
Rev. 1.2
06 September 2005
Track ID: JATR-1076-21
RTL8187L
COPYRIGHT
©2005 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are
trademarks/registered trademarks of their respective owners.
Datasheet
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision Release Date
1.0 2004/10/22 First release.
1.1 2005/04/25 Revised data transaction content.
1.2 2005/09/06 Added RoHS declaration (see last 2 pages).
Summary
Added offset 8 information (Table 27, page 23, and Table 28, page 23).
Added lead (Pb)-free and package identification information on page 4.
Corrected section 14 Mechanical Dimensions, page 34.
Wireless LAN Network Interface Controller ii Track ID: JATR-1076-21 Rev. 1.2
RTL8187L
Datasheet
Table of Contents
1. GENERAL DESCRIPTION ...............................................................................................................................................1
2. FEATURES ..........................................................................................................................................................................2
3. SYSTEM APPLICATIONS ................................................................................................................................................3
4. BLOCK DIAGRAM ............................................................................................................................................................3
5. PIN ASSIGNMENTS...........................................................................................................................................................4
5.1. LEAD (PB)-FREE PACKAGE IDENTIFICATION ...................................................................................................................4
6. PIN DESCRIPTIONS ..........................................................................................................................................................5
6.1. USB TRANSCEIVER INTERFACE ......................................................................................................................................5
6.2. EEPROM INTERFACE .....................................................................................................................................................5
6.3. POWER PINS ....................................................................................................................................................................5
6.4. LED INTERFACE..............................................................................................................................................................6
6.5. ATTACHMENT UNIT INTERFACE ......................................................................................................................................6
6.5.1. RTL8225 RF Chipset..............................................................................................................................................6
6.5.2. RTL8255 RF Chipset..............................................................................................................................................7
6.6. CLOCK AND OTHER PINS.................................................................................................................................................8
7. CPU ACCESS TO ENDPOINT DATA..............................................................................................................................9
7.1. CONTROL TRANSFER.......................................................................................................................................................9
7.2. BULK TRANSFER .............................................................................................................................................................9
8. USB REQUEST..................................................................................................................................................................10
8.1. GET DESCRIPTOR-DEVICE.............................................................................................................................................10
8.2. GET DESCRIPTOR-DEVICE QUALIFIER (HIGH SPEED)....................................................................................................10
8.3. GET DESCRIPTOR-CONFIGURATION ..............................................................................................................................11
8.4. GET DESCRIPTOR-STRING INDEX 0 ...............................................................................................................................11
8.5. GET DESCRIPTOR-STRING INDEX 1 ...............................................................................................................................12
8.6. GET DESCRIPTOR-STRING INDEX 2 ...............................................................................................................................12
8.7. GET DESCRIPTOR-STRING INDEX 3 ...............................................................................................................................13
8.8. GET DESCRIPTOR-STRING INDEX 4 ...............................................................................................................................13
8.9. GET DESCRIPTOR-STRING INDEX 5 ...............................................................................................................................14
8.10. GET DESCRIPTOR-OTHER SPEED CONFIGURATION....................................................................................................14
8.11. SET ADDRESS ............................................................................................................................................................15
8.12. SET INTERFACE 0 ......................................................................................................................................................15
8.13. SET FEATURE DEVICE ...............................................................................................................................................15
8.14. CLEAR FEATURE DEVICE ..........................................................................................................................................16
8.15. SET CONFIG 0............................................................................................................................................................16
8.16. SET CONFIG 1............................................................................................................................................................16
9. EEPROM (93C46 OR 93C56) CONTENTS ....................................................................................................................17
9.1. EEPROM REGISTERS SUMMARY..................................................................................................................................20
9.2. EEPROM POWER MANAGEMENT REGISTERS SUMMARY .............................................................................................20
10. USB PACKET BUFFERING ........................................................................................................................................21
10.1. TRANSMIT BUFFER MANAGER ..................................................................................................................................21
10.2. RECEIVE BUFFER MANAGER .....................................................................................................................................21
Wireless LAN Network Interface Controller iii Track ID: JATR-1076-21 Rev. 1.2
RTL8187L
10.3. PACKET RECOGNITION ..............................................................................................................................................21
11. FUNCTIONAL DESCRIPTION ..................................................................................................................................22
11.1. TRANSMIT & RECEIVE OPERATIONS..........................................................................................................................22
11.1.1. Transmit ...............................................................................................................................................................22
11.1.2. Receive .................................................................................................................................................................25
11.2. LOOPBACK OPERATION .............................................................................................................................................27
11.3. TX ENCAPSULATION (WITH RTL8187L INTERNAL BASEBAND PROCESSOR)............................................................27
11.4. RX DECAPSULATION (WITH RTL8187L INTERNAL BASEBAND PROCESSOR) ...........................................................27
11.5. LED FUNCTIONS .......................................................................................................................................................28
11.5.1. Link Monitor.........................................................................................................................................................28
11.5.2. Infrastructure Monitor .........................................................................................................................................28
11.5.3. Rx LED .................................................................................................................................................................28
11.5.4. Tx LED .................................................................................................................................................................29
11.5.5. Tx/Rx LED ............................................................................................................................................................29
11.5.6. LINK/ACT LED ....................................................................................................................................................30
12. APPLICATION DIAGRAM .........................................................................................................................................31
13. ELECTRICAL CHARACTERISTICS........................................................................................................................32
13.1. TEMPERATURE LIMIT RATINGS .................................................................................................................................32
13.2. DC CHARACTERISTICS ..............................................................................................................................................32
13.3. AC CHARACTERISTICS ..............................................................................................................................................33
13.3.1. Serial EEPROM Interface Timing (93C46(64*16)/93C56(128*16))...................................................................33
Datasheet
14. MECHANICAL DIMENSIONS ...................................................................................................................................34
14.1. MECHANICAL DIMENSIONS NOTES............................................................................................................................35
15. ORDERING INFORMATION .....................................................................................................................................36
List of Tables
TABLE 1. USB TRANSCEIVER INTERFACE .....................................................................................................................................5
TABLE 2. EEPROM INTERFACE ....................................................................................................................................................5
TABLE 3. POWER PINS ...................................................................................................................................................................5
TABLE 4. LED INTERFACE.............................................................................................................................................................6
TABLE 5. ATTACHMENT UNIT INTERFACE .....................................................................................................................................6
TABLE 6. RTL8255 RF CHIPSET....................................................................................................................................................7
TABLE 7. CLOCK AND OTHER PINS ................................................................................................................................................8
TABLE 8. GET DESCRIPTOR-DEVICE............................................................................................................................................10
TABLE 9. GET DESCRIPTOR- DEVICE QUALIFIER (HIGH SPEED) ..................................................................................................10
TABLE 10. GET DESCRIPTOR-CONFIGURATION .............................................................................................................................11
TABLE 11. GET DESCRIPTOR-STRING INDEX 0 ..............................................................................................................................11
TABLE 12. GET DESCRIPTOR-STRING INDEX 1 ..............................................................................................................................12
TABLE 13. GET DESCRIPTOR-STRING INDEX 2 ..............................................................................................................................12
TABLE 14. GET DESCRIPTOR-STRING INDEX 3 ..............................................................................................................................13
TABLE 15. GET DESCRIPTOR-STRING INDEX 4 ..............................................................................................................................13
TABLE 16. GET DESCRIPTOR-STRING INDEX 5 ..............................................................................................................................14
TABLE 17. GET DESCRIPTOR-OTHER SPEED CONFIGURATION ......................................................................................................14
TABLE 18. SET ADDRESS ..............................................................................................................................................................15
TABLE 19. SET INTERFACE 0 .........................................................................................................................................................15
Wireless LAN Network Interface Controller iv Track ID: JATR-1076-21 Rev. 1.2
RTL8187L
TABLE 20. SET FEATURE DEVICE..................................................................................................................................................15
TABLE 21. CLEAR FEATURE DEVICE .............................................................................................................................................16
TABLE 22. SET CONFIG 0 ..............................................................................................................................................................16
TABLE 23. SET CONFIG 1 ..............................................................................................................................................................16
TABLE 24. EEPROM (93C46 OR 93C56) CONTENTS....................................................................................................................17
TABLE 25. EEPROM REGISTERS SUMMARY ................................................................................................................................20
TABLE 26. EEPROM POWER MANAGEMENT REGISTERS SUMMARY............................................................................................20
TABLE 27. TX DESCRIPTOR FORMAT ............................................................................................................................................22
TABLE 28. TX STATUS DESCRIPTOR..............................................................................................................................................23
TABLE 29. RX DESCRIPTOR FORMAT ............................................................................................................................................25
TABLE 30. RX STATUS DESCRIPTOR..............................................................................................................................................25
TABLE 31. TEMPERATURE LIMIT RATINGS....................................................................................................................................32
TABLE 32. DC CHARACTERISTICS.................................................................................................................................................32
TABLE 33. EEPROM ACCESS TIMING PARAMETERS ....................................................................................................................33
TABLE 34. ORDERING INFORMATION ............................................................................................................................................36
Datasheet
List of Figures
FIGURE 1. BLOCK DIAGRAM..........................................................................................................................................................3
FIGURE 2. PIN ASSIGNMENTS.........................................................................................................................................................4
FIGURE 3. RX LED ......................................................................................................................................................................28
FIGURE 4. TX LED ......................................................................................................................................................................29
FIGURE 5. TX/RX LED ................................................................................................................................................................29
FIGURE 6. LINK/ACT LED.........................................................................................................................................................30
FIGURE 7. APPLICATION DIAGRAM..............................................................................................................................................31
FIGURE 8. SERIAL EEPROM INTERFACE TIMING ........................................................................................................................33
Wireless LAN Network Interface Controller v Track ID: JATR-1076-21 Rev. 1.2
RTL8187L
Datasheet
1. General Description
The Realtek RTL8187L is a low-profile highly integrated cost-effective Wireless LAN USB 2.0 network
interface controller that integrates a USB 2.0 PHY, SIE (Serial Interface Engine), 8051 MCU, a Wireless
LAN MAC, and a Direct Sequence Spread Spectrum/OFDM baseband processor onto one chip. It provides
USB high speed (480Mbps), and full speed (12Mbps), and supports 4 endpoints for transfer pipes. To
reduce protocol overhead, the RTL8187L supports Short InterFrame Space (SIFS) burst mode to send
packets back-to-back. A protection mechanism prevents collisions among 802.11b nodes. The RTL8187L
fully complies with IEEE 802.11a/b/g specifications.
Direct Sequence Spread Spectrum (DSSS), Complementary Code Keying (CCK), and Orthogonal
Frequency Division Multiplexing (OFDM) baseband processing are implemented to support all IEEE
802.11a, 802.11b, and 802.11g data rates. Differential phase shift keying modulation schemes, DBPSK and
DQPSK with data scrambling capability, are available, along with complementary code keying to provide
data rates of 1, 2, 5.5, and 11Mbps, with long or short preamble. A high-speed Fast Fourier Transform
(FFT)/Inverse Fast Fourier Transform (IFFT), combined with BPSK, QPSK, 16QAM and 64QAM
modulation of the individual sub-carriers, provides data rates of 6, 9, 12, 18, 24, 36, 48 and 54Mbps, with
rate-compatible punctured convolutional coding with a coding rate of 1/2, 2/3, and 3/4.
An enhanced signal detector, an adaptive frequency domain equalizer, and a soft-decision Viterbi decoder
are built-in to alleviate severe multipath effects. Efficient IQ-imbalance calibration, DC offset, phase noise,
frequency offset, and timing offset compensation reduce radio frequency front-end impairments. Selectable
digital transmit and receiver FIR filters are provided to meet the requirements of transmit spectrum masks,
and to reject adjacent channel interference, respectively. Both in the transmitter and receiver,
programmable scaling in the digital domain trades the quantization noise against the increased probability
of clipping. Robust signal detection, symbol boundary detection, and channel estimation perform well at
the minimum sensitivity.
The RTL8187L supports fast receiver Automatic Gain Control (AGC) and antenna diversity functions, and
an adaptive transmit power control function to obtain better performance in the analog portions of the
transceiver. It also has on-chip digital-to-analog converters and analog-to-digital converters for analog I
and Q inputs and outputs, transmit TSSI and receiver RSSI inputs, and transmit and receiver AGC outputs.
The RTL8187L is highly integrated and requires no ‘glue’ logic or external memory. It keeps network
maintenance costs low and eliminates usage barriers.
Wireless LAN Network Interface Controller 1 Track ID JATR-1076-21 Rev. 1.2
2. Features
RTL8187L
Datasheet
128-Pin LQFP and 128-pin LQFP Lead
(Pb)-Free package
State machine implementation without
external memory (RAM, flash) requirement
Complies with IEEE 802.11a/b/g standards
Supports descriptor-based buffer
management
Integrated Wireless LAN MAC and Direct
Sequence Spread Spectrum/OFDM
Baseband Processor in one chip
Enhanced signal detector, adaptive frequency
domain equalizer, and soft-decision Viterbi
decoder to alleviate severe multipath effects
Processing Gain compliant with FCC
On-Chip A/D and D/A converters for I/Q
Data, AGC, and Adaptive Power Control
OFDM with BPSK, QPSK, 16QAM and
64QAM modulations and demodulations
supported with rate compatible punctured
convolutional coding with coding rate of 1/2,
2/3, and 3/4
Efficient IQ-imbalance calibration, DC
offset, phase noise, frequency offset and
timing offset compensation reduce analog
front-end impairments
Selectable digital transmit and receiver FIR
filters provided to meet transmit spectrum
mask requirements and to reject adjacent
channel interference
Programmable scaling both in transmitter
and receiver to trade quantization noise
against the increased probability of clipping
Fast receiver Automatic Gain Control (AGC)
& antenna diversity functions
Supports both transmit and receive Antenna
Diversity
Data rates of 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36,
48, and 54Mbps
Supports 40MHz OSC as the internal clock
source. The frequency deviation of the OSC
must be within 25 PPM on IEEE 802.11g and
20 PPM on IEEE 802.11a
IEEE 802.11g protection mechanisms for
both RTS/CTS and CTS-to-self
Burst-mode support for dramatically
enhanced throughput
DSSS with DBPSK and DQPSK, CCK
modulations and demodulations supported
with long and short preamble
Hardware-based IEEE 802.11i
encryption/decryption engine, including
64-bit/128-bit WEP, TKIP, and AES
Supports Wi-Fi alliance WPA and WPA2
security
Contains two large independent transmit and
receive FIFO buffers
Advanced power saving mode when the
LAN and wakeup function are not used
Uses 93C46 (64*16-bit EEPROM) or 93C56
(128*16-bit EEPROM) to store resource
configuration and ID parameter data
LED pins for various network activity
indications
Two GPIO pins supported
Wireless LAN Network Interface Controller 2 Track ID JATR-1076-21 Rev. 1.2
RTL8187L
Datasheet
Supports digital loopback capability on both
ports
Scatter and gather operation
Complies with USB Specification 2.0
Supports Full-speed (12Mbps) and
High-speed (480Mbps)
Embedded standard 8051 CPU with
enhanced features:
Four cycles per instruction
Variable clock speed cuts power
consumption
3. System Applications
Supports 4 endpoints:
64-Byte buffer for control endpoint
512-Byte buffer for bulk IN endpoint
Two 512-Byte buffers for bulk OUT
endpoint
3.3V and 1.8V power supplies required
5V tolerant I/Os
0.18µm CMOS process
USB Dongle WLAN adapter
Embedded WLAN solution in notebook, desktop, mobile phone, and motherboard
Wireless LAN Network Interface Controller 3 Track ID JATR-1076-21 Rev. 1.2
4. Block Diagram
RTL8187L
Datasheet
MAC
D+
D-
BBP, TX Section
MAC/BBP
Interface
SIE + Register
Scrambler
EEPROM
Interface
LED Driver
Power and TX/RX Timing Control Logic
WEP/
TKIP/
AES
Engine
Interrupt
Control
Logic
FIFO
Coding
Checksum
Logic
RTS, CTS,
ACK Frame
Generator
FIFO
Control
Logic
Digital
Filter
Serial
Control
Register
Frame Length
Transmit/
Receive
Logic
Interface
DAC
DAC
Frame Type
CCA/
NAV
Radio and
Synthesizer
Control
Discriminator
From BBP
MAC/BBP
Interface
TXI
TXQ
From
MAC
Register
TX State
Machine
TX AGC
Control
DAC
ADC
TXAGC
TXDET
BBP, RX Section
MAC/BBP
Interface
To MAC
From
MAC
Descrambler
Register
Clear Channel
Assessment/
Signal Quality
Decoding
RX AGC
Control
RX State
Machine
ADC
ADC
DAC
ADC
Antenna
Diversity
Control
Figure 1. Block Diagram
Wireless LAN Network Interface Controller 3 Track ID JATR-1076-21 Rev. 1.2
RXI
RXQ
RXAGC
RSSI
ANTSEL
ANTSELB
5. Pin Assignments
RTL8187L
Datasheet
Figure 2. Pin Assignments
5.1. Lead (Pb)-Free Package Identification
Lead (Pb)-free package is indicated by an ‘L’ in the location marked ‘T’ in Figure 2.
Wireless LAN Network Interface Controller 4 Track ID JATR-1076-21 Rev. 1.2
RTL8187L
Datasheet
6. Pin Descriptions
In order to reduce pin count, and therefore size and cost, some pins have multiple functions. In such cases,
the functions are separated with a ‘/’ symbol. Refer to the Pin Assignments diagram on page 4 for a
graphical representation.
The following signal type codes are used in the tables:
I: Input.
O: Output
S/T/S: Sustained Tri-State.
O/D: Open Drain.
T/S: Tri-State bi-directional input/output pin.
6.1. USB Transceiver Interface
Table 1. USB Transceiver Interface
Symbol Type Pin No Description
HSDP I/O 26 High speed USB D+ signal
HSDM I/O 24 High speed USB D- signal
FSDP I/O 27 Full speed USB D+ signal
FSDM I/O 25 Full speed USB D- signal
RUP N/A 28 External pull-up resistor (1.5kW) for D+ line.
RREF N/A 31 External Reference. Requires 1% precision 6.25K resistor to ground
6.2. EEPROM Interface
Table 2. EEPROM Interface
Symbol Type Pin No Description
EESK O 51 EESK in 93C46 (93C56) programming or auto-load mode.
EEDI O 39 EEDI in 93C46 (93C56) programming or auto-load mode.
EEDO I/O 36 EEDO in 93C46 (93C56) programming or auto-load mode.
EECS O 47 EEPROM Chip Select.
93C46 (93C56) chip select.
6.3. Power Pins
Table 3. Power Pins
Symbol Type Pin No Description
VDD33 P 40, 59, 78, 93, 111 +3.3V (Digital).
AVDD P 2, 9, 22, 29, 32, 127 +3.3V (Analog).
VDD P 44, 53, 72, 82, 90, 96,
105, 115
GND P 41, 45, 52, 60, 73, 80,
83, 91, 110
AGND P 3, 10, 21, 23, 30, 123,
126, 128
Wireless LAN Network Interface Controller 5 Track ID JATR-1076-21 Rev. 1.2
+1.8V.
Ground (Digital).
Ground (Analog).
RTL8187L
Datasheet
6.4. LED Interface
Table 4. LED Interface
Symbol Ty pe Pin No Description
LED0, 1 O 48, 56 LED Pins (Active low)
LED0 TX/RX TX/RX TX LINK/ACT
LED1 Infrastructure LINK RX Infrastructure
During power down mode, the LED signals are logic high.
LEDS1~0 00 01 10 11
6.5. Attachment Unit Interface
6.5.1. RTL8225 RF Chipset
Table 5. Attachment Unit Interface
Symbol Type Pin No Description
RIFSCK O 57 Serial Clock Output.
For the RTL8225 RF chipset, all operation mode switching and register setting is
done via a 4-wire serial interface.
RIFSD I/O 61 Serial Data Input/Output.
RFLE O 58 Serial Enable control.
CALEN O 77 Serial Read/Write control.
CALMODE O 108 Receiver Output.
I and Q channel AC coupling high-pass corner frequency selection. The output
function of this pin is not used in the RTL8225 RF chipset.
LNA_HL O 88 Not used in the RTL8225 RF chipset.
ANTSEL O 87 Antenna Select.
The antenna detects signal change states as the receiver switches from antenna to
antenna during the acquisition process in antenna diversity mode. This is a
complement for ANTSELB for differential drive of antenna switches.
ANTSELB O 95 Antenna Select B.
The antenna detects signal change states as the receiver switches from antenna to
antenna during the acquisition process in the antenna diversity mode. This is a
complement for ANTSEL for differential drive of antenna switches.
TRSW
TRSWB
VCOPDN O 49 Output Pin as shutdown mode select digital input.
A_PAPE O 85 2.4GHz Transmit Power Amplifier Power Enable.
B_PAPE O 107 Not used in the RTL8225 RF chipset.
RFTXEN O 102 Not used in the RTL8225 RF chipset.
RFRXEN O 113 Not used in the RTL8225 RF chipset.
GPIO0 O 67 General purpose input/output pin.
GPIO1 O 68 General purpose input/output pin.
GPIO2 O 69 General purpose input/output pin.
GPIO3 O 70 General purpose input/output pin.
O
O
104
103
Transmit/Receive path select.
The TRSW select signal controls the direction of the Transmit/Receive switch.
Wireless LAN Network Interface Controller 6 Track ID JATR-1076-21 Rev. 1.2
RTL8187L
Symbol Type Pin No Description
GPIO4 O 100 General purpose input/output pin.
GPIO5 O 94 General purpose input/output pin.
VREFO X 118 Not used in the RTL8225 RF chipset.
VRP X 119 Not used in the RTL8225 RF chipset.
VRN X 120 Not used in the RTL8225 RF chipset.
RXIP
RXIN
RXQP
RXQN
RXAGC I 4 Not used in the RTL8225 RF chipset.
TXAGC O 5 Not used in the RTL8225 RF chipset.
RSSI I 6 Analog Input to the Receive Power A/D Converter for Receive AGC Control.
TSSI0
TSSI1
TXQP
TXQN
TXIP
TXIN
TXQTP
TXQTN
TXITP
TXITN
I
I
I
I
I 7 Input to the Transmit Power A/D Converter for 2.4GHz Transmit AGC Control.
I 8 Not used in the RTL8225 RF chipset.
I
I
O
O
O
O
O
O
121
122
124
125
11
12
14
13
15
16
17
18
Receive (Rx) In-phase Analog Data.
Receive (Rx) Quadrature-phase Analog Data.
Not used in the RTL8225 RF chipset.
Not used in the RTL8225 RF chipset.
Transmit (TX) Quadrature-phase Analog Data.
Transmit (TX) In-phase Analog Data.
Datasheet
6.5.2. RTL8255 RF Chipset
Table 6. RTL8255 RF Chipset
Symbol Type Pin No Description
RIFSCK O 57 Serial Clock Output.
For the RTL8255 RF chipset, all operation mode switching and register setting is
done via a 3-wire serial interface.
RIFSD O 61 Serial Data Input/Output.
RFLE O 58 Serial Enable control.
CALEN X 77 Not used in the RTL8255 RF chipset.
CALMODE O 108 Receiver Output.
I and Q channel AC coupling high-pass corner frequency selection. The output
function of this pin is not used in the RTL8255 RF chipset.
LNAHL O 88 Not used in the RTL8255 RF chipset.
ANTSEL
ANTSELB
TRSW
TRSWB
VCOPDN O 49 Not used in the RTL8255 RF chipset.
APAPE O 85 2.4GHz Transmit Power Amplifier Power Enable.
BPAPE O 107 5GHz Transmit Power Amplifier Power Enable.
O
O
O
O
87
95
104
103
Antenna Select.
The antenna detects signal change states as the receiver switches from antenna to
antenna during the acquisition process in antenna diversity mode.
Transmit/Receive path select.
The TRSW select signal controls the direction of the Transmit/Receive switch.
Wireless LAN Network Interface Controller 7 Track ID JATR-1076-21 Rev. 1.2
Symbol Type Pin No Description
RFTXEN O 102 Not used in the RTL8255 RF chipset.
RFRXEN O 113 Not used in the RTL8255 RF chipset.
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
VREFO X
VRP
VRN
RXIP
RXIN
RXQP
RXQN
RXAGC
TXAGC
RSSI
TSSI0
TSSI1
TXQP
TXQN
TXIP
TXIN
TXQTP
TXQTN
TXITP
TXITN
O
O
O
O
O
O
X 119 Not used in the RTL8255 RF chipset.
X 120 Not used in the RTL8255 RF chipset.
I
I
I
I
O 4 Not used in the RTL8255 RF chipset.
O 5 Not used in the RTL8255 RF chipset.
I 6 Analog Input to the Receive Power A/D Converter for Receive AGC Control.
I 7 Input to the Transmit Power A/D Converter for 2.4GHz Transmit AGC Control.
I 8 Input to the Transmit Power A/D Converter for 5GHz Transmit AGC Control.
O
O
O
O
O
O
O
O
67
68
69
70
100
94
118
121
122
124
125
11
12
14
13
15
16
17
18
General purpose input/output pin.
General purpose input/output pin.
General purpose input/output pin.
General purpose input/output pin.
General purpose input/output pin.
General purpose input/output pin.
Not used in the RTL8255 RF chipset.
Receive (Rx) In-phase Analog Data.
Receive (Rx) Quadrature-phase Analog Data.
Transmit (TX) Quadrature-phase Analog Data.
Transmit (TX) In-phase Analog Data.
Not used in the RTL8255 RF chipset.
Not used in the RTL8255 RF chipset.
RTL8187L
Datasheet
6.6. Clock and Other Pins
Table 7. Clock and Other Pins
Symbol Type Pin No Description
R15K I/O 1 This pin must be pulled low by a 15K Ω resistor.
XI I 20 40MHz OSC Input.
Wireless LAN Network Interface Controller 8 Track ID JATR-1076-21 Rev. 1.2
RTL8187L
Datasheet
7. CPU Access to Endpoint Data
7.1. Control Transfer
Control transfers configure and send commands to a device. Because they are so important, they employ
extensive USB error checking. The host reserves a portion of each USB frame for control transfers. Control
transfers consist of two or three stages. The SETUP stage contains eight bytes of USB control data. An
optional DATA stage contains more data, if required. The STATUS stage allows the device to indicate
successful completion of a control operation.
7.2. Bulk Transfer
Bulk data is bursty, traveling in packets of 8, 16, 32, or 64 bytes at full speed, or at 512 bytes at high speed.
Bulk data has guaranteed accuracy due to an automatic retry mechanism for erroneous data. The host
schedules bulk packets when there is available bus time.
Wireless LAN Network Interface Controller 9 Track ID JATR-1076-21 Rev. 1.2
Loading...