Realtek RTL8139D, RTL8139D-GR, RTL8139DL, RTL8139D-LF, RTL8139DL-GR Schematic [ru]
...
RTL8139D
RTL8139DL
RTL8139D-LF
RTL8139DL-LF
RTL8139D-GR
RTL8139DL-GR
SINGLE-CHIP MULTI-FUNCTION 10/100Mbps
ETHERNET CONTROLLER WITH POWER
MANAGEMENT
DATASHEET
Rev. 1.2
08 Aug 2005
Track ID: JATR-1076-21
RTL8139DL
COPYRIGHT
©2005 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are
trademarks/registered trademarks of their respective owners.
Datasheet
USING THIS DOCUMENT
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision Release Date Summary
1.2 2005/08/08 Added section 13 Ordering Information, on page 61.
Added lead (Pb)-free and version package identification information on
page 2 and page 3.
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RTL8139DL
Datasheet
Table of Contents
1. GENERAL DESCRIPTION...............................................................................................................1
2. FEATURES ..........................................................................................................................................2
3. PIN ASSIGNMENTS ..........................................................................................................................2
3.1. PACKAGE IDENTIFICATION......................................................................................................2
3.2. P
4. PIN DESCRIPTIONS .........................................................................................................................4
ACKAGE IDENTIFICATION......................................................................................................3
4.1. P
4.2. PCI
4.3. EEPROM
4.4. P
4.5. LED
4.6. A
4.7. M
4.8. T
OWER MANAGEMENT/ISOLATION INTERFACE.......................................................................4
INTERFACE.......................................................................................................................4
INTERFACE.............................................................................................................6
OWER PINS............................................................................................................................6
INTERFACE .....................................................................................................................6
TTACHMENT UNIT INTERFACE..............................................................................................7
ULTI-FUNCTION INTERFACE ................................................................................................7
EST AND OTHER PINS ...........................................................................................................7
5. REGISTER DESCRIPTIONS............................................................................................................8
5.1. R
5.2. T
5.3. ERSR:
5.4. C
5.5. I
5.6. I
5.7. T
5.8. R
5.9. 9346CR:
5.10. CONFIG
5.11. CONFIG
5.12. M
5.13. CONFIG
5.14. CONFIG
5.15. M
5.16. PCI
5.17. T
5.18. B
5.19. B
5.20. A
5.21. A
5.22. A
5.23. D
ECEIVE STATUS REGISTER IN RX PACKET HEADER ............................................................10
RANSMIT STATUS REGISTER ...............................................................................................11
EARLY RX STATUS REGISTER ...................................................................................12
OMMAND REGISTER ...........................................................................................................12
NTERRUPT MASK REGISTER ................................................................................................13
NTERRUPT STATUS REGISTER ..............................................................................................13
RANSMIT CONFIGURATION REGISTER.................................................................................14
ECEIVE CONFIGURATION REGISTER....................................................................................15
93C46 COMMAND REGISTER.................................................................................18
0: CONFIGURATION REGISTER 0............................................................................19
1: CONFIGURATION REGISTER 1............................................................................20
EDIA STATUS REGISTER.....................................................................................................21
3: CONFIGURATION REGISTER3.............................................................................22
4: CONFIGURATION REGISTER4.............................................................................23
ULTIPLE INTERRUPT SELECT REGISTER .............................................................................24
REVISION ID ..................................................................................................................24
RANSMIT STATUS OF ALL DESCRIPTORS (TSAD) REGISTER ..............................................24
ASIC MODE CONTROL REGISTER........................................................................................25
ASIC MODE STATUS REGISTER ...........................................................................................26
UTO-NEGOTIATION ADVERTISEMENT REGISTER.................................................................26
UTO-NEGOTIATION LINK PARTNER ABILITY REGISTER .....................................................27
UTO-NEGOTIATION EXPANSION REGISTER .........................................................................28
ISCONNECT COUNTER ........................................................................................................28
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5.24. FALSE CARRIER SENSE COUNTER .........................................................................................28
5.25. NW
5.26. RX_ER
5.27. CS
5.28. C
AY TEST REGISTER.........................................................................................................29
COUNTER ................................................................................................................29
CONFIGURATION REGISTER.............................................................................................29
ONFIG5: CONFIGURATION REGISTER 5 ...............................................................................30
6. EEPROM (93C46) CONTENTS ......................................................................................................31
Datasheet
6.1. S
6.2. S
UMMARY OF RTL8139D(L) EEPROM REGISTERS ............................................................33
UMMARY OF EEPROM POWER MANAGEMENT REGISTERS................................................33
7. PCI CONFIGURATION SPACE REGISTERS.............................................................................34
7.1. PCI
7.2. PCI
7.3. D
7.4. PCI
CONFIGURATION SPACE TABLE .....................................................................................34
CONFIGURATION SPACE FUNCTIONS..............................................................................36
EFAULT VALUES AFTER POWER-ON (RSTB ASSERTED) ....................................................40
POWER MANAGEMENT FUNCTIONS ...............................................................................41
8. BLOCK DIAGRAM..........................................................................................................................45
9. FUNCTIONAL DESCRIPTION......................................................................................................46
9.1. T
9.2. R
9.3. B
9.4. L
9.5. C
9.6. L
9.7. T
9.8. C
9.9. R
9.10. F
RANSMIT OPERATION .........................................................................................................46
ECEIVE OPERATION ............................................................................................................46
ASE LINE WANDER COMPENSATION...................................................................................46
INE QUALITY MONITOR......................................................................................................46
LOCK RECOVERY MODULE.................................................................................................47
OOPBACK OPERATION ........................................................................................................47
X ENCAPSULATION .............................................................................................................47
OLLISION ............................................................................................................................47
X DECAPSULATION.............................................................................................................48
LOW CONTROL....................................................................................................................48
9.10.1. Control Frame Transmission...............................................................................................48
9.10.2. Control Frame Reception ....................................................................................................48
9.11. LED FUNCTIONS...................................................................................................................49
9.11.1. 10/100Mbps Link Monitor ...................................................................................................49
9.11.2. LED_RX...............................................................................................................................49
9.11.3. LED_TX ...............................................................................................................................50
9.11.4. LED_TX+LED_RX ..............................................................................................................50
10. APPLICATION DIAGRAM ............................................................................................51
11. ELECTRICAL CHARACTERISTICS ...........................................................................52
11.1. TEMPERATURE LIMIT RATINGS.............................................................................................52
11.2. DC
CHARACTERISTICS..........................................................................................................52
11.2.1. Supply Voltage Vcc = 3.0V min. to 3.6V max......................................................................52
11.2.2. Supply Voltage Vdd25 = 2.3V min. to 2.7V max. ................................................................52
11.3. AC CHARACTERISTICS..........................................................................................................53
11.3.1. PCI Bus Operation Timing ..................................................................................................53
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12. MECHANICAL DIMENSIONS ......................................................................................59
12.1. QFP ......................................................................................................................................59
12.2. LQFP....................................................................................................................................60
13. ORDERING INFORMATION.........................................................................................61
Datasheet
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Datasheet
1. General Description
The Realtek RTL8139D(L) is a highly integrated and cost-effective single-chip Fast Ethernet controller
that provides 32-bit performance, PCI bus master capability, and full compliance with IEEE 802.3u
100Base-T specifications and IEEE 802.3x Full Duplex Flow Control. It also supports Advanced
Configuration Power management Interface (ACPI), PCI power management for modern operating
systems that are capable of Operating System Directed Power Management (OSPM) to achieve the most
efficient power management possible. The RTL8139D(L) also supports shared Boot ROM pins & clock run
pin.
In addition to the ACPI feature, the RTL8139D(L) also supports remote wake-up (including AMD Magic
Packet, LinkChg, and Microsoft® wake-up frame) in both ACPI and APM environments. The
RTL8139D(L) is capable of performing an internal reset through the application of auxiliary power. When
auxiliary power is applied and the main power remains off, the RTL8139D(L) is ready and is waiting for
the Magic Packet or Link Change to wake the system up. Also, the LWAKE pin provides 4 different output
signals including active high, active low, positive pulse, and negative pulse. The versatility of the
RTL8139D(L) LWAKE pin provides motherboards with Wake-On-LAN (WOL) functionality.
The RTL8139D(L) also supports Analog Auto-Power-down, that is, the analog part of the RTL8139D(L)
can be shut down temporarily according to user requirement or when the RTL8139D(L) is in a power down
state with the wakeup function disabled. In addition, when the analog part is shut down and the IsolateB pin
is low (i.e. the main power is off), then both the analog and digital parts stop functioning and the power
consumption of the RTL8139D(L) will be negligible. The RTL8139D(L) also supports an auxiliary power
auto-detect function, and will auto-configure related bits of their own PCI power management registers in
PCI configuration space.
PCI Vital Product Data (VPD) is also supported to provide the information that uniquely identifies
hardware (Ex., the OEM brand name of RTL8139D(L) LAN card). The information may consist of part
number, serial number, and other detailed information.
To provide cost down support, the RTL8139D(L) is capable of using a 25MHz crystal or OSC as its internal
clock source.
The RTL8139D(L) keeps network maintenance costs low and eliminates usage barriers. It is the easiest
way to upgrade a network from 10 to 100Mbps. It also supports full-duplex operation, making 200Mbps
bandwidth possible at no additional cost. To improve compatibility with other brands’ products, the
RTL8139D(L) is also capable of receiving packets with InterFrameGap no less than 40 Bit-Time. The
RTL8139D(L) is highly integrated and requires no “glue” logic or external memory.
The RTL8139D(L) provides a flexible multi-function mode (Realtek patent pending) to incorporate other
PCI master devices, like a hardware modem. When in multi-function mode, the RTL8139D(L) acts as an
arbiter to distinguish LAN signals from those of other devices. The second device recognizes no difference
between being connected to the RTL8139D or a regular PCI bus.
The RTL8139D(L) includes a PCI and Expansion Memory Share Interface (Realtek’s patent pending) for a
boot ROM and can be used in diskless workstations, providing maximum network security and ease of
management.
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2. Features
RTL8139DL
Datasheet
100 pin QFP/LQFP
Integrated Fast Ethernet MAC, Physical chip
and transceiver in one chip
10Mbps and 100Mbps operation
Supports 10Mbps and 100Mbps N-way
Auto-negotiation operation
Supports PCI multi-function capabilities
PCI local bus single-chip Fast Ethernet
controller
Complies with PCI Revision 2.2
Supports PCI clock 16.75MHz-40MHz
Supports PCI target fast back-to-back
transaction
Provides PCI bus master data transfers
and PCI memory space or I/O space
mapped data transfers of
RTL8139D(L)'s operational registers
Supports PCI VPD (Vital Product
Data)
Supports ACPI, PCI power
management
Supports PCI multi-function to
incorporate with other PCI master
device
Supports 4 Wake-On-LAN (WOL) signals
(active high, active low, positive pulse, and
negative pulse)
Supports auxiliary power-on internal reset, to
be ready for remote wake-up when main
power remains off
Supports auxiliary power auto-detect, and sets
the related capability of power management
registers in PCI configuration space
Includes a programmable, PCI burst size and
early Tx/Rx threshold
Supports a 32-bit general-purpose timer with
the external PCI clock as clock source, to
generate timer-interrupt
Contains two large (2Kbyte) independent
receive and transmit FIFO’s
Advanced power saving mode when LAN
function or wakeup function is not used
Uses 93C46 (64*16-bit EEPROM) to store
resource configuration, ID parameter, and
VPD data
Supports LED pins for various network
activity indications
Supports loopback capability
Half/Full duplex capability
Supports 25MHz crystal or 25MHz
OSC as the internal clock source. The
frequency deviation of either crystal or
OSC must be within 50 PPM.
Complies with PC99 and PC2001 standards
Supports Wake-On-LAN function and remote
wake-up (Magic Packet*, LinkChg and
Supports Full Duplex Flow Control (IEEE
802.3x)
2.5/3.3V power supply with 5V tolerant I/Os
Up to 128K byte Boot ROM interface for both
EPROM and Flash memory is supported
0.25u CMOS process
Microsoft® wake-up frame)
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3. Pin Assignments
66 GND
67 RXIN-
68 RXIN+
69 NC
70 AVDD
71 TXD-
72 TXD+
73 GND
74 ISOLATEB
75 AVDD
76 NC
77 LED2
78 IDSEL2
79 LED1
80 LED0
RTL8139DL
Datasheet
65 RTSET
64 LWAKE
63 RTT3
62 GND
61 X1
60 X2
59 AVDD
58 AVDD25
57 PMEB
56 GND
55 VCTRL
54 GNTB2
53 REQB2
52 CLKRUNB
51 VDD25
81 INTAB
82 RSTB
83 CLK
84 GNTB
85 REQB
86 AD31
87 AD30
88 GND
89 AD29
90 VDD
91 AD28
92 AD27
93 AD26
94 AD25
95 AD24
96 VDD25
97 VDD
98 CBE3B
99 IDSEL
100 AD23
1 AD22
2 GND
3 AD21
4 AD20
5 AD19
6 VDD
7 NC
8 AD18
9 AD17
10 AD16
11 CBE2B
12 FRAMEB
13 IRDYB
14 TRDYB
DEVSELB
RTL8139D QFP
Figure 1. Pin Assignments (100-Pin QFP)
LLLLLLL
TXXXX TAIWAN
50 AUX
49 EECS
48 EESK
47 EEDI
46 EEDO
45 AD0
44 AD1
43 GND
42 AD2
41 AD3
40 NC
39 VDD
38 AD4
37 AD5
36 AD6
35 ROMCS/OEB
34 VDD
33 AD7
32 CBE0B
31 GND
30 AD8
29 AD9
28 AD10
27 AD11
26 AD12
25 AD13
24 AD14
23 AD15
22 VDD
21 CBE1B
20 PAR
19 SERRB
18 PERRB
17 STOPB
16 GND15
3.1. Package Identification
Lead (Pb)-free package is indicated by an ‘L’ in the location marked ‘T’ in Figure 1.
‘Green’ package is indicated by a ‘G’ in the location marked ‘T’ in Figure 1.
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RTL8139DL
63 RTT3
64 LWAKE
65 RTSET
66 GND
67 RXIN-
68 RXIN+
69 NC
70 AVDD
71 TXD-
72 TXD+
73 GND
74 ISOLATEB
75 AVDD
62 GND
61 X1
60 X2
59 AVDD
58 AVDD25
57 PMEB
56 GND
55 VCTRL
54 GNTB2
53 REQB2
52 CLKRUNB
51 VDD25
Datasheet
76 NC
77 LED2
78 IDSEL2
79 LED1
80 LED0
81 INTAB
82 RSTB
83 CLK
84 GNTB
85 REQB
86 AD31
87 AD30
88 GND
89 AD29
90 VDD
91 AD28
92 AD27
93 AD26
94 AD25
95 AD24
96 VDD25
97 VDD
98 CBE3B
99 IDSEL
100 AD23
1 AD22
2 GND
3 AD21
4 AD20
5 AD19
6 VDD
7 NC
8 AD18
9 AD17
10 AD16
11 CBE2B
12 FRAMEB
13 IRDYB
RTL8139DL LQFP
Figure 2. Pin Assignments (100-Pin LQFP)
LLLLLLL
TXXXX TAIWAN
50 AUX
49 EECS
48 EESK
47 EEDI
46 EEDO
45 AD0
44 AD1
43 GND
42 AD2
41 AD3
40 NC
39 VDD
38 AD4
37 AD5
36 AD6
35 ROMCS/OEB
34 VDD
33 AD7
32 CBE0B
31 GND
30 AD8
29 AD9
28 AD10
27 AD11
26 AD12
25 AD13
24 AD14
23 AD15
22 VDD
21 CBE1B
20 PAR
19 SERRB
18 PERRB
17 STOPB
16 GND
15 DEVSELB
14 TRDYB
3.2. Package Identification
Lead (Pb)-free package is indicated by an ‘L’ in the location marked ‘T’ in Figure 2.
‘Green’ package is indicated by a ‘G’ in the location marked ‘T’ in Figure 2.
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RTL8139DL
Datasheet
4. Pin Descriptions
Note that some pins have multiple functions. Refer to the Pin Assignment diagrams for a graphical
representation.
4.1. Power Management/Isolation Interface
Symbol Type Pin No Description
PMEB
(PME#)
ISOLATEB
(ISOLATE#)
LWAKE O 64
O/D 57
I 74
Power Management Event: Open drain, active low. Used by the
RTL8139D(L) to request a change in its current power management
state and/or to indicate that a power management event has occurred.
Isolate pin: Active low. Used to isolate the RTL8139D(L) from the PCI
bus. The RTL8139D(L) does not drive its PCI outputs (excluding
PME#) and does not sample its PCI input (including RST# and
PCICLK) as long as the Isolate pin is asserted.
LAN WAKE-UP signal: This signal is used to inform the motherboard
to execute the wake-up process. The motherboard must support
Wake-On-LAN (WOL). There are 4 choices of output, including active
high, active low, positive pulse, and negative pulse, that may be asserted
from the LWAKE pin. Please refer to the LWACT bit in the CONFIG1
register and the LWPTN bit in the CONFIG4 register for the setting of
this output signal. The default output is an active high signal.
Once a PME event is received, the LWAKE and PMEB assert at the
same time when the LWPME (bit4, CONFIG4) is set to 0. If the
LWPME is set to 1, the LWAKE asserts only when the PMEB asserts
and the ISOLATEB is low.
This pin is a 3.3V signaling output pin.
4.2. PCI Interface
Symbol Type Pin No Description
AD31-0 T/S 86,87,89,91-95,100,
1,3-5,8-10,23-30,33,
36-38,41,42,44,45
C/BE3-0 T/S 98,11,21,32 PCI bus command and byte enables multiplexed pins.
CLK I 83
DEVSELB S/T/S 15
FRAMEB S/T/S 12
PCI address and data multiplexed pins.
Pins AD31-24 are shared with BootROM data pins, while AD16-0 are
shared with BootROM address pins.
Clock: This PCI Bus clock provides timing for all transactions and bus
phases, and is input to PCI devices. The rising edge defines the start of
each phase. The clock frequency ranges from 0 to 33MHz.
Device Select: As a bus master, the RTL8139D(L) samples this signal
to insure that a PCI target recognizes the destination address for the data
transfer. As a target, the RTL8139D(L) asserts this signal low when it
recognizes its target address after FRAMEB is asserted.
Cycle Frame: As a bus master, this pin indicates the beginning and
duration of an access. FRAMEB is asserted low to indicate the start of a
bus transaction. While FRAMEB is asserted, data transfer continues.
When FRAMEB is deasserted, the transaction is in the final data phase.
As a target, the device monitors this signal before decoding the address
to check if the current transaction is addressed to it.
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Symbol Type Pin No Description
GNTB I 84
REQB T/S 85
IDSEL I 99
INTAB O/D 81
IRDYB S/T/S 13
TRDYB S/T/S 14
PAR T/S 20
PERRB S/T/S 18
SERRB O/D 19
STOPB S/T/S 17
RSTB I 82
Grant: This signal is asserted low to indicate to the RTL8139D(L) that
the central arbiter has granted ownership of the bus to the
RTL8139D(L). This input is used when the RTL8139D(L) is acting as a
bus master.
Request: The RTL8139D(L) will assert this signal low to request the
ownership of the bus from the central arbiter.
Initialization Device Select: This pin allows the RTL8139D(L) to
identify when configuration read/write transactions are intended for it.
INTAB: Used to request an interrupt. It is asserted low when an
interrupt condition occurs, as defined by the Interrupt Status, Interrupt
Mask and Interrupt Enable registers.
Initiator Ready: This indicates the initiating agent’s ability to complete
the current data phase of the transaction.
As a bus master, this signal will be asserted low when the RTL8139D(L)
is ready to complete the current data phase transaction. This signal is used
in conjunction with the TRDYB signal. Data transaction takes place at the
rising edge of CLK when both IRDYB and TRDYB are asserted low. As
a target, this signal indicates that the master has put data on the bus.
Target Ready: This indicates the target agent’s ability to complete the
current phase of the transaction.
As a bus master, this signal indicates that the target is ready for the data
during write operations and with the data during read operations. As a
target, this signal will be asserted low when the (slave) device is ready
to complete the current data phase transaction. This signal is used in
conjunction with the IRDYB signal. Data transaction takes place at the
rising edge of CLK when both IRDYB and TRDYB are asserted low.
Parity: This signal indicates even parity across AD31-0 and C/BE3-0
including the PAR pin. As a master, PAR is asserted during address and
write data phases. As a target, PAR is asserted during read data phases.
Parity Error: When the RTL8139D(L) is the bus master and a parity
error is detected, the RTL8139D(L) asserts both SERR bit in ISR and
Configuration Space command bit 8 (SERRB enable). Next, it
completes the current data burst transaction, then stops operation and
resets itself. After the host clears the system error, the RTL8139D(L)
continues its operation.
When the RTL8139D(L) is the bus target and a parity error is detected,
the RTL8139D(L) asserts this PERRB pin low.
System Error: If an address parity error is detected and Configuration
Space Status register bit 15 (detected parity error) is enabled,
RTL8139D(L) asserts both SERRB pin low and bit 14 of Status register
in Configuration Space.
Stop: Indicates the current target is requesting the master to stop the
current transaction.
Reset: When RSTB is asserted low, the RTL8139D(L) performs
internal system hardware reset. RSTB must be held for a minimum of
120 ns.
RTL8139DL
Datasheet
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RTL8139DL
Datasheet
4.3. EEPROM Interface
Symbol Type Pin No Description
AUX
EESK O 48 The MA2-0 pins are switched to EESK, EEDI, EEDO in 93C46
EEDI O 47 programming or auto-load mode.
EEDO O, I 46
EECS O 49
I
50
Aux. Power Detect: This pin is used to notify the RTL8139D(L) of the
existence of Aux. power during initial power-on or a PCI reset.
This pin should be pulled high to the Aux. power via a resistor to detect
the Aux. power. Doing so, will enable wakeup support from ACPI D3
cold or APM power-down. If this pin is not pulled high, the
RTL8139D(L) assumes that no Aux. power exists.
EEPROM chip select
4.4. Power Pins
Symbol Type Pin No Description
VDD P 6,22,34,39,90,97
AVDD P 59,70,75
VDD25 P 51,96
AVDD25 P 58
GND P 2,16,31,43,56,
62,66,73,88
+3.3V (Digital)
+3.3V (Analog)
+2.5V (Digital)
+2.5V (Analog)
Ground
4.5. LED Interface
Symbol Type Pin No Description
LED0, 1, 2 O 80,79,77 LED pins
LEDS1-0 00 01 10 11
LED0
LED1
LED2
During power down mode, the LED’s are OFF.
TX/RX TX/RX TX TX
LINK100 LINK10/100 LINK10/100 LINK100
LINK10 FULL RX LINK10
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4.6. Attachment Unit Interface
Symbol Type Pin No Description
TXD+
TXDRXIN+
RXINX1 I 61 25 MHz crystal/OSC. input.
X2 O 60
O
O
I
I
72
71
68
67
100/10BASE-T transmit (Tx) data.
100/10BASE-T receive (Rx) data.
Crystal feedback output: This output is used in crystal connection only.
It must be left open when X1 is driven with an external 25 MHz oscillator.
4.7. Multi-Function Interface
RTL8139DL
Datasheet
Symbol Type Pin No Description
REQB2 IN 53
GNTB2 T/S,O 54
IDSEL2 O 78
Request2: The 2
ownership of the PCI bus.
Grant2: This signal is asserted low to indicate that the central arbiter
has granted ownership of the bus to the 2
Initialization Device Select 2: Used as a chip-select during
configuration read and write transactions to the 2
nd
device will assert this pin low to request the
nd
device.
nd
device.
4.8. Test And Other Pins
Symbol Type Pin No Description
RTT3 TEST 63 Chip test pin.
RTSET I/O 65 This pin must be pulled low by a resistor. Please refer to the application
circuit for correct value.
VCTRL Analog 55 Use this pin and an external PNP type transistor to generate +2.5V for
the RTL8139D(L).
ROMCS/OEB O 35
CLKRUNB I/O 52
NC - 7,40,69,76
ROM Chip Select and Output Enable: This is the chip select signal
and output enable for the Boot PROM.
Clock Run: This signal is used by the RTL8139D(L) to request starting
(or speeding up) the clock, CLK. CLKRUNB also indicates the clock
status. For the RTL8139D(L), CLKRUNB is an open drain output as
well as an input. The RTL8139D(L) requests the central resource to
start, speed up, or maintain the interface clock by the assertion of
CLKRUNB. For the host system, it is an S/T/S signal. The host system
(central resource) is responsible for maintaining CLKRUNB asserted,
and for driving it high to the negated (deasserted) state.
Reserved
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Track ID: JATR-1076-21 Rev. 1.2
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RTL8139DL
Datasheet
5. Register Descriptions
The RTL8139D(L) provides the following set of operational registers mapped into PCI memory space or
I/O space.
Offset
0000h R/W IDR0 ID Register 0, The ID register0-5 are only permitted to read/write by
0001h R/W IDR1 ID Register 1
0002h R/W IDR2 ID Register 2
0003h R/W IDR3 ID Register 3
0004h R/W IDR4 ID Register 4
0005h R/W IDR5 ID Register 5
0006h-0007h - - Reserved
0008h R/W MAR0 Multicast Register 0, The MAR register0-7 are only permitted to
0009h R/W MAR1 Multicast Register 1
000Ah R/W MAR2 Multicast Register 2
000Bh R/W MAR3 Multicast Register 3
000Ch R/W MAR4 Multicast Register 4
000Dh R/W MAR5 Multicast Register 5
000Eh R/W MAR6 Multicast Register 6
000Fh R/W MAR7 Multicast Register 7
0010h-0013h R/W TSD0 Transmit Status of Descriptor 0
0014h-0017h R/W TSD1 Transmit Status of Descriptor 1
0018h-001Bh R/W TSD2 Transmit Status of Descriptor 2
001Ch-001Fh R/W TSD3 Transmit Status of Descriptor 3
0020h-0023h R/W TSAD0 Transmit Start Address of Descriptor0
0024h-0027h R/W TSAD1 Transmit Start Address of Descriptor1
0028h-002Bh R/W TSAD2 Transmit Start Address of Descriptor2
002Ch-002Fh R/W TSAD3 Transmit Start Address of Descriptor3
0030h-0033h R/W RBSTART Receive (Rx) Buffer Start Address
0034h-0035h R ERBCR Early Receive (Rx) Byte Count Register
0036h R ERSR Early Rx Status Register
0037h R/W CR Command Register
0038h-0039h R/W CAPR Current Address of Packet Read
003Ah-003Bh R CBR Current Buffer Address: The initial value is 0000h. It reflects total
003Ch-003Dh R/W IMR Interrupt Mask Register
003Eh-003Fh R/W ISR Interrupt Status Register
0040h-0043h R/W TCR Transmit (Tx) Configuration Register
0044h-0047h R/W RCR Receive (Rx) Configuration Register
0048h-004Bh R/W TCTR Timer CounT Register: This register contains a 32-bit general-purpose
004Ch-004Fh R/W MPC Missed Packet Counter: Indicates the number of packets discarded due
R/W Tag Description
4-byte access. Read access can be byte, word, or double word access.
The initial value is autoloaded from EEPROM EthernetID field.
read/write by 4-byte access. Read access can be byte, word, or double
word access. Driver is responsible for initializing these registers.
received byte-count in the rx buffer.
timer. Writing any value to this 32-bit register will reset the original
timer and begin to count from zero.
to Rx FIFO overflow. It is a 24-bit counter. After s/w reset, MPC is
cleared. Only the lower 3 bytes are valid.
Single Chip Multifunction 10/100 Ethernet Controller w/Power Management
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RTL8139DL
Datasheet
Offset
0050h R/W 9346CR 93C46 Command Register
0051h R/W CONFIG0 Configuration Register 0
0052h R/W CONFIG1 Configuration Register 1
0053H - - Reserved
0054h-0057h
0058h R/W MSR Media Status Register
0059h R/W CONFIG3 Configuration register 3
005Ah R/W CONFIG4 Configuration register 4
005Bh - - Reserved
005Ch-005Dh R/W MULINT Multiple Interrupt Select
005Eh R RERID PCI Revision ID = 10h.
005Fh - - Reserved.
0060h-0061h R TSAD Transmit Status of All Descriptors
0062h-0063h R/W BMCR Basic Mode Control Register
0064h-0065h R BMSR Basic Mode Status Register
0066h-0067h R/W ANAR Auto-Negotiation Advertisement Register
0068h-0069h R ANLPAR Auto-Negotiation Link Partner Register
006Ah-006Bh R ANER Auto-Negotiation Expansion Register
006Ch-006Dh R DIS Disconnect Counter
006Eh-006Fh R FCSC False Carrier Sense Counter
0070h-0071h R/W NWAYTR N-way Test Register
0072h-0073h R REC RX_ER Counter
0074h-0075h R/W CSCR CS Configuration Register
0076-0077h - - Reserved.
0078h-007Bh R/W PHY1_PARM PHY parameter 1
007Ch-007Fh R/W TW_PARM Twister parameter
0080h R/W PHY2_PARM PHY parameter 2
0081-0083h - - Reserved
0084h R/W CRC0 Power Management CRC register0 for wakeup frame0
0085h R/W CRC1 Power Management CRC register1 for wakeup frame1
0086h R/W CRC2 Power Management CRC register2 for wakeup frame2
0087h
0088h R/W CRC4 Power Management CRC register4 for wakeup frame4
0089h R/W CRC5 Power Management CRC register5 for wakeup frame5
008Ah R/W CRC6 Power Management CRC register6 for wakeup frame6
008Bh R/W CRC7 Power Management CRC register7 for wakeup frame7
008Ch–0093h R/W Wakeup0 Power Management wakeup frame0 (64bit)
0094h–009Bh R/W Wakeup1 Power Management wakeup frame1 (64bit)
009Ch–00A3h R/W Wakeup2 Power Management wakeup frame2 (64bit)
00A4h–00ABh R/W Wakeup3 Power Management wakeup frame3 (64bit)
00ACh–00B3h R/W Wakeup4 Power Management wakeup frame4 (64bit)
00B4h–00BBh R/W Wakeup5 Power Management wakeup frame5 (64bit)
00BCh–00C3h R/W Wakeup6 Power Management wakeup frame6 (64bit)
00C4h–00CBh R/W Wakeup7 Power Management wakeup frame7 (64bit)
00CCh R/W LSBCRC0 LSB of the mask byte of wakeup frame0 within offset 12 to 75
R/W Tag Description
When written any value, MPC will be reset also.
R /W
R/W
TimerInt
CRC3 Power Management CRC register3 for wakeup frame3
Timer Interrupt Register. Once having written a nonzero value to this
register, the Timeout bit of ISR register will be set whenever the
TCTR reaches to this value. The Timeout bit will never be set as long
as TimerInt register is zero.
Single Chip Multifunction 10/100 Ethernet Controller w/Power Management
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RTL8139DL
Datasheet
Offset
00CDh R/W LSBCRC1 LSB of the mask byte of wakeup frame1 within offset 12 to 75
00CEh R/W LSBCRC2 LSB of the mask byte of wakeup frame2 within offset 12 to 75
00CFh R/W LSBCRC3 LSB of the mask byte of wakeup frame3 within offset 12 to 75
00D0h R/W LSBCRC4 LSB of the mask byte of wakeup frame4 within offset 12 to 75
00D1h R/W LSBCRC5 LSB of the mask byte of wakeup frame5 within offset 12 to 75
00D2h R/W LSBCRC6 LSB of the mask byte of wakeup frame6 within offset 12 to 75
00D3h R/W LSBCRC7 LSB of the mask byte of wakeup frame7 within offset 12 to 75
00D4h-00D7h - - Reserved.
00D8h R/W Config5 Configuration register 5
00D9h-00FFh - - Reserved.
R/W Tag Description
5.1. Receive Status Register in Rx Packet Header
Bit R/W Symbol Description
15 R MAR
14 R PAM
13 R BAR
12-6 - -
5 R ISE
4 R RUNT
3 R LONG
2 R CRC
1 R FAE
0 R ROK
Multicast Address Received: This bit set to 1 indicates that a multicast
packet is received.
Physical Address Matched: This bit set to 1 indicates that the destination
address of this packet matches the value written in ID registers.
Broadcast Address Received: This bit set to 1 indicates that a broadcast
packet is received. BAR, MAR bit will not be set simultaneously.
Reserved
Invalid Symbol Error: (100BASE-TX only) This bit set to 1 indicates
that an invalid symbol was encountered during the reception of this packet.
Runt Packet Received: This bit set to 1 indicates that the received packet
length is smaller than 64 bytes ( i.e. media header + data + CRC < 64
bytes )
Long Packet: This bit set to 1 indicates that the size of the received
packet exceeds 4k bytes.
CRC Error: When set, indicates that a CRC error occurred on the
received packet.
Frame Alignment Error: When set, indicates that a frame alignment
error occurred on this received packet.
Receive OK: When set, indicates that a good packet is received.
Single Chip Multifunction 10/100 Ethernet Controller w/Power Management
Track ID: JATR-1076-21 Rev. 1.2
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RTL8139DL
Datasheet
5.2. Transmit Status Register
(TSD0-3)(Offset 0010h-001Fh, R/W)
The read-only bits (CRS, TABT, OWC, CDH, NCC3-0, TOK, TUN) will be cleared by the RTL8139D(L)
when the Transmit Byte Count (bits 12-0) in the corresponding Tx descriptor is written. It is not affected
when software writes to these bits. These registers are only permitted to write by double-word access. After
software reset, all bits except OWN bit are reset to “0”.
Bit R/W Symbol Description
31 R CRS
30 R TABT
29 R OWC
28 R CDH
27-24 R NCC3-0
23-22 - 21-16 R/W ERTXTH5-0
15 R TOK
14 R TUN
13 R/W OWN
12-0 R/W SIZE
Carrier Sense Lost: This bit is set to 1 when the carrier is lost during
transmission of a packet.
Transmit Abort: This bit is set to 1 if the transmission of a packet was
aborted. This bit is read only, writing to this bit is not affected.
Out of Window Collision: This bit is set to 1 if the RTL8139D(L)
encountered an "out of window" collision during the transmission of a
packet.
CD Heart Beat: The NIC watches for a collision signal (ie, CD
Heartbeat signal) during the first 6.4us of the interframe gap following a
transmission. This bit is set if the transceiver fails to send this signal.
This bit is cleared in the 100 Mbps mode.
Number of Collision Count: Indicates the number of collisions
encountered during the transmission of a packet.
Reserved
Early Tx Threshold: Specifies the threshold level in the Tx FIFO to
begin the transmission. When the byte count of the data in the Tx FIFO
reaches this level, (or the FIFO contains at least one complete packet)
the RTL8139D(L) will transmit this packet.
000000 = 8 bytes
These fields count from 000001 to 111111 in unit of 32 bytes.
This threshold must avoid exceeding 2K bytes.
Transmit OK: Set to 1 indicates that the transmission of a packet was
completed successfully and no transmit underrun has occurred.
Transmit FIFO Underrun: Set to 1 if the Tx FIFO was exhausted
during the transmission of a packet. The RTL8139D(L) can re-transfer
data if the Tx FIFO underruns and can also transmit the packet to the
wire successfully even though the Tx FIFO underruns. That is, when
TSD<TUN>=1, TSD<TOK>=0 and ISR<TOK>=1 (or ISR<TER>=1).
OWN: The RTL8139D(L) sets this bit to 1 when the Tx DMA
operation of this descriptor was completed. The driver must set this bit
to 0 when the Transmit Byte Count (bits 0-12) is written. The default
value is 1.
Descriptor Size: The total size in bytes of the data in this descriptor. If
the packet length is more than 1792 byte (0700h), the Tx queue will be
invalid, i.e. the next descriptor will be written only after the OWN bit of
that long packet's descriptor has been set.
Single Chip Multifunction 10/100 Ethernet Controller w/Power Management
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5.3. ERSR: Early Rx Status Register
(Offset 0036h, R)
Bit R/W Symbol Description
7-4 - -
3 R ERGood
2 R ERBad
1 R EROVW
0 R EROK
Reserved
Early Rx Good packet: This bit is set whenever a packet is completely
received and the packet is good. Writing a 1 to this bit will clear it.
Early Rx Bad packet: This bit is set whenever a packet is completely
received and the packet is bad. Writing a 1 to this bit will clear it.
Early Rx OverWrite: This bit is set when the RTL8139D(L)'s local
address pointer is equal to CAPR. In the early mode, this is different
from buffer overflow. It happens that the RTL8139D(L) detected an Rx
error and wanted to fill another packet data from the beginning address
of that error packet. Writing a 1 to this bit will clear it.
Early Rx OK: The power-on value is 0. It is set when the Rx byte count
of the arriving packet exceeds the Rx threshold. After the whole packet
is received, the RTL8139D(L) will set ROK or RER in ISR and clear
this bit simultaneously. Setting this bit will invoke a ROK interrupt.
RTL8139DL
Datasheet
5.4. Command Register
(Offset 0037h, R/W)
This register is used for issuing commands to the RTL8139D(L). These commands are issued by setting the
corresponding bits for the function. A global software reset along with individual reset and enable/disable
for transmitter and receiver are provided here.
Bit R/W Symbol Description
7-5 - -
4 R/W RST
3 R/W RE
2 R/W TE
1 - 0 R BUFE
Reserved
Reset: Setting to 1 forces the RTL8139D(L) to a software reset state
which disables the transmitter and receiver, reinitializes the FIFOs,
resets the system buffer pointer to the initial value (Tx buffer is at
TSAD0, Rx buffer is empty). The values of IDR0-5 and MAR0-7 and
PCI configuration space will have no changes. This bit is 1 during the
reset operation, and is cleared to 0 by the RTL8139D(L) when the reset
operation is complete.
Receiver Enable: When set to 1, and the receive state machine is idle,
the receive machine becomes active. This bit will read back as a 1
whenever the receive state machine is active. After initial power-up,
software must insure that the receiver has completely reset before
setting this bit.
Transmitter Enable: When set to 1, and the transmit state machine is
idle, then the transmit state machine becomes active. This bit will read
back as a 1 whenever the transmit state machine is active. After initial
power-up, software must insure that the transmitter has completely reset
before setting this bit.
Reserved
Buffer Empty: Rx Buffer Empty. There is no packet stored in the Rx
buffer ring.
Single Chip Multifunction 10/100 Ethernet Controller w/Power Management
Track ID: JATR-1076-21 Rev. 1.2
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RTL8139DL
Datasheet
5.5. Interrupt Mask Register
(Offset 003Ch-003Dh, R/W)
This register masks the interrupts that can be generated from the Interrupt Status Register. A hardware reset
will clear all mask bits. Setting a mask bit allows the corresponding bit in the Interrupt Status Register to
cause an interrupt. The Interrupt Status Register bits are always set to 1 if the condition is present,
regardless of the state of the corresponding mask bit.
Bit R/W Symbol Description
15 R/W SERR
14 R/W TimeOut
13 R/W LenChg
12-7 - -
6 R/W FOVW
5 R/W PUN/LinkChg
4 R/W RXOVW
3 R/W TER
2 R/W TOK
1 R/W RER
0 R/W ROK
System Error Interrupt: 1 => Enable, 0 => Disable.
Time Out Interrupt: 1 => Enable, 0 => Disable.
Cable Length Change Interrupt: 1 => Enable, 0 => Disable.
Reserved
Rx FIFO Overflow Interrupt: 1 => Enable, 0 => Disable.
Packet Underrun/Link Change Interrupt: 1 => Enable, 0 =>
Disable.
Rx Buffer Overflow Interrupt: 1 => Enable, 0 => Disable.
Transmit Error Interrupt: 1 => Enable, 0 => Disable.
Transmit OK Interrupt: 1 => Enable, 0 => Disable.
Receive Error Interrupt: 1 => Enable, 0 => Disable.
Receive OK Interrupt: 1 => Enable, 0 => Disable.
5.6. Interrupt Status Register
(Offset 003Eh-003Fh, R/W)
This register indicates the source of an interrupt when the INTA pin goes active. Enabling the
corresponding bits in the Interrupt Mask Register (IMR) allows bits in this register to produce an interrupt.
When an interrupt is active, one of more bits in this register are set to a “1”. The interrupt Status Register
reflects all current pending interrupts, regardless of the state of the corresponding mask bit in the IMR.
Reading the ISR clears all interrupts. Writing to the ISR has no effect.
Bit R/W Symbol Description
15 R/W SERR
14 R/W TimeOut
13 R/W LenChg
12 - 7 - -
6 R/W FOVW
5 R/W PUN/LinkChg
4 R/W RXOVW
3 R/W TER
2 R/W TOK
1 R/W RER
System Error: Set to 1 when the RTL8139D(L) signals a system error
on the PCI bus.
Time Out: Set to 1 when the TCTR register reaches to the value of the
TimerInt register.
Cable Length Change: Cable length is changed after Receiver is enabled.
Reserved
Rx FIFO Overflow: Set when an overflow occurs on the Rx status FIFO.
Packet Underrun/Link Change: Set to 1 when CAPR is written but
Rx buffer is empty, or when link status is changed.
Rx Buffer Overflow: Set when receive (Rx) buffer ring storage
resources have been exhausted.
Transmit (Tx) Error: Indicates that a packet transmission was
aborted, due to excessive collisions, according to the TXRR's setting.
Transmit (Tx) OK: Indicates that a packet transmission is completed
successfully.
Receive (Rx) Error: Indicates that a packet has either CRC error or
Single Chip Multifunction 10/100 Ethernet Controller w/Power Management
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RTL8139DL
f
Bit R/W Symbol Description
frame alignment error (FAE). The collided frame will not be recognized
as CRC error if the length of this frame is shorter than 16 byte.
0 R/W ROK
Receive (Rx) OK: In normal mode, indicates the successful completion
of a packet reception. In early mode, indicates that the Rx byte count of
the arriving packet exceeds the early Rx threshold.
Datasheet
5.7. Transmit Configuration Register
(Offset 0040h-0043h, R/W)
This register defines the Transmit Configuration for the RTL8139D(L). It controls such functions as
Loopback, Heartbeat, Auto Transmit Padding, programmable Interframe Gap, Fill and Drain Thresholds,
and maximum DMA burst size.
Bit R/W Symbol Description
31 - -
30-26 R HWVERID_A
25-24 R/W IFG1, 0
23-22 R HWVERID_B
21-19 - -
18, 17 R/W LBK1, LBK0
Reserved
Hardware Version ID A:
Bit30 Bit29 Bit28 Bit27 Bit26 Bit23 Bit22
RTL8139 1 1 0 0 0 0 0
RTL8139A 1 1 1 0 0 0 0
RTL8139A-G 1 1 1 0 1 0 0
RTL8139B 1 1 1 1 0 0 0
RTL8130 1 1 1 1 0 0 0
RTL8139C 1 1 1 0 1 0 0
RTL8100 1 1 1 1 0 1 0
RTL8100B/
8139D
RTL8139C+ 1 1 1 0 1 1 0
RTL8101 1 1 1 0 1 1 1
Reserved Other combination
Interframe Gap Time: This field allows the user to adjust the
interframe gap time below the standard: 9.6 us for 10Mbps, 960 ns for
100Mbps. The time can be programmed from 9.6 us to 8.4 us (10Mbps)
and 960ns to 840ns (100Mbps). Note that any value other than (1, 1)
will violate the IEEE 802.3 standard.
The formula for the inter frame gap is:
10 Mbps 8.4us + 0.4(IFG(1:0)) us
100 Mbps 840ns + 40(IFG(1:0)) ns
Hardware Version ID B
Reserved
Loopback test: There will be no packet on the TX+/- lines under the
Loopback test condition. The loopback function must be independent o
the link state.
00 : normal operation
01 : Reserved
10 : Reserved
11 : Loopback mode
1 1 1 0 1 0 1
Single Chip Multifunction 10/100 Ethernet Controller w/Power Management
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Bit R/W Symbol Description
16 R/W CRC
15-11 - -
10-8 R/W MXDMA2, 1, 0
7-4 R/W TXRR
3-1 - -
0 W CLRABT
Append CRC: Setting to 1 means that there is no CRC appended at the
end of a packet. Setting to 0 means that there is CRC appended at the
end of a packet.
Reserved
Max DMA Burst Size per Tx DMA Burst: This field sets the
maximum size of transmit DMA data bursts according to the following
table:
000 = 16 bytes
001 = 32 bytes
010 = 64 bytes
011 = 128 bytes
100 = 256 bytes
101 = 512 bytes
110 = 1024 bytes
111 = 2048 bytes
Tx Retry Count: These are used to specify additional transmission
retries in multiple of 16(IEEE 802.3 CSMA/CD retry count). If the
TXRR is set to 0, the transmitter will re-transmit 16 times before
aborting due to excessive collisions. If the TXRR is set to a value
greater than 0, the transmitter will re-transmit a number of times equals
to the following formula before aborting:
Total retries = 16 + (TXRR * 16)
The TER bit in the ISR register or transmit descriptor will be set when
the transmission fails and reaches to this specified retry count.
Reserved
Clear Abort: Setting this bit to 1 causes the RTL8139D(L) to
retransmit the packet at the last transmitted descriptor when this
transmission was aborted, Setting this bit is only permitted in the
transmit abort state.
RTL8139DL
Datasheet
5.8. Receive Configuration Register
(Offset 0044h-0047h, R/W)
This register is used to set the receive configuration for the RTL8139D(L). Receive properties such as
accepting error packets, runt packets, setting the receive drain threshold etc. are controlled here.
Bit R/W Symbol Description
31-28 - 27-24 R/W ERTH3, 2, 1, 0
Single Chip Multifunction 10/100 Ethernet Controller w/Power Management
Reserved
Early Rx threshold bits: These bits are used to select the Rx threshold
multiplier of the whole packet that has been transferred to the system
buffer in early mode when the frame protocol is under the
RTL8139D(L)'s definition.
0000 = no early rx threshold 0001 = 1/16
0010 = 2/16 0011 = 3/16
0100 = 4/16 0101 = 5/16
0110 = 6/16 0111 = 7/16
1000 = 8/16 1001 = 9/16
1010 = 10/16 1011 = 11/16
1100 = 12/16 1101 = 13/16
Track ID: JATR-1076-21 Rev. 1.2
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