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LICENSE
This product is covered by one or more of the following patents: US5,307,459, US5,434,872,
US5,732,094, US6,570,884, US6,115,776, and US6,327,625.
Datasheet
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
Integrated Gigabit Ethernet Controller for PCI Express ii Track ID: JATR-2265-11 Rev. 1.1
RTL8111E
Datasheet
Table of Contents
1. GENERAL DESCRIPTION..............................................................................................................................................1
3. SYSTEM APPLICATIONS...............................................................................................................................................3
5.5.REGULATOR AND REFERENCE......................................................................................................................................6
5.9.POWER AND GROUND ..................................................................................................................................................8
6.1.PCIEXPRESS BUS INTERFACE......................................................................................................................................9
6.2.1. Link Monitor...........................................................................................................................................................9
6.2.2. RX LED ................................................................................................................................................................10
6.2.5. LINK/ACT LED ....................................................................................................................................................11
6.2.6. Customizable LED Configuration ........................................................................................................................12
6.7.VITAL PRODUCT DATA (VPD)...................................................................................................................................18
8.1.ABSOLUTE MAXIMUM RATINGS ................................................................................................................................21
8.7.1. Serial EEPROM Interface Timing........................................................................................................................24
8.8.PCIEXPRESS BUS PARAMETERS................................................................................................................................25
TABLE 5.REGULATOR AND REFERENCE ......................................................................................................................................6
TABLE 9.POWER AND GROUND ...................................................................................................................................................8
TABLE 14.FEATURE CONTROL TABLE-1.....................................................................................................................................13
TABLE 15.FEATURE CONTROL TABLE-2.....................................................................................................................................13
TABLE 18.ABSOLUTE MAXIMUM RATINGS ................................................................................................................................21
TABLE 28.AUXILIARY SIGNAL TIMING PARAMETERS.................................................................................................................30
TABLE 29.ORDERING INFORMATION ..........................................................................................................................................32
FIGURE 7.SINGLE-ENDED MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT AND SWING ..................................................28
FIGURE 8.SINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT ...........................................................................28
FIGURE 9.SINGLE-ENDED MEASUREMENT POINTS FOR RISE AND FALL TIME MATCHING ........................................................28
FIGURE 10.DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE AND PERIOD ...................................................................29
FIGURE 11.DIFFERENTIAL MEASUREMENT POINTS FOR RISE AND FALL TIME ...........................................................................29
FIGURE 12.DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK............................................................................................29
FIGURE 13.REFERENCE CLOCK SYSTEM MEASUREMENT POINT AND LOADING .........................................................................30
FIGURE 14.AUXILIARY SIGNAL TIMING......................................................................................................................................30
Integrated Gigabit Ethernet Controller for PCI Express v Track ID: JATR-2265-11 Rev. 1.1
RTL8111E
Datasheet
1. General Description
The Realtek RTL8111E-VL-CG Gigabit Ethernet controller combines a triple-speed IEEE 802.3
compliant Media Access Controller (MAC) with a triple-speed Ethernet transceiver, PCI Express bus
controller, and embedded memory. With state-of-the-art DSP technology and mixed-mode signal
technology, the RTL8111E offers high-speed transmission over CAT 5 UTP cable or CAT 3 UTP
(10Mbps only) cable. Functions such as Crossover Detection and Auto-Correction, polarity correction,
adaptive equalization, cross-talk cancellation, echo cancellation, timing recovery, and error correction are
implemented to provide robust transmission and reception capability at high speeds.
The RTL8111E supports the PCI Express 1.1 bus interface for host communications with power
management, and is compliant with the IEEE 802.3u specification for 10/100Mbps Ethernet and the IEEE
802.3ab specification for 1000Mbps Ethernet. It also supports an auxiliary power auto-detect function,
and will auto-configure related bits of the PCI power management registers in PCI configuration space.
The RTL8111E features embedded One-Time-Programmable (OTP) memory to replace the external
EEPROM (93C46/93C56/93C66).
Advanced Configuration Power management Interface (ACPI)—power management for modern
operating systems that are capable of Operating System-directed Power Management (OSPM)—is
supported to achieve the most efficient power management possible. PCI MSI (Message Signaled
Interrupt) and MSI-X are also supported.
In addition to the ACPI feature, remote wake-up (including AMD Magic Packet and Microsoft Wake-up
frame) is supported in both ACPI and APM (Advanced Power Management) environments. To support
WOL from a deep power down state (e.g., D3cold, i.e., main power is off and only auxiliary exists), the
auxiliary power source must be able to provide the needed power for the RTL8111E.
The RTL8111E is fully compliant with Microsoft NDIS5, NDIS6 (IPv4, IPv6, TCP, UDP) Checksum and
Segmentation Task-offload (Large send and Giant send) features, and supports IEEE 802 IP Layer 2
priority encoding and IEEE 802.1Q Virtual bridged Local Area Network (VLAN). The above features
contribute to lowering CPU utilization, especially benefiting performance when in operation on a network
server.
The RTL8111E supports Receive Side Scaling (RSS) to hash incoming TCP connections and
load-balance received data processing across multiple CPUs. RSS improves the number of transactions
per second and number of connections per second, for increased network throughput.
The RTL8111E supports Protocol offload. It offloads some of the most common protocols to NIC
hardware in order to prevent spurious wake up and further reduce power consumption. The RTL8111E
can offload ARP (IPv4) and NS (IPv6) protocols while in the D3 power saving state.
The RTL8111E supports IEEE 802.3az Draft 3.0, also known as Energy Efficient Ethernet (EEE). IEEE
802.3az operates with the IEEE 802.3 Media Access Control (MAC) Sublayer to support operation in
Low Power Idle mode. When the Ethernet network is in low link utilization, EEE allows systems on both
sides of the link to save power.
The device also features inter-connect PCI Express technology. PCI Express is a high-bandwidth,
low-pin-count, serial, interconnect technology that offers significant improvements in performance over
conventional PCI and also maintains software compatibility with existing PCI infrastructure.
The RTL8111E is suitable for multiple market segments and emerging applications, such as desktop,
mobile, workstation, server, communications platforms, and embedded applications.
Used to reactivate the PCI Express slot’s main power rails and reference clocks.
Refer to the reference schematic for strapping pin information.
All strapping pins are power-on-latch pins.
Isolate Pin: Active low.
Used to isolate the RTL8111E from the PCI Express bus. The RTL8111E will not
drive its PCI Express outputs (excluding LANWAKEB) and will not sample its
PCI Express input as long as the Isolate pin is asserted.
EEDO I 31 Input from Serial Data Output Pin of EEPROM.
30 EECS: EEPROM Chip Select.
EECS O
Refer to the reference schematic for strapping pin information.
All strapping pins are power-on-latch pins.
Refer to the reference schematic for strapping pin information.
All strapping pins are power-on-latch pins.
5.7. LEDs
Table 7. LEDs
Symbol Type Pin No Description
LED0 O
LED1 O
LED3 O 31
Note 1: During power down mode, the LED signals are logic high.
Note 2: LEDS1-0’s initial value comes from the EEPROM. If there is no EEPROM, the default value of the
(LEDS1, LEDS0)=(1, 1).
40
37
See section 6.2.6 Customizable LED Configuration, page 12 for details.
RTL8111E
Datasheet
When implementing dual color LEDs and EEPROM at the same time:
Pin31 and Pin37 of the RTL8111E are shared pins. Follow the RTLRTL8111E reference design (version
1.00 or later) to select these 2 pins for a dual-color LED circuit. Otherwise, the RTLRTL8111E EEPROM
may not function.
5.8. SMBus
Table 8. SMBus
Symbol Type Pin No Description
SMBus Clock.
SMBCLK O/D 14
SMBDATA O/D 15
SMBALERT O/D 38
Refer to the reference schematic for strapping pin information.
All strapping pins are power-on-latch pins.
SMBus Data.
Refer to the reference schematic for strapping pin information.
All strapping pins are power-on-latch pins.
SMBus Alert.
Refer to the reference schematic for strapping pin information.
All strapping pins are power-on-latch pins.