Realtek RTL8100C, RTL8100CL Schematic [ru]

RTL8100C & RTL8100CL

SINGLE-CHIP FAST ETHERNET CONTROLLER

WITH POWER MANAGEMENT

DATASHEET

Rev. 1.06

05 November 2004

Track ID: JATR-1076-21

RTL8100C & RTL8100CL

Datasheet

COPYRIGHT

©2004 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,

transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any

means without the written permission of Realtek Semiconductor Corp.

DISCLAIMER

Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,

including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in

this document or in the product described in this document at any time. This document could include

technical inaccuracies or typographical errors.

TRADEMARKS

Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are

trademarks/registered trademarks of their respective owners.

USING THIS DOCUMENT

This document provides detailed user guidelines to achieve the best performance when implementing a

2-layer board PC design with the RTL8100C or RTL8100CL Single-Chip Fast Ethernet Controller with

Power Management Control.

Though every effort has been made to ensure that this document is current and accurate, more information

may have become available subsequent to the production of this guide. In that event, please contact your

Realtek representative for additional information that may help in the development process.

REVISION HISTORY

Revision Release Date

1.01 2003/01/20 First release.

1.02 2003/02/24 Revised pin functions/descriptions.

1.03 2003/10/30 Add Ordering Information.

Summary

- Add pin description for Pin32.

- Pin 45 becomes NC pin.

- Pin Reallocation: Reallocate XTAL1 from Pin 125 to Pin 121 (Pin 125
becomes NC pin)

- Pin Reallocation: Reallocate XTAL2 from Pin 126 to Pin 122 (Pin126
becomes NC pin)

- Pin Reassignment: Pin 123 reassigned to GND

- Pin Reassignment: Pin 124 reassigned to GND

1.04 2004/03/30 Pins 64, 88,113 become NC pins (see Table 7, page 9).
Revised format

1.05 2004/06/16 Added Lead-Free package part numbers to Ordering Information, page 65.

1.06 2004/11/05 Corrected minor typing errors.

Single-Chip Fast Ethernet Controller ii Track ID: JATR-1076-21 Rev. 1.06

RTL8100C & RTL8100CL

Datasheet

Table of Contents

1. GENERAL DESCRIPTION...............................................................................................................1

2. FEATURES..........................................................................................................................................2

3. BLOCK DIAGRAM............................................................................................................................3

4. PIN ASSIGNMENTS ..........................................................................................................................4

4.1. RTL8100C (QFP) & RTL8100CL (LQFP).....................................................................................4

5. PIN DESCRIPTION............................................................................................................................5

5.1. POWER MANAGEMENT/ISOLATION INTERFACE ................................................................................5

5.2. PCI INTERFACE ................................................................................................................................6

5.3. EPROM/EEPROM INTERFACE/AUX .............................................................................................8

5.4. POWER PINS .....................................................................................................................................8

5.5. LED INTERFACE...............................................................................................................................8

5.6. ATTACHMENT UNIT INTERFACE .......................................................................................................9

5.7. TEST AND OTHER PINS .....................................................................................................................9

5.8. REGISTER DESCRIPTIONS................................................................................................................10

5.9. RECEIVE STATUS REGISTER IN RX PACKET HEADER.....................................................................12

5.10. TRANSMIT STATUS REGISTER (TSD0-3)(OFFSET 0010H-001FH, R/W) ........................................13

5.11. ERSR: EARLY RX STATUS REGISTER (OFFSET 0036H, R) ............................................................14

5.12. COMMAND REGISTER (OFFSET 0037H, R/W).................................................................................15

5.13. INTERRUPT MASK REGISTER (OFFSET 003CH-003DH, R/W).........................................................15

5.14. INTERRUPT STATUS REGISTER (OFFSET 003EH-003FH, R/W) .......................................................16

5.15. TRANSMIT CONFIGURATION REGISTER (OFFSET 0040H-0043H, R/W)...........................................17

5.16. RECEIVE CONFIGURATION REGISTER (OFFSET 0044H-0047H, R/W).............................................19

5.17. 9346CR: 93C46 COMMAND REGISTER (OFFSET 0050H, R/W) .....................................................22

5.18. CONFIG 0: CONFIGURATION REGISTER 0 (OFFSET 0051H, R/W)................................................23

5.19. CONFIG 1: CONFIGURATION REGISTER 1 (OFFSET 0052H, R/W)................................................23

5.20. MEDIA STATUS REGISTER (OFFSET 0058H, R/W) ..........................................................................24

5.21. CONFIG 3: CONFIGURATION REGISTER3 (OFFSET 0059H, R/W).................................................25

5.22. CONFIG 4: CONFIGURATION REGISTER4 (OFFSET 005AH, R/W)................................................27

5.23. MULTIPLE INTERRUPT SELECT REGISTER (OFFSET 005CH-005DH, R/W).....................................28

Single-Chip Fast Ethernet Controller iii Track ID: JATR-1076-21 Rev. 1.06

RTL8100C & RTL8100CL

Datasheet

5.24. PCI REVISION ID (OFFSET 005EH, R)............................................................................................28

5.25. TRANSMIT STATUS OF ALL DESCRIPTORS (TSAD) REGISTER (OFFSET 0060H-0061H, R/W) .......28

5.26. BASIC MODE CONTROL REGISTER (OFFSET 0062H-0063H, R/W)..................................................29

5.27. BASIC MODE STATUS REGISTER (OFFSET 0064H-0065H, R)..........................................................29

5.28. AUTO-NEGOTIATION ADVERTISEMENT REGISTER (OFFSET 0066H-0067H, R/W).........................30

5.29. AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (OFFSET 0068H-0069H, R) ...................31

5.30. AUTO-NEGOTIATION EXPANSION REGISTER (OFFSET 006AH-006BH, R) .....................................32

5.31. DISCONNECT COUNTER ..................................................................................................................32

5.32. FALSE CARRIER SENSE COUNTER (OFFSET 006EH-006FH, R) .......................................................32

5.33. NWAY TEST REGISTER (OFFSET 0070H-0071H, R/W)...................................................................33

5.34. RX_ER COUNTER (OFFSET 0072H-0073H, R) ...............................................................................33

5.35. CS CONFIGURATION REGISTER (OFFSET 0074H-0075H, R/W) ......................................................33

5.36. CONFIG5: CONFIGURATION REGISTER 5 (OFFSET 00D8H, R/W)....................................................34

5.37. EEPROM (93C46) CONTENTS ......................................................................................................35

5.38. RTL8100C(L) EEPROM REGISTERS SUMMARY ..........................................................................37

5.39. EEPROM POWER MANAGEMENT REGISTERS SUMMARY ..............................................................37

6. PCI CONFIGURATION SPACE REGISTERS.............................................................................38

6.1. PCI CONFIGURATION SPACE TABLE...............................................................................................38

6.2. PCI CONFIGURATION SPACE FUNCTIONS .......................................................................................39

6.3. PCI CONFIGURATION SPACE STATUS .............................................................................................41

6.4. DEFAULT VALUES AFTER POWER-ON (RSTB ASSERTED)..............................................................44

6.5. PCI POWER MANAGEMENT FUNCTIONS.........................................................................................45

6.5.1. Power Down Mode ..............................................................................................................45

6.6. VPD (V

ITAL PRODUCT DATA) .......................................................................................................48

7. FUNCTIONAL DESCRIPTION......................................................................................................49

7.1. TRANSMIT OPERATION ...................................................................................................................49

7.2. R

ECEIVE OPERATION......................................................................................................................49

7.3. WANDER COMPENSATION ..............................................................................................................49

7.4. SIGNAL DETECT .............................................................................................................................49

7.5. LINE QUALITY MONITOR ...............................................................................................................50

7.6. CLOCK RECOVERY MODULE ..........................................................................................................50

7.7. L

OOPBACK OPERATION ..................................................................................................................50

7.8. TX ENCAPSULATION.......................................................................................................................50

7.9. COLLISION......................................................................................................................................50

Single-Chip Fast Ethernet Controller ii Track ID: JATR-1076-21 Rev. 1.06

RTL8100C & RTL8100CL

Datasheet

7.10. RX DECAPSULATION ......................................................................................................................51

7.11. FLOW CONTROL .............................................................................................................................51

7.11.1. Control Frame Transmission...............................................................................................51

7.11.2. Control Frame Reception ....................................................................................................51

7.12. LED FUNCTIONS ............................................................................................................................52

7.12.1. 10/100Mbps Link Monitor...................................................................................................52

7.12.2. LED_RX...............................................................................................................................52

7.12.3. LED_TX ...............................................................................................................................53

7.12.4. LED_TX+LED_RX..............................................................................................................53

8. CHARACTERISTICS ......................................................................................................................54

8.1. THERMAL CHARACTERISTICS .........................................................................................................54

8.2. DC CHARACTERISTICS ...................................................................................................................54

8.2.1. Supply Voltage (Vcc = 3.0V min. to 3.6V max.)..................................................................54

8.2.2. Supply Voltage (Vdd25 = 2.3V min. to 2.7V max.)..............................................................54

8.3. AC CHARACTERISTICS ...................................................................................................................55

8.3.1. PCI Bus Operation Timing ..................................................................................................55

9. APPLICATION INFORMATION ..................................................................................................61

10. MECHANICAL DIMENSIONS ......................................................................................................62

10.1. RTL8100C 128-PIN QFP...............................................................................................................62

10.2. NOTES FOR RTL8100C 128-PIN QFP ............................................................................................63

10.3. RTL8100CL 128-P

IN LQFP..........................................................................................................64

10.4. NOTES FOR RTL8100CL 128-PIN LQFP .......................................................................................65

11. ORDERING INFORMATION ........................................................................................................65

Single-Chip Fast Ethernet Controller iii Track ID: JATR-1076-21 Rev. 1.06

RTL8100C & RTL8100CL

Datasheet

List of Tables

Table 1. Power Management/Isolation Interface.........................................................................................5

Table 2. PCI Interface ..................................................................................................................................6

Table 3. EPROM/EEPROM Interface/AUX ...............................................................................................8

Table 4. Power Pins .....................................................................................................................................8

Table 5. LED Interface ................................................................................................................................8

Table 6. Attachment Unit Interface..............................................................................................................9

Table 7. Test and Other Pins ........................................................................................................................9

Table 8. Register Descriptions...................................................................................................................10

Table 9. Receive Status Register in RX Packet Header.............................................................................12

Table 10. Transmit Status Register ..............................................................................................................13

Table 11. ERSR: Early RX Status Register .................................................................................................14

Table 12. Command Register.......................................................................................................................15

Table 13. Interrupt Mask Register ...............................................................................................................15

Table 14. Interrupt Status Register ..............................................................................................................16

Table 15. Transmit Configuration Register .................................................................................................17

Table 16. Receive Configuration Register...................................................................................................19

Table 17. 9346CR: 93C46 Command Register ...........................................................................................22

Table 18. CONFIG 0: Configuration Register 0..........................................................................................23

Table 19. CONFIG 1: Configuration Register 1..........................................................................................23

Table 20. Media Status Register ..................................................................................................................24

Table 21. CONFIG 3: Configuration Register3...........................................................................................25

Table 22. CONFIG 4: Configuration Register4...........................................................................................27

Table 23. Multiple Interrupt Select Register ...............................................................................................28

Table 24. PCI Revision ID...........................................................................................................................28

Table 25. Transmit Status of All Descriptors (TSAD) Register ..................................................................28

Table 26. Basic Mode Control Register.......................................................................................................29

Table 27. Basic Mode Status Register .........................................................................................................29

Table 28. Auto-Negotiation Advertisement Register...................................................................................30

Table 29. Auto-Negotiation Link Partner Ability Register..........................................................................31

Table 30. Auto-Negotiation Expansion Register .........................................................................................32

Table 31. Disconnect Counter......................................................................................................................32

Table 32. False Carrier Sense Counter ........................................................................................................32

Table 33. NWay Test Register......................................................................................................................33

Single-Chip Fast Ethernet Controller ii Track ID: JATR-1076-21 Rev. 1.06

RTL8100C & RTL8100CL

Datasheet

Table 34. RX_ER Counter...........................................................................................................................33

Table 35. CS Configuration Register...........................................................................................................33

Table 36. Config5. Configuration Register 5...............................................................................................34

Table 37. EEPROM (93C46) Contents........................................................................................................35

Table 38. RTL8100C(L) EEPROM Registers Summary.............................................................................37

Table 39. EEPROM Power Management Registers Summary....................................................................37

Table 40. PCI Configuration Space Table ...................................................................................................38

Table 41. PCI Configuration Space Functions ............................................................................................40

Table 42. PCI Configuration Space Status...................................................................................................41

Table 43. Base IO Address...........................................................................................................................42

Table 44. Base Memory Address for Memory Accesses .............................................................................43

Table 45. Default Values after Power-On (RSTB Asserted)........................................................................44

Table 46. Thermal Characteristics ...............................................................................................................54

Table 47. Supply Voltage (3.0V min. to 3.6V max.)....................................................................................54

Table 48. Supply Voltage (2.3V min. to 2.7V max.)....................................................................................54

Single-Chip Fast Ethernet Controller iii Track ID: JATR-1076-21 Rev. 1.06

RTL8100C & RTL8100CL

Datasheet

List of Figures

Figure 1. Block Diagram .............................................................................................................................3

Figure 2. Pin Assignments ...........................................................................................................................4

Figure 3. LED_RX.....................................................................................................................................52

Figure 4. LED_TX.....................................................................................................................................53

Figure 5. LED_TX+LED_RX ...................................................................................................................53

Figure 6. Target Read.................................................................................................................................55

Figure 7. Target Write................................................................................................................................55

Figure 8. Configuration Read ....................................................................................................................56

Figure 9. Configuration Write....................................................................................................................56

Figure 10. Bus Arbitration...........................................................................................................................57

Figure 11. Memory Read.............................................................................................................................57

Figure 12. Memory Write ............................................................................................................................58

Figure 13. Target Initiated Termination - Retry...........................................................................................58

Figure 14. Target Initiated Termination - Disconnect..................................................................................59

Figure 15. Target Initiated Termination - Abort...........................................................................................59

Figure 16. Master Initiated Termination – Abort.........................................................................................60

Figure 17. Parity Operation - One Example ................................................................................................60

Figure 18. Application Information .............................................................................................................61

Single-Chip Fast Ethernet Controller iv Track ID: JATR-1076-21 Rev. 1.06

RTL8100C & RTL8100CL

Datasheet

1. General Description

The Realtek RTL8100C(L) is a highly integrated, cost-effective single-chip Fast Ethernet controller that
provides 32-bit performance, PCI bus master capability, and full compliance with IEEE 802.3u 100Base-T
specifications and IEEE 802.3x Full Duplex Flow Control. It also supports the Advanced Configuration
and Power Interface (ACPI), PCI power management for modern operating systems that are capable of
Operating System-Directed Power Management (OSPM) to achieve the most efficient power management
possible. The RTL8100C(L) does not support CardBus mode (the RTL8139C does).

In addition to the ACPI feature, the RTL8100C(L) also supports remote wake-up (including AMD Magic
Packet, LinkChg, and Microsoft® wake-up frame) in both ACPI and APM (Advanced Power Management)
environments. The RTL8100C(L) is capable of performing an internal reset through the application of
auxiliary power. When auxiliary power is applied and the main power remains off, the RTL8100C(L) is
ready and waiting for a Magic Packet or Link Change to wake the system up. Also, the LWAKE pin
provides 4 output signals (active high, active low, positive pulse, and negative pulse). The versatility of the
RTL8100C(L) LWAKE pin provides motherboards with Wake-On-LAN (WOL) functionality.

The RTL8100C(L) also supports Analog Auto-Power-down. The analog part of the RTL8100C(L) can be
shut down temporarily according to user requirements, or when the RTL8100C(L) is in a power down state
with the wakeup function disabled. When the analog part is shut down and the IsolateB pin is low (i.e. the
main power is off), both the analog and digital parts stop functioning and the power consumption of the
RTL8100C(L) is negligible. The RTL8100C(L) also supports an auxiliary power auto-detect function, and
will auto-configure related bits of its PCI power management registers in PCI configuration space.

PCI Vital Product Data (VPD) is also supported to provide hardware identifier information. The
information may consist of part number, serial number, OEM brand name, and other detailed information.

To provide cost down support, the RTL8100C(L) is capable of using a 25MHz crystal or OSC as its internal
clock source.

The RTL8100C(L) keeps network maintenance costs low and eliminates usage barriers. It is the easiest way
to upgrade a network from 10 to 100Mbps. It also supports full-duplex operation, making 200Mbps
bandwidth possible at no additional cost. To improve compatibility with other brands’ products, the
RTL8100C(L) is also capable of receiving packets with an InterFrame Gap equal to or more than 40-bit
time. The RTL8100C(L) is highly integrated and requires no glue logic or external memory.

Single-Chip Fast Ethernet Controller 1 Track ID: JATR-1076-21 Rev. 1.06

2. Features

RTL8100C & RTL8100CL

Datasheet

 128-pin QFP/LQFP

 Integrated Fast Ethernet MAC, Physical chip,

and transceiver in one chip

 10Mbps and 100Mbps operation

 Supports 10Mbps and 100Mbps NWay

auto-negotiation

 PCI local bus single-chip Fast Ethernet

controller

 Complies with PCI Revision 2.2

 Supports PCI clock 16.75MHz-40MHz

 Supports PCI target fast back-to-back

transaction

 Provides PCI bus master data transfers and

PCI memory space or I/O space mapped
data transfers of the RTL8100C(L)’s
operational registers

 Supports PCI VPD (Vital Product Data)

 Supports ACPI, PCI power management

 Supports 25MHz crystal or 25MHz OSC as the

internal clock source. The frequency deviation
of either crystal or OSC must be within
50PPM.

 Complies with the PC99/PC2001 standard

 Supports Wake-On-LAN and remote wake-up

(Magic Packet*, LinkChg, and Microsoft®
wake-up frame)

 Supports 4 Wake-On-LAN (WOL) signals

(active high, active low, positive pulse, and
negative pulse)

 Supports auxiliary power-on internal reset, to

be ready for remote wake-up when main
power remains off

 Supports auxiliary power auto-detect, and sets

the related capability of power management
registers in PCI configuration space

 Includes programmable PCI burst size and

early Tx/Rx threshold

 Supports a 32-bit general-purpose timer, with

the external PCI clock as clock source, for
generating timer-interrupts

 Contains two (2Kbyte) independent receive

and transmit FIFOs

 Advanced power saving mode when LAN and

wakeup function are not used

 Uses 93C46 (64*16-bit EEPROM) to store

resource configuration, ID parameter, and
VPD data

 Supports LED pins for various network

activity indications

 Supports loopback capability

 Half/Full duplex capability

 Supports Full Duplex Flow Control

(IEEE 802.3x)

 2.5/3.3V power supply with 5V tolerant I/Os.

 0.25µm CMOS process

* Third-party brands and names are the property of their respective owners.

Note: The QFP package model number is RTL8100C. The LQFP package model number is RTL8100CL.

Single-Chip Fast Ethernet Controller 2 Track ID: JATR-1076-21 Rev. 1.06

3. Block Diagram

RTL8100C & RTL8100CL

Datasheet

PCI

Interface

MII

Interface

PHY

half /full

MAC

10/100

Switch

Logic

100M

Power Control Logic

Interrupt

Control

Logic

PCI Interface + Register

FIFO

5B 4B
Decoder

4B 5B
Encoder

EEPROM

Interface

Early Interrupt

Threshold

Register

Early Interrupt

Control Logic

Control

Data

Alignment

FIFO

Logic

Scrambler

LED Driver

Packet Leng th

Transmit/

Receive

Interface

Descrambler

Register

Logic

Packet Type

Discriminator

MII

Interface

RXD

RXC 25M

TXD

TXC 25M

TXC 25M

TXD

RXC 25M

RXD

TXC10
TXD10

RXC10
RXD10

Transceiver

Serial to
Parrallel

10/100M Auto-negotiation

Control Logic

10M

Manchester Coded

Waveform

Data Recovery Receive Low Pass Filter

TD+

Variable Current

3 Level

Comparator

Slave

PLL

MLT-3

to NRZI

Parrallel

to Serial

ck

Data

Baseline

Wander

Correction

Control
Voltage

10M Output Waveform

Figure 1. Block Diagram

Shaping

3 Level

Driver

Peak

Detect

Adaptive

Equalizer

Master

PPL

25M

Link Pulse

TXO+
TXO -

RXIN+

RXIN-

Single-Chip Fast Ethernet Controller 3 Track ID: JATR-1076-21 Rev. 1.06

RTL8100C & RTL8100CL

4. Pin Assignments

4.1. RTL8100C (QFP) & RTL8100CL (LQFP)

128

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

1

TX+

2

TX-

3

AVDD33

4

GND

5

RX+

6

RX-

7

AVDD33

8

CTRL25

9

NC

10

NC

11

NC

12

AVDD25

13

NC

14

NC

15

NC

16

NC

17

GND

18

NC

19

NC

20

AVDD33(REG)

21

GND

22

NC

23

ISOLATEB

24

NC

25

INTAB

26

VDD33

27

PCIRSTB

28

PCICLK

29

GNTB

30

REQB

31

PMEB

32

VDD25

33

AD31

34

AD30

35

GND

36

AD29

37

AD28

38

GND

127

GND

RSET

NC

NC

GND

GND

XTAL2

XTAL1

NC

NC

GND

LED0NCLED1

LED2

NC

NC

NC

EESK

EEDO

AUX / EEDI

EECS

VDD33

LANWAKE

104

103

AD0

AD1

DEVSELB

CLKRUNB

AD2
GND
GND

VDD25

AD3

AD4

AD5

AD6

VDD33

AD7

CBEB0

GND

AD8

AD9

NC
AD10
AD11
AD12

VDD33

AD13
AD14

GND
GND

AD15

VDD25
CBEB1

PAR

SERRB

NC

NC

NC

VDD33

PERRB

STOPB

TRDYB

GND

Datasheet

102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65

AD27

AD26

AD25

AD24

VDD33

39404142434445464748495051525354555657585960616263

CBEB3NCIDSEL

AD23NCAD22

AD21

GND

GND

AD20

VDD25

AD19

VDD33

AD18

AD17

AD16

CBEB2

FRAMEBNCIRDYB

NC

64

Figure 2. Pin Assignments

Single-Chip Fast Ethernet Controller 4 Track ID: JATR-1076-21 Rev. 1.06

RTL8100C & RTL8100CL

5. Pin Description

5.1. Power Management/Isolation Interface

The following signal type codes are used in the tables:

I: Input.

O: Output.

T/S: Tri-State bi-directional input/output pin.

S/T/S: Sustained Tri-State.

O/D: Open Drain.

Table 1. Power Management/Isolation Interface

Symbol Type Pin No Description

PMEB
(PME#)

ISOLATEB
(ISOLATE#)

LWAKE O 105 LAN WAKE-UP Signal.

O/D 31 Power Management Event.

Open drain, active low. Used by the RTL8100C(L) to request a
change in its current power management state and/or to indicate that
a power management event has occurred.

I 23 Isolate Pin: Active low.

Isolates the RTL8100C(L) from the PCI bus. The RTL8100C(L) does
not drive its PCI outputs (excluding PME#) and does not sample its
PCI input (including RST# and PCICLK) as long as the Isolate pin is
asserted.

Signals to the motherboard that it should execute the wake-up
process. The motherboard must support Wake-On-LAN (WOL).
There are 4 output choices, active high, active low, positive pulse,
and negative pulse, that may be asserted from the LWAKE pin. See
the LWACT bit in Table 19. CONFIG 1: Configuration Register 1,
page 23, for the setting of this output signal. The default output is an
active high signal.

When a PME event is received, LWAKE and PMEB assert at the
same time if LWPME (bit4, CONFIG4) is set to 0. If LWPME is set
to 1, LWAKE asserts only when PMEB asserts and ISOLATEB is
low.

This pin is a 3.3V signaling output pin.

Datasheet

Single-Chip Fast Ethernet Controller 5 Track ID: JATR-1076-21 Rev. 1.06

RTL8100C & RTL8100CL

5.2. PCI Interface

Table 2. PCI Interface

Symbol Type Pin No Description

AD31-0 T/S 33, 34, 36, 37, 39, 40,

42, 43, 47, 49, 50, 53,
55, 57, 58, 59, 79, 82,
83, 85, 86, 87, 89, 90,

93, 95, 96, 97, 98, 103,

104

C/BE3-0 T/S 44, 60, 77, 92 PCI Bus Command and Byte Enables Multiplexed Pins.
CLK I 28 Clock.

DEVSELB S/T/S 68 Device Select.

FRAMEB S/T/S 61 Cycle Frame.

GNTB I 29 Grant.

REQB T/S 30 Request.

IDSEL I 46 Initialization Device Select.

INTAB O/D 25 INTAB.

PCI Address and Data Multiplexed Pins.

This PCI Bus clock provides timing for all transactions and bus
phases, and is input to PCI devices. The rising edge defines the start
of each phase. The clock frequency ranges from 0 to 40MHz. For
normal network operation, the RTL8100C(L) requires a minimum
PCI clock frequency of 16.75MHz.

As a bus master, the RTL8100C (L) samples this signal to ensure that
a PCI target recognizes the destination address for the data transfer.
As a target, the RTL8100C(L) asserts this signal low when it
recognizes its target address after FRAMEB is asserted.

As a bus master, this pin indicates the beginning and duration of an
access. FRAMEB is asserted low to indicate the start of a bus
transaction. While FRAMEB is asserted, data transfer continues.
When FRAMEB is deasserted, the transaction is in the final data
phase.

As a target, the device monitors this signal before decoding the
address to check if the current transaction is addressed to it.

This signal is asserted low to indicate to the RTL8100C(L) that the
central arbiter has granted ownership of the bus to the RTL8100C(L).
This input is used when the RTL8100C(L) is acting as a bus master.

The RTL8100C(L) will assert this signal low to request the
ownership of the bus from the central arbiter.

This pin allows the RTL8100C(L) to identify when configuration
read/write transactions are intended for it.

Used to request an interrupt. It is asserted low when an interrupt
condition occurs, as defined by the Interrupt Status, Interrupt Mask
and Interrupt Enable registers.

Datasheet

Single-Chip Fast Ethernet Controller 6 Track ID: JATR-1076-21 Rev. 1.06

Symbol Type Pin No Description

IRDYB S/T/S 63 Initiator Ready.

This indicates the initiating agent’s ability to complete the current
data phase of the transaction.

As a bus master, this signal will be asserted low when the
RTL8100C(L) is ready to complete the current data phase
transaction. This signal is used in conjunction with the TRDYB
signal. Data transaction takes place at the rising edge of CLK when
both IRDYB and TRDYB are asserted low. As a target, this signal
indicates that the master has put data on the bus.

TRDYB S/T/S 67 Target Ready.

This indicates the target agent’s ability to complete the current phase
of the transaction.

As a bus master, this signal indicates that the target is ready for the
data during write operations and holds the data during read
operations. As a target, this signal will be asserted low when the
(slave) device is ready to complete the current data phase transaction.
This signal is used in conjunction with the IRDYB signal. Data
transaction takes place at the rising edge of CLK when both IRDYB
and TRDYB are asserted low.

PAR T/S 76 Parity.

This signal indicates even parity across AD31-0 and C/BE3-0
including the PAR pin. As a master, PAR is asserted during address
and write data phases. As a target, PAR is asserted during read data
phases.

PERRB S/T/S 70 Parity Error.

When the RTL8100C(L) is the bus master and a parity error is
detected, the RTL8100C(L) asserts both the SERR bit in ISR, and
Configuration Space command bit 8 (SERRB enable). Next, it
completes the current data burst transaction, then stops operation and
resets itself. After the host clears the system error, the RTL8100C(L)
continues its operation.

When the RTL8100C(L) is the bus target and a parity error is
detected, the RTL8100C(L) asserts this PERRB pin low.

SERRB O/D 75 System Error.

If an address parity error is detected and Configuration Space Status
register bit 15 (detected parity error) is enabled, the RTL8100C(L)
asserts both the SERRB pin low, and bit 14 of the Status register in
Configuration Space.

STOPB S/T/S 69 Stop.

Indicates the current target is requesting the master to stop the current
transaction.

RSTB I 27 Reset.

When RSTB is asserted low, the RTL8100C(L) performs an internal
system hardware reset. RSTB must be held for a minimum of 120ns.

RTL8100C & RTL8100CL

Datasheet

Single-Chip Fast Ethernet Controller 7 Track ID: JATR-1076-21 Rev. 1.06

RTL8100C & RTL8100CL

5.3. EPROM/EEPROM Interface/AUX

Table 3. EPROM/EEPROM Interface/AUX

Symbol Type Pin No Description

EESK
EEDO
AUX / EEDI I/O 109 Aux. Power Detect.

EECS O 106 EEPROM chip select.

O

O, I

111
108

The MA2-0 pins are switched to EESK, EEDI, EEDO in 93C46
programming or auto-load mode.

This pin is used to notify the RTL8100C(L) of the existence of Aux.
power (only during initial power-on). This pin should be pulled high
to the auxiliary power (5VPM or 3VAUX) via a resistor to detect the
Aux. power. Doing so will enable wakeup support from ACPI D3
cold or APM power-down. If this pin is not pulled high, the
RTL8100C(L) assumes that no auxiliary power exists.

EEDI: After Aux. Power On Detection is complete; EEDI is enabled
to support EEPROM auto-load operation.

Datasheet

5.4. Power Pins

Table 4. Power Pins

Symbol Type Pin No Description

VDD33 P 26, 41, 56, 71,

84, 94, 107

AVDD33 P 3, 7, 20 +3.3V (Analog).
VDD25 P 32, 54, 78, 99 +2.5V (Digital).
AVDD25 P 12 +2.5V (Analog).
GND P 4, 17, 21, 35, 38, 51,

52, 66, 80, 81, 91, 100,

101, 119, 123, 124, 128

+3.3V (Digital)

Ground.

5.5. LED Interface

Table 5. LED Interface

Symbol Type Pin No Description

LED0, 1, 2 O 117, 115, 114 LED Pins

LED0 TX/RX TX/RX TX TX
LED1 LINK100 LINK10/100 LINK10/100 LINK100
LED2 LINK10 FULL RX LINK10
During power down mode, the LEDs are OFF.

LEDS1-0 00 01 10 11

Single-Chip Fast Ethernet Controller 8 Track ID: JATR-1076-21 Rev. 1.06

RTL8100C & RTL8100CL

Datasheet

5.6. Attachment Unit Interface

Table 6. Attachment Unit Interface

Symbol Type Pin No Description

TXD+
TXD­RXIN+
RXIN­X1 I 121 25MHz Crystal/OSC Input.
X2 O 122 Crystal Feedback Output.

O
O

1
2

I
I

5
6

100/10Base-T Transmit (TX) data.

100/10Base-T Receive (RX) data.

This output is used in a crystal connection only. It must be left open when
X1 is driven with an external 25MHz oscillator.

5.7. Test and Other Pins

Table 7. Test and Other Pins

Symbol Type Pin No Description

RTT3 TEST 123 Chip Test pin.
RTSET I/O 127 This pin must be pulled low by a resistor.

Refer to section 9 Application Information, page 61, for the correct
value.

CTRL25 Analog 8 Use this pin and an external PNP type transistor to generate +2.5V for

the RTL8100C(L).

CLKRUN I/O 65 Clock Run.

This signal is used to request starting (or speeding up) of the clock.
CLKRUN also indicates the clock status. CLKRUN is an open drain
output as well as an input. The RTL8100C(L) requests the central
resource to start, speed up, or maintain the interface clock by the
assertion of CLKRUN. For the host system, it is an S/T/S signal. The
host system (central resource) is responsible for maintaining
CLKRUN asserted, and for driving it high to the negated (deasserted)
state.

NC - 9~11,13~16, 18, 19, 22,

24, 45, 48, 62, 72~74,

110, 112, 116, 118,

120, 125, 126

Not Connected.

Single-Chip Fast Ethernet Controller 9 Track ID: JATR-1076-21 Rev. 1.06

RTL8100C & RTL8100CL

Datasheet

5.8. Register Descriptions

The RTL8100C(L) provides the following set of operational registers mapped into PCI memory space or
I/O space.

Table 8. Register Descriptions

Offset R/W Tag Description

0000h R/W IDR0 ID Register 0.

ID registers 0-5 are only permitted to read/write via 4-byte access.
Read access can be byte, word, or double word access. The initial

value is autoloaded from the EEPROM EthernetID field.
0001h R/W IDR1 ID Register 1.
0002h R/W IDR2 ID Register 2.
0003h R/W IDR3 ID Register 3.
0004h R/W IDR4 ID Register 4.
0005h R/W IDR5 ID Register 5.
0006h-0007h - - Reserved.
0008h R/W MAR0 Multicast Address Register 0.

The MAR register 0-7 are only permitted to read/write via 4-byte

access. Read access can be byte, word, or double word access. The

driver is responsible for initializing these registers.
0009h R/W MAR1 Multicast Address Register 1.
000Ah R/W MAR2 Multicast Address Register 2.
000Bh R/W MAR3 Multicast Address Register 3.
000Ch R/W MAR4 Multicast Address Register 4.
000Dh R/W MAR5 Multicast Address Register 5.
000Eh R/W MAR6 Multicast Address Register 6.
000Fh R/W MAR7 Multicast Address Register 7.
0010h-0013h R/W TSD0 Transmit Status of Descriptor 0.
0014h-0017h R/W TSD1 Transmit Status of Descriptor 1.
0018h-001Bh R/W TSD2 Transmit Status of Descriptor 2.
001Ch-001Fh R/W TSD3 Transmit Status of Descriptor 3.
0020h-0023h R/W TSAD0 Transmit Start Address of Descriptor 0.
0024h-0027h R/W TSAD1 Transmit Start Address of Descriptor 1.
0028h-002Bh R/W TSAD2 Transmit Start Address of Descriptor 2.
002Ch-002Fh R/W TSAD3 Transmit Start Address of Descriptor 3.
0030h-0033h R/W RBSTART Receive (Rx) Buffer Start Address.
0034h-0035h R ERBCR Early Receive (Rx) Byte Count Register.
0036h R ERSR Early Rx Status Register.
0037h R/W CR Command Register.
0038h-0039h R/W CAPR Current Address of Packet Read.
003Ah-003Bh R CBR Current Buffer Address.

The initial value is 0000h. It reflects total received byte-count in the

Rx buffer.
003Ch-003Dh R/W IMR Interrupt Mask Register.
003Eh-003Fh R/W ISR Interrupt Status Register.
0040h-0043h R/W TCR Transmit (Tx) Configuration Register.

Single-Chip Fast Ethernet Controller 10 Track ID: JATR-1076-21 Rev. 1.06

RTL8100C & RTL8100CL

Datasheet

Offset R/W Tag Description

0044h-0047h R/W RCR Receive (Rx) Configuration Register.
0048h-004Bh R/W TCTR Timer CounT Register.

This register contains a 32-bit general-purpose timer. Writing any

value to this register will reset the original timer and start a count

from zero.
004Ch-004Fh R/W MPC Missed Packet Counter.

Indicates the number of packets discarded due to Rx FIFO

overflow. It is a 24-bit counter. After s/w reset, MPC is cleared.

Only the lower 3 bytes are valid.

When any value is written, MPC will be reset also.
0050h R/W 9346CR 93C46 Command Register.
0051h R/W CONFIG0 Configuration Register 0.
0052h R/W CONFIG1 Configuration Register 1.
0053H - - Reserved.
0054h-0057h R /W TimerInt Timer Interrupt Register.

Once having written a non-zero value to this register, the Timeout

bit of the ISR register will be set whenever the TCTR reaches that

value. The Timeout bit will never be set whilst the TimerInt register

is zero.
0058h R/W MSR Media Status Register.
0059h R/W CONFIG3 Configuration register 3.
005Ah R/W CONFIG4 Configuration register 4.
005Bh - - Reserved.
005Ch-005Dh R/W MULINT Multiple Interrupt Select.
005Eh R RERID PCI Revision ID = 10h.
005Fh - - Reserved.
0060h-0061h R TSAD Transmit Status of All Descriptors.
0062h-0063h R/W BMCR Basic Mode Control Register.
0064h-0065h R BMSR Basic Mode Status Register.
0066h-0067h R/W ANAR Auto-Negotiation Advertisement Register.
0068h-0069h R ANLPAR Auto-Negotiation Link Partner Register.
006Ah-006Bh R ANER Auto-Negotiation Expansion Register.
006Ch-006Dh R DIS Disconnect Counter.
006Eh-006Fh R FCSC False Carrier Sense Counter.
0070h-0071h R/W NWAYTR N-way Test Register.
0072h-0073h R REC RX_ER Counter.
0074h-0075h R/W CSCR CS Configuration Register.
0076-0077h - - Reserved.
0078h-007Bh R/W PHY1_PARM PHY Parameter 1.
007Ch-007Fh R/W TW_PARM Twister Parameter.
0080h R/W PHY2_PARM PHY Parameter 2.
0081-0083h - - Reserved.
0084h R/W CRC0 Power Management CRC register 0 for wakeup frame 0.
0085h R/W CRC1 Power Management CRC register 1 for wakeup frame 1.
0086h R/W CRC2 Power Management CRC register 2 for wakeup frame 2.
0087h R/W CRC3 Power Management CRC register 3 for wakeup frame 3.
0088h R/W CRC4 Power Management CRC register 4 for wakeup frame 4.

Single-Chip Fast Ethernet Controller 11 Track ID: JATR-1076-21 Rev. 1.06

RTL8100C & RTL8100CL

Datasheet

Offset R/W Tag Description

0089h R/W CRC5 Power Management CRC register 5 for wakeup frame 5.
008Ah R/W CRC6 Power Management CRC register 6 for wakeup frame 6.
008Bh R/W CRC7 Power Management CRC register 7 for wakeup frame 7.
008Ch–0093h R/W Wakeup0 Power Management Wakeup frame 0 (64-bit).
0094h–009Bh R/W Wakeup1 Power Management Wakeup frame 1 (64-bit).
009Ch–00A3h R/W Wakeup2 Power Management Wakeup frame 2 (64-bit).
00A4h–00ABh R/W Wakeup3 Power Management Wakeup frame 3 (64-bit).
00ACh–00B3h R/W Wakeup4 Power Management Wakeup frame 4 (64-bit).
00B4h–00BBh R/W Wakeup5 Power Management Wakeup frame 5 (64-bit).
00BCh–00C3h R/W Wakeup6 Power Management Wakeup frame 6 (64-bit).
00C4h–00CBh R/W Wakeup7 Power Management Wakeup frame 7 (64-bit).
00CCh R/W LSBCRC0 LSB of the mask byte of wakeup frame 0 within offset 12 to 75.
00CDh R/W LSBCRC1 LSB of the mask byte of wakeup frame 1 within offset 12 to 75.
00CEh R/W LSBCRC2 LSB of the mask byte of wakeup frame 2 within offset 12 to 75.
00CFh R/W LSBCRC3 LSB of the mask byte of wakeup frame 3 within offset 12 to 75.
00D0h R/W LSBCRC4 LSB of the mask byte of wakeup frame 4 within offset 12 to 75.
00D1h R/W LSBCRC5 LSB of the mask byte of wakeup frame 5 within offset 12 to 75.
00D2h R/W LSBCRC6 LSB of the mask byte of wakeup frame 6 within offset 12 to 75.
00D3h R/W LSBCRC7 LSB of the mask byte of wakeup frame 7 within offset 12 to 75.
00D4h-00D7h - - Reserved.
00D8h R/W Config5 Configuration register 5.
00D9h-00FFh - - Reserved.

5.9. Receive Status Register in RX Packet Header

Table 9. Receive Status Register in RX Packet Header

Bit R/W Symbol Description

15 R MAR Multicast Address Received.

This bit set to 1 indicates that a multicast packet has been received.

14 R PAM Physical Address Matched.

This bit set to 1 indicates that the destination address of this packet
matches the value written in ID registers.

13 R BAR Broadcast Address Received.

This bit set to 1 indicates that a broadcast packet is received. BAR,
MAR bit will not be set simultaneously.

12-6 - - Reserved.

5 R ISE Invalid Symbol Error (100Base-TX only).

This bit set to 1 indicates that an invalid symbol was encountered during
the reception of this packet.

4 R RUNT Runt Packet Received.

This bit set to 1 indicates that the received packet length is smaller than
64 bytes ( i.e. media header + data + CRC < 64 bytes )

3 R LONG Long Packet.

This bit set to 1 indicates that the size of the received packet exceeds
4k bytes.

Single-Chip Fast Ethernet Controller 12 Track ID: JATR-1076-21 Rev. 1.06

RTL8100C & RTL8100CL

Datasheet

Bit R/W Symbol Description

2 R CRC Cyclic Redundancy Check (CRC) Error.

When set, indicates that a CRC error occurred on the received
packet.

1 R FAE Frame Alignment Error.

When set, indicates that a frame alignment error occurred on this
received packet.

0 R ROK Receive OK.

When set, indicates that a good packet was received.

5.10. Transmit Status Register
(TSD0-3)(Offset 0010h-001Fh, R/W)

The read-only bits (CRS, TABT, OWC, CDH, NCC3-0, TOK, TUN) will be cleared by the RTL8100C(L)
when the Transmit Byte Count (bits 12-0) in the corresponding Tx descriptor is written. It is not affected
when software writes to these bits. These registers are only permitted to be written via double-word access.
After a software reset, all bits except OWN bit are reset to 0.

Table 10. Transmit Status Register

Bit R/W Symbol Description

31 R CRS Carrier Sense Lost.

This bit is set to 1 when the carrier is lost during transmission of a
packet.

30 R TABT Transmit Abort.

This bit is set to 1 if the transmission of a packet was aborted. This bit
is read only, writing to this bit is not affected.

29 R OWC Out of Window Collision.

This bit is set to 1 if the RTL8100C(L) encountered an ‘out of window’
collision during the transmission of a packet.

28 R CDH CD HeartBeat.

The NIC watches for a collision signal (i.e., CD Heartbeat signal)
during the first 6.4µs of the InterFrame Gap following a
transmission. This bit is set if the transceiver fails to send this signal.

This bit is cleared in 100Mbps mode.

27-24 R NCC3-0 Number of Collision Count.

Indicates the number of collisions encountered during the

transmission of a packet.
23-22 - - Reserved.
21-16 R/W ERTXTH5-0 Early Tx Threshold.

Specifies the threshold level in the Tx FIFO to begin the

transmission. When the byte count of the data in the Tx FIFO reaches

this level, (or the FIFO contains at least one complete packet) the

RTL8100C(L) will transmit this packet.

000000 = 8 bytes

These fields count from 000001 to 111111 in units of 32 bytes.

This threshold must be prevented from exceeding 2k bytes.

Single-Chip Fast Ethernet Controller 13 Track ID: JATR-1076-21 Rev. 1.06

RTL8100C & RTL8100CL

Datasheet

Bit R/W Symbol Description

15 R TOK Transmit OK.

Set to 1 indicates that the transmission of a packet was completed

successfully and no transmit underrun has occurred.

14 R TUN Transmit FIFO Underrun.

Set to 1 if the Tx FIFO was exhausted during the transmission of a

packet. The RTL8100C(L) can re-transfer data if the Tx FIFO

underruns. That is, when TSD<TUN>=1, TSD<TOK>=0 and

ISR<TOK>=1 (or ISR<TER>=1).

13 R/W OWN OWN.

The RTL8100C(L) sets this bit to 1 when the Tx DMA operation of

this descriptor has completed. The driver must set this bit to 0 when

the Transmit Byte Count (bits 0-12) is written. The default value is 1.

12-0 R/W SIZE Descriptor Size.

The total size in bytes of the data in this descriptor. If the packet

length is more than 1792 bytes (0700h), the Tx queue will be invalid,

i.e. the next descriptor will be written only after the OWN bit of that

long packet’s descriptor has been set.

5.11. ERSR: Early RX Status Register (Offset 0036h, R)

Table 11. ERSR: Early RX Status Register

Bit R/W Symbol Description

7-4 - - Reserved.

3 R ERGood Early Rx Good packet.

This bit is set whenever a packet is completely received and the

packet is good. Writing a 1 to this bit will clear it.

2 R ERBad Early Rx Bad packet.

This bit is set whenever a packet is completely received and the

packet is bad. Writing a 1 to this bit will clear it.

1 R EROVW Early Rx OverWrite.

This bit is set when the RTL8100C(L)’s local address pointer is equal

to CAPR. In Early Mode, this is different from buffer overflow. It

happens when the RTL8100C(L) detects an Rx error and wants to fill

another packet data from the beginning address of that error packet.

Writing a 1 to this bit will clear it.

0 R EROK Early Rx OK.

The power-on value is 0. It is set when the Rx byte count of the

arriving packet exceeds the Rx threshold. After the whole packet is

received, the RTL8100C(L) will set ROK or RER in ISR and clear

this bit simultaneously. Setting this bit will invoke an ROK interrupt.

Single-Chip Fast Ethernet Controller 14 Track ID: JATR-1076-21 Rev. 1.06

RTL8100C & RTL8100CL

Datasheet

5.12. Command Register (Offset 0037h, R/W)

This register is used for issuing commands to the RTL8100C(L). These commands are issued by setting the
corresponding bits for the function. A global software reset along with individual reset and enable/disable for
transmitter and receiver are provided here.

Table 12. Command Register

Bit R/W Symbol Description

7-5 - - Reserved.

4 R/W RST Reset.

Setting to 1 forces the RTL8100C(L) to a software reset state which

disables the transmitter and receiver, reinitializes the FIFOs, resets

the system buffer pointer to the initial value (Tx buffer is at TSAD0,

Rx buffer is empty). The values of IDR0-5 and MAR0-7 and PCI

configuration space will have no changes. This bit is 1 during the

reset operation, and is cleared to 0 by the RTL8100C(L) when the

reset operation is complete.

3 R/W RE Receiver Enable.

When set to 1, makes the idle receive state machine active. This bit

will read back as a 1 whenever the receive state machine is active.

After initial power-up, software must ensure that the receiver has

completely reset before setting this bit. This bit will be reset after PCI

reset deassertion.

2 R/W TE Transmitter Enable.

When set to 1, and the transmit state machine is idle, then the transmit

state machine becomes active. This bit will read back as a 1 whenever

the transmit state machine is active. After initial power-up, software

must ensure that the transmitter has completely reset before setting

this bit. This bit will be reset after PCI reset deassertion.

1 - - Reserved.
0 R BUFE Buffer Empty.

RX Buffer Empty. There are no packets stored in the RX buffer ring.

5.13. Interrupt Mask Register (Offset 003Ch-003Dh, R/W)

This register masks the interrupts that can be generated from the Interrupt Status Register. A hardware reset
will clear all mask bits. Setting a mask bit allows the corresponding bit in the Interrupt Status Register to
cause an interrupt. The Interrupt Status Register bits are always set to 1 if the condition is present,
regardless of the state of the corresponding mask bit.

Table 13. Interrupt Mask Register

Bit R/W Symbol Description

15 R/W SERR System Error Interrupt.

1: Enable

0: Disable

14 R/W TimeOut Time Out Interrupt.

1: Enable

0: Disable

Single-Chip Fast Ethernet Controller 15 Track ID: JATR-1076-21 Rev. 1.06