Realtek ALC203, ALC203-LF Schematics
ALC203
ALC203-LF
TWO-CHANNEL AC’97 2.3 AUDIO CODEC
DATASHEET
Rev. 1.6
28 April 2006
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
ALC203 DataSheet
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technical inaccuracies or typographical errors.
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CONFIDENTIALITY
This document is confidential and should not be provided to a third-party without the permission of Realtek
Semiconductor Corporation.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision Release Date
Summary
1.00 2003/06/10 First release.
1.10 2003/05/30 1.Pin-45 is re-defined as a Jack-Detect (JD0).
1.20 2003/08/06 1.Digital data path in Section 3-2.
1.30 2003/10/24 Add ordering information.
1.40 2005/03/14 Add lead (Pb)-free and version package identification
information on page 4 and on page 48.
1.50 2005/12/05 Update section 6.1.12 MX1A Record Select, page 12.
Update section 12. Ordering Information, page 48.
1.60 2006/04/28 Add a note to, and change Susceptibility Voltage data in
section 7.1.1 Absolute Maximum Ratings, page 27.
Two-Channel AC’97 2.3 Audio Codec Rev1.6
ii
ALC203 DataSheet
Table of Contents
1. GENERAL DESCRIPTION .................................................................................................................................................. 1
2. FEATURES ............................................................................................................................................................................. 1
3. BLOCK DIAGRAM ............................................................................................................................................................... 2
3.1 ANALOG MIXER BLOCK ....................................................................................................................................................... 2
3.2 DIGITAL DATA PATH............................................................................................................................................................ 3
4. PIN ASSIGNMENTS.............................................................................................................................................................. 4
4.1 LEAD (PB)-FREE PACKAGE AND VERSION IDENTIFICATION ................................................................................................. 4
5. PIN DESCRIPTION............................................................................................................................................................... 5
5.1 DIGITAL I/O PINS ................................................................................................................................................................. 5
5.2 ANALOG I/O PINS ................................................................................................................................................................ 6
5.3 FILTER/REFERENCE/NC ....................................................................................................................................................... 6
5.4 POWER/GROUND .................................................................................................................................................................. 6
6. REGISTERS............................................................................................................................................................................ 7
6.1 MIXER REGISTERS................................................................................................................................................................ 7
6.1.1 MX00 Reset .................................................................................................................................................................. 8
6.1.2 MX02 Master Volume .................................................................................................................................................. 8
6.1.3 MX04 Headphone .......................................................................................................................................................... 8
6.1.4 MX06 MONO_OUT Volume........................................................................................................................................ 9
6.1.5 MX0A PC BEEP Volume ............................................................................................................................................. 9
6.1.6 MX0C PHONE Volume................................................................................................................................................ 9
6.1.7 MX0E MIC Volume.................................................................................................................................................... 10
6.1.8 MX10 LINE_IN Volume............................................................................................................................................. 10
6.1.9 MX12 CD Volume ...................................................................................................................................................... 10
6.1.10 MX16 AUX Volume.................................................................................................................................................. 11
6.1.11 MX18 PCM_OUT Volume ....................................................................................................................................... 11
6.1.12 MX1A Record Select ................................................................................................................................................ 12
6.1.13 MX1C Record Gain for Stereo ADC........................................................................................................................ 12
6.1.14 MX1E Record Gain for MIC ADC........................................................................................................................... 13
6.1.15 MX20 General Purpose Register ............................................................................................................................. 13
6.1.16 MX22 3D Control .................................................................................................................................................... 13
6.1.17 MX24 Audio interrupt and Paging........................................................................................................................... 14
6.1.18 MX26 Powerdown Control/Status ........................................................................................................................... 15
6.1.19 MX28 Extended Audio ID ........................................................................................................................................ 16
6.1.20 MX2A Extended Audio Status and Control,................................................................................................................ 17
6.1.21 MX2C PCM DAC Rate ............................................................................................................................................ 18
6.1.22 MX32 PCM ADC Rate ............................................................................................................................................. 18
6.1.23 MX3A S/PDIF Out Channel Status/Control ............................................................................................................... 19
6.2 VENDOR DEFINED REGISTERS (PAGE-00H)........................................................................................................................ 20
6.2.1 Page -0h, MX60 S/PDIF In Status [15:0] ................................................................................................................. 20
6.2.2 Page -0h, MX62 S/PDIF In Status [29:15] ............................................................................................................... 20
6.2.3 Page -0h, MX6A Data Flow Control ......................................................................................................................... 20
6.3 DISCOVERY DESCRIPTOR (PAGE ID-01H) .......................................................................................................................... 21
6.3.1 Page -1h, MX62 PCI Sub System ID.......................................................................................................................... 21
6.3.2 Page -1h, MX64 PCI Sub Vendor ID......................................................................................................................... 21
6.3.3 Page -1h, MX66 Sense Function Select ..................................................................................................................... 22
6.3.4 Page -1h, MX68 Sense Function................................................................................................................................ 22
6.3.5 Page -1h, MX6A Sense Detail.................................................................................................................................... 23
6.4 EXTENSION REGISTERS ...................................................................................................................................................... 24
6.4.1 MX76 GPIO & Interrupt Setup.................................................................................................................................. 24
Two-Channel AC’97 2.3 Audio Codec Rev1.6
iii
ALC203 DataSheet
6.4.2 MX78 GPIO & Interrupt Status................................................................................................................................. 25
6.4.3 MX7A Miscellaneous Control.................................................................................................................................... 26
6.4.4 MX7C Vendor ID1 ..................................................................................................................................................... 26
6.4.5 MX7E Vendor ID2 ..................................................................................................................................................... 26
7. ELECTRICAL CHARACTERISTICS .............................................................................................................................. 27
7.1 DC CHARACTERISTICS ....................................................................................................................................................... 27
7.1.1 Absolute Maximum Ratings ....................................................................................................................................... 27
7.1.2 Threshold Hold Voltage............................................................................................................................................. 27
7.1.3 Digital Filter Characteristics..................................................................................................................................... 27
7.1.4 S/PDIF output Characteristics................................................................................................................................... 28
7.2 AC TIMING CHARACTERISTICS .......................................................................................................................................... 28
7.2.1 Cold Reset .................................................................................................................................................................. 28
7.2.2 Warm Reset ................................................................................................................................................................ 28
7.2.3 AC-Link Clocks .......................................................................................................................................................... 29
7.2.4 Data Output and Input Timing................................................................................................................................... 29
7.2.5 Signal Rise and Fall Timing....................................................................................................................................... 30
7.2.6 AC-Link Low Power Mode Timing ............................................................................................................................ 30
7.2.7 ATE Test Mode........................................................................................................................................................... 31
7.2.8 AC-Link IO Pin Capacitance and Loading................................................................................................................ 31
7.2.9 SPDIF Output ............................................................................................................................................................ 31
8. ANALOG PERFORMANCE CHARACTERISTICS....................................................................................................... 32
9. DESIGN SUGGESTIONS.................................................................................................................................................... 34
9.1 CLOCKING.......................................................................................................................................................................... 34
9.2 AC-LINK............................................................................................................................................................................ 35
9.3 RESET ................................................................................................................................................................................ 36
9.4 CD INPUT........................................................................................................................................................................... 36
9.5 ODD ADDRESSED REGISTER ACCESS ................................................................................................................................. 36
9.6 POWER-DOWN MODE ......................................................................................................................................................... 36
9.7 TEST MODE........................................................................................................................................................................ 36
9.7.1 ATE In Circuit Test Mode .......................................................................................................................................... 36
9.7.2 Vendor Specific Test Mode ........................................................................................................................................ 36
9.8 JACK-DETECT FUNCTION & ASSIGNMENT FOR JACK ......................................................................................................... 37
9.9 DC VOLTAGE VOLUME CONTROL...................................................................................................................................... 39
9.10 POWER OFF CD FUNCTION ........................................................................................................................................... 40
9.11 GPIO SMART VOLUME CONTROL .................................................................................................................................... 41
10. APPLICATION CIRCUIT ................................................................................................................................................ 42
11. MECHANICAL DIMENSIONS........................................................................................................................................ 45
12. ORDERING INFORMATION.......................................................................................................................................... 48
Two-Channel AC’97 2.3 Audio Codec Rev1.6
iv
ALC203 DataSheet
1. General Description
The ALC203 AC'97 codec is a 20-bit DAC and 18-bit ADC full duplex AC'97 2.3 compatible stereo audio codec designed for PC
multimedia systems, including host/soft audio and AMR/CNR based designs. The ALC203 incorporates proprietary converter
technology to achieve a high SNR, greater than 100 dB, sensing logic for device reporting, and Universal Audio Jack® to improve
user experience.
The ALC203 supports multiple CODEC extensions with independent variable sampling rates and built-in 3D effects. The ALC203
CODEC provides two pairs of stereo outputs with independent volume controls, a mono output, and multiple stereo and mono
inputs, along with flexible mixing, gain and mute functions to provide a complete integrated audio solution for PCs. The circuitry of
the ALC203 codec operates from a +3.3V digital power and +5V analog power supply with EAPD (External Amplifier Power
Down) control for use in notebook and PC applications. An integrated 14.318MÆ24.576MHz PLL generate required clock to
eliminate the need for external crystal. Built in PCBEEP generator to save buzzer on board.
The ALC203 integrates a 50mW/20Ω headset audio amplifier into the codec, saving BOM costs. The ALC203 also supports the
SPDIF out function, compliant with AC'97 2.3, which offers easy connection of PCs to consumer electronic products, such as AC3
decoder/speaker and mini disk devices. The ALC203 codec supports host/soft audio from Intel ICHx chipsets as well as audio
controller based VIA/SIS/ALI/AMD/nVIDIA/ATI chipsets.
Bundled Windows series drivers (WinXP/ME/2000/98/NT), EAX/ Direct Sound 3D/ I3DL2/ A3D compatible sound effect utilities
(supporting Karaoke, 26-types of environment sound emulation, 10-band equalizer), HRTF 3D positional audio and Sensaura™ 3D
(optional) provide an excellent entertainment package and game experience for PC users.
2. Features
z Single chip with high S/N ratio (>100 dB)
z Meets performance requirements for audio on
PC99/2001 systems
z Meets Microsoft WHQL/WLP 2.0 audio
requirements
z 20-bit DAC and 18-bit ADC resolution
z 18-bit Stereo full-duplex CODEC with
independent and variable sampling rate
z Compliant with AC’97 2.3 specifications
-LINE/HP-OUT, MIC-IN and LINE-IN sensing
-14.318MHz-Æ24.576MHz PLL saves crystal
-12.288MHz BITCLK input can be consumed
-Integrated PCBEEP generator to save buzzer
-Interrupt capability
-Page registers and Analog Plug&Play
z Support of S/PDIF out is fully compliant with
AC’97 rev2.3 specifications
z Three analog line-level stereo inputs with 5-bit
volume control: LINE_IN, CD, AUX
z High quality differential CD input
z Two analog line-level mono input: PCBEEP,
PHONE-IN
z Supports double sampling rate (96KHz) of DVD
audio playback
z Two software selectable MIC inputs
z +6/12/20/30dB boost preamplifier for MIC input
z Stereo output with 6-bit volume control
z Mono output with 5-bit volume control
z Headphone output with 50mW/20Ω amplifier
z 3D Stereo Enhancement
z Multiple CODEC extension capability
z External Amplifier Power Down (EAPD)
capability
z Power management and enhanced power saving
features
z Stereo MIC record for AEC/BF application
z DC Voltage volume control
z Auxiliary power to support Power Off CD
z Adjustable VREFOUT control
z 2 GPIO pins with smart GPIO volume control
2 Universal Audio Jack (UAJ)® for front panel
z
z Support 32K/44.1K/48K/96KHz of S/PDIF output
z Support 32K/44.1K/48KHz of S/PDIF input
z Standard 48-Pin LQFP Package
z EAX™ 1.0 & 2.0 compatible
z Direct Sound 3D™ compatible
z A3D™ compatible
z I3DL2 compatible
z HRTF 3D Positional Audio
z Sensaura™ 3D Enhancement (optional)
z 10 Bands of Software Equalizer
z Voice Cancellation and Key Shifting in
KaraOK mode
z AVRack
z Configuration Panel to improve User
Experience
®
Media Player
Two-Channel AC’97 2.3 Audio Codec Rev1.6
1
ALC203 DataSheet
3. Block Diagram
3.1 Analog Mixer Block
HP-OUT
AMP
MX04
HeadPhone
Volume
LINE-OUT
No
Yes
Master
MX02
Volume
1
0*
3D
MONO-OUT
RESET#
Mono
MX6A.14
MX22
Volume
MX06
M
phone
mono mix
stereo mix
ADC
Gain
Record
U
line
mic-L
mic-R
MX1C
X
CD
ALC203
MIC ADC
Record
MX1A
1*
aux
left channel
right channel
Gain
0
MX1E
MX6A.8
MX0A
MX18
DAC output
PC-BEEP
MX0C
MX20.8
0*
MIC1
PHONE
MX0E
Boost
1
1
0*
MIC2
MX10
MX6A.7
LINE-IN
CD-IN
MX12
MX16
Boost
Boost
AUX-IN
0*
1
MX6A.6
mono analog
stereo analog
* : default setting
Analog Mixer Diagram
Two-Channel AC’97 2.3 Audio Codec Rev1.6
2
3.2 Digital Data Path
ALC203 DataSheet
AC-
LINK
SP-In data
SPDIF-In data
20-bi t PCM
Left
1
Right
0
Left
20-bi t SPDIF In
20-bi t SPDIF Out
01
01
SPDIF
Input
1
0
1
DVOL
DVOL
Digital
1
3D
0
Original
ADC
MIC
ADC
DAC
Mixer
Block
Line-In
CD-In
MIC-In
...
SPDIF
0
Output
Di gi tal Stereo
Digital Mono
A nalog St ereo
Analog Mono
A nalog outputs
DVOL : Digital Volume Control
Digital data path diagram
Two-Channel AC’97 2.3 Audio Codec Rev1.6
3
4. Pin Assignments
ALC203 DataSheet
NC
DCVOL
VREFOUT2
DVSS1
AFILT2
DVSS2
BIT-CLK
SDATA-OUT
AFILT1
VREFOUT
ALC203
DVDD2
SDATA-IN
VREF
AVSS1
AVDD1
24
LINE-IN-R
23
LINE-IN-L
22
MIC2
21
MIC1
20
CD-R
19
CD-GND
18
CD-L
JD1
17
16
JD2
AUX-R
15
14
AUX-L
13
PHONE
SYNC
PCBEEP
RESET#
MONO-OUT/VREFOUT3
HP-OUT-L
HP-OUT-R
XTLSEL
SPDIFI /EAPD
AVDD2
NC
AVSS2
GPIO0
GPIO1
JD0
SPDIFO
VAUX
LINE-OUT-L
LINE-OUT-R
36 35 34 33 32 31 30 29 28 27 26 25
37
38
39
40
41
42
43
44
45
46
47
48
LLLLLLL TXXXV
123456789101112
DVDD1
XTL-IN
XTL-OUT
Pin Assignments
4.1 Lead (Pb)-Free Package and Version Identification
Lead (Pb)-free package is indicated by an ‘L’ in the location marked ‘T’ in the figure above. The version number is shown in the
location marked ‘V’.
Two-Channel AC’97 2.3 Audio Codec Rev1.6
4
ALC203 DataSheet
5. Pin Description
In order to reduce pin count, and therefore size and cost, some pins have multiple functions. In those cases, the functions are
separated with a “/” symbol. Refer to the Pin Assignment diagram for a graphical representation.
5.1 Digital I/O Pins
Name Type Pin No Description Characteristic Definition
RESET# I 11 AC'97 H/W reset Schmitt trigger input
XTL-IN I 2 Crystal input pad Crystal: 24.576M/14.318M crystal input
External: 24.576M/14.318M external clock input
XTL-OUT O 3 Crystal output pad Crystal: 24.576M/14.318M crystal output
External: 24.576M/14.318M clock output
SYNC I 10 Sample Sync (48KHz) Schmitt trigger input
BIT-CLK IO 6 Bit clock input/output
(12.288Mhz)
SDATA-OUT I 5 Serial TDM AC97 output CMOS input
SDATA-IN O 8 Serial TDM AC97 input CMOS output
GPIO0 I/O 43 General purpose pin-0.
(Smart volume up)
GPIO1 I/O 44 General purpose pin-1.
(Smart volume down)
XELSEL I 46 Pulled low to use external
14.318MHz clock source
SPDIFI/EAPD O 47 S/PDIF input / External
Amplifier power down
control
SPDIFO O 48 S/PDIF output
CMOS input/output
Internally pulled high by a 50K resistor.
Internally pulled high by a 50K resistor.
CMOS input Vt=0.35Vdd, internally pulled high by a 50K
resistor.
CMOS input / output
Digital output has 12 mA@75Ω driving capability.
Total: 13 Pins
Two-Channel AC’97 2.3 Audio Codec Rev1.6
5
ALC203 DataSheet
5.2 Analog I/O Pins
Name Type Pin No Description Characteristic Definition
PC-BEEP I 12 PC speaker input Analog input (1.6Vrms)
PHONE I 13 Speakerphone input Analog input (1.6Vrms)
AUX-L IO 14 AUX Left channel Analog input/output
AUX-R IO 15 AUX Right channel Analog input/output
JD2 I 16 Jack Detect 2 for UAJ2 Internally pulled high to AVDD by a 50K resistor
JD1 I 17 Jack Detect 1 for UAJ2 Internally pulled high to AVDD by a 50K resistor
JD0 I 45 Jack Detect 0 for MIC Internally pulled high to AVDD by a 50K resistor
CD-L I 18 CD audio Left channel Analog input (1.6Vrms)
CD-GND I 19 CD audio analog GND Analog input
CD-R I 20 CD audio Right channel Analog input (1.6Vrms)
MIC1 I 21 First MIC input Analog input (1.6Vrms)
MIC2 I 22 Second MIC input Analog input (1.6Vrms)
LINE-IN-L I 23 Line input Left channel Analog input (1.6Vrms)
LINE-IN-R I 24 Line input Right channel Analog input (1.6Vrms)
LINE-OUT-L O 35 Line-Out Left channel Analog output w/o amplifier
LINE-OUT-R O 36 Line-Out Right channel Analog output w/o amplifier
HP-OUT-L IO 39 Headphone Out Left
channel
HP-OUT-R IO 41 Headphone Out Left
channel
MONO-OUT/
VREFOUT3
O 37 Speaker Phone output /
Third Ref. voltage out
ALC203: Analog output with amplifier / Analog input
ALC203: Analog output with amplifier / Analog input
Analog output / Third reference voltage output
(2.5V/4.0V)
Total: 18 Pins
5.3 Filter/Reference/NC
Name Type Pin No Description Characteristic Definition
VREF - 27 Reference voltage 1uf capacitor to analog ground
VREFOUT O 28 Ref. voltage out Analog DC voltage output (2.5V / 4.0V)
AFILT1 - 29 ADC anti-aliasing filter 1000pf capacitor to analog ground.
AFILT2 - 30 ADC anti-aliasing filter 1000pf capacitor to analog ground.
NC - 31 Not Connection
DC VOL I 32 DC Voltage Volume
Control
VREFOUT2 O 33 Secondary Ref. voltage out Analog DC voltage output (2.5V / 4.0V)
VAUX I 34 Auxiliary Power to keep CD
and amplifier turned on.
NC - 40 Not Connection
Analog Input (AGND~AVDD)
+5V analog stand-by power
Total: 9 Pins
5.4 Power/Ground
Name Type Pin No Description Characteristic Definition
AVDD1 I 25 Analog VDD
AVDD2 I 38 Analog VDD
AVSS1 I 26 Analog GND
AVSS2 I 42 Analog GND
DVDD1 I 1 Digital VDD (3.3V)
DVDD2 I 9 Digital VDD (3.3V)
DVSS1 I 4 Digital GND
DVSS2 I 7 Digital GND
Total: 8 Pins
Two-Channel AC’97 2.3 Audio Codec Rev1.6
6
ALC203 DataSheet
6. Registers
6.1 Mixer Registers
Access to registers with an odd number will return a 0. Reading unimplemented registers will also return a 0. X=Reserved bit.
REG.
(HEX)
00h Reset X SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0190h
02h Master
04h Headphone
06h Mono-Out
0Ah PC_BEEP
0Ch PHONE
0Eh MIC Volume Mute X X X X X BGO1 BGO0 X BC X MI4 MI3 MI2 MI1 MI0 8008h
10h Line-In
12h CD Volume Mute X X CL4 CL3 CL2 CL1 CL0 RM* X X CR4 CR3 CR2 CR1 CR0 8808h
16h Aux Volume Mute X X AL4 AL3 AL2 AL1 AL0 RM* X X AR4 AR3 AR2 AR1 AR0 8808h
18h PCM Out
1Ah Record Select X X X X X LRS2 LRS1 LRS0 X X X X X RRS2 RRS1 RRS0 0000h
1Ch ADC
1Eh MIC ADC
20h General
22h 3D Control X X X X X X X X X X X X X DP2 DP1 DP0 0000h
24h Audio Int. &
26h Power Down
28h Extended
2Ah Extended
2Ch PCM front Out
32h PCM Input
34h MIC Input
3Ah S/PDIF Ctl V DRS SPSR1 SPSR0 L CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COPY /AUD
60h/
6Eh
76h GPIO Setup 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h
78h GPIO Status 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h
7Ch Vendor ID1 F7 F6 F5 F4 F3 F2 F1 F0 S7 S6 S5 S4 S3 S2 S1 S0 414Ch
7Eh Vendor ID2 T7 T6 T5 T4 T3 T2 T1 T0 DEV7 DEV6 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0 4770h
NAME D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Volume
volume
Volume
Volume
Volume
Volume
Volume
Record Gain
Record Gain
Purpose
Paging
Ctrl/Status
Audio ID
Audio Status
Sample Rate
Sample Rate
Sample Rate
Vendor Define 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h
Mute X ML5 ML4 ML3 ML2 ML1 ML0 RM* X MR5 MR4 MR3 MR2 MR1 MR0 8000h
Mute X HPL5 HPL4 HPL3 HPL2 HPL1 HPL0 RM* X HPR5 HPR4 HPR3 HPR2 HPR1 HPR0 8000h
Mute X X X X X X X X X X MM4 MM3 MM2 MM1 MM0 8000h
Mute X X F7 F6 F5 F4 F3 F2 F1 F0 PB3 PB2 PB1 PB0 X 8000h
Mute X X X X X X X X X X PH4 PH3 PH2 PH1 PH0 8008h
Mute X X NL4 NL3 NL2 NL1 NL0 RM* X X NR4 NR3 NR2 NR1 NR0 8808h
Mute X X PL4 PL3 PL2 PL1 PL0 RM* X X PR4 PR3 PR2 PR1 PR0 8808h
Mute X X X LRG3 LRG2 LRG1 LRG0 X X X X RRG3 RRG2 RRG1 RRG0 8000h
Mute X X X LMR
POP X 3D X DRSS1 DRSS0 MIX MS LBK X X X X X X X 0400h
I4 I3 I2 I1 I0 X X X X X X X PG3 PG2 PG1 PG0 0000h
EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 X X X X REF ANL DAC ADC 000Fh
ID1 ID0 X X REV1 REV0 AMAP X X X X X X SPDIF DRA VRA 0A07h
X X X X X SPCV X X X X SPSA1 SPSA0 X SPDIF DRA VRA 0000h
FSR
FSR14 FSR13 FSR12 FSR11 FSR10 FSR9 FSR8 FSR7 FSR6 FSR5 FSR4 FSR3 FSR2 FSR1 FSR0 BB80h
15
ISR
ISR
ISR
15
MSR
15
14
MSR
14
13
MSR
13
ISR
12
MSR
12
G3
ISR
11
MSR
11
LMR
LMR
LMR
G2
G1
ISR
ISR 9 ISR 8 ISR 7 ISR 6 ISR 5 ISR 4 ISR 3 ISR 2 ISR 1 ISR 0 BB80h
10
MSR
MSR9 MSR8 MSR7 MSR6 MSR5 MSR4 MSR 3 MSR 2 MSR 1 MSR0 BB80h
10
X X X X RMR
G0
G3
RMR
G2
RMR
G1
IO
DEFAUL
T
RMR
8000h
G0
PRO 2000h
Two-Channel AC’97 2.3 Audio Codec Rev1.6
7
ALC203 DataSheet
6.1.1 MX00 Reset
Default: 0190h
Writing any value to this register will start a register reset, and causes all of the registers to revert to their default values, then the
written data is ignored. Reading this register returns the ID code of the specific part.
Bit Type Function
15
14:10 R Return 00000b
9 R Read as 0 (No support for 20-bit ADC)
8 R Read as 1 (Support for 18-bit ADC)
7 R Read as 1 (Support for 20-bit DAC)
6 R Read as 0 (No support for 18-bit DAC)
5 R Read as 0 (No support for Loudness)
4 R Read as 1 (Headphone output support)
3 R Read as 0 (No simulated stereo; for analog 3D block use)
2 R Read as 0 (No Bass & Treble Control)
1 R
0 R Read as 0 (No dedicated MIC PCM input)
Reserved
Reserved, Read as 0
6.1.2 MX02 Master Volume
Default: 8000h
These registers control the overall volume level of the output functions. Each step on the left and right channels corresponds to
a 1.5dB increase/decrease in volume.
Bit Type Function
15 R/W
14
13:8 R/W
7:6
5:0 R/W
n For MRV/MLV: 00h 0 dB attenuation
3Fh 94.5 dB attenuation
Mute Control 0: Normal 1: Mute (-∞ dB)
Reserved
Master Left Volume (MLV[5:0]) in 1.5 dB steps
Reserved
Master Right Volume (MRV[5:0]) in 1.5 dB steps
6.1.3 MX04 Headphone
Default: 8000h
Register 04h controls the headphone (ALC203) output volume. Each step in bits 5:0 and 13:8 corresponds to a 1.5dB
increase/decrease in volume, allowing 63 levels of volume, from 000000 to 111111.
Bit Type Function
15 R/W
14
13:8 R/W
7:6
5:0 R/W
n For HPR/HPL: 00h 0 dB attenuation
3Fh 94.5 dB attenuation
Mute Control 0: Normal 1: Mute (-∞ dB)
Reserved
Headphone/True Line Output Left Volume (HPL[5:0]) in 1.5 dB steps
Reserved
Headphone/True Line Output Right Volume (HPR[5:0]) in 1.5 dB steps
Two-Channel AC’97 2.3 Audio Codec Rev1.6
8
ALC203 DataSheet
6.1.4 MX06 MONO_OUT Volume
Default: 8000h
Register 06h controls the mono volume output. Mono output is the same data sent on all output channels. Each step in bits 4:0
corresponds to a 1.5dB increase/decrease in volume, allowing 32 levels of volume from 00000 to 11111.
Bit Type Function
15 R/W
14:5
4:0 R/W
n For MMV: 00h 0 dB attenuation
1Fh 46.5 dB attenuation
Mute Control 0: Normal 1: Mute (-∞ dB)
Reserved
Mono Master Volume (MMV[4:0]) in 1.5 dB steps
6.1.5 MX0A PC BEEP Volume
Default: 8000h
This register controls the input volume for the PC beep signal. Each step in bits 4:1 corresponds to a 3dB increase/decrease in
volume. 16 levels of volume are available, from 0000 to 1111.
The purpose of this register is to allow the PC Beep signals to pass through the ALC203, eliminating the need for an external system
speaker/buzzer. The PC BEEP pin is directly routed (internally hardwired) to the LINE-OUTL & R pins. If the PC speaker/buzzer is
eliminated, it is recommended to connect the external speakers at all times so the POST codes can be heard during reset.
Bit Type Function
15 R/W
14:13
12:5 R/W
4:1 R/W
0
n For PBV: 00h 0 dB attenuation
0Fh 45 dB attenuation
Mute Control 0: Normal 1: Mute (-∞ dB)
Reserved
Internal PCBEEP Frequency, F[7:0]
The internal PCBEEP frequency is the result of dividing the 48KHz clock by 4 times the number specified
in F[7:0].
The lowest tone is 48KHz/(255*4)=47Hz.
The highest tone is 48KHz/(1*4)=12KHz.
A value of 00h in F[7:0] disables internal PCBEEP generator and allows external PCBEEP input.
PC Beep Volume (PBV[3:0]) in 3 dB steps
Reserved
6.1.6 MX0C PHONE Volume
Default: 8008h
Register 0Ch controls the telephone input volume for software modem applications. Because software modem applications may
not have a speaker, the CODEC can offer a speaker-out service. Each step in bits 4:0 corresponds to a 1.5dB increase/decrease in
volume, allowing 32 levels of volume, from 00000 to 11111.
Bit Type Function
15 R/W
14:5
4:0 R/W
n For PV: 00h +12 dB Gain
08h 0dB gain
1Fh -34.5dB Gain
Two-Channel AC’97 2.3 Audio Codec Rev1.6
Mute Control 0: Normal 1: Mute (-∞ dB)
Reserved
Phone Volume (PV[4:0]) in 1.5 dB steps
9
ALC203 DataSheet
6.1.7 MX0E MIC Volume
Default: 8008h
Register 0Eh controls the microphone input volume. Each step in bits 4:0 corresponds to a 1.5dB increase/decrease in volume,
allowing 32 levels of volume, from 00000 to 11111. Bit 6 enables/disables a boost in volume to a magnification based on bits 9:8.
Bit Type Function
15 R/W
14:10
9:8 R/W
7
6 R/W
5
4:0 R/W
n For MV: 00h +12 dB Gain
08h 0dB gain
1Fh -34.5dB Gain
o If 29.5dB boost gain is selected, input resistor can be reduced to save area of feedback resistor.
Mute Control 0: Normal 1: Mute (-∞ dB)
Reserved
Boost Gain Option (BGO)
00: 20 dB 01: 6 dB 10: 12 dB 11: 29.5 dB (V=30*Vmic-in)
Reserved
Boost Control (BC)
0: Disable 1: Enable Boost
Reserved
Mic Volume (MV[4:0]) in 1.5 dB steps
6.1.8 MX10 LINE_IN Volume
Default: 8808h
Register 10h controls the LINE_IN input volume. Each step in bits 4:0 corresponds to a 1.5dB increase/decrease in volume for
the right channel, allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 corresponds to a 1.5dB
increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111.
Bit Type Function
15 R/W
14:13
12:8 R/W
7:5
4:0 R/W
n For NLV/NRV: 00h +12 dB Gain
08h 0dB gain
1Fh -34.5dB Gain
Mute Control 0: Normal 1: Mute (-∞ dB)
Reserved
Line-In Left Volume (NLV[4:0]) in 1.5 dB steps
Reserved
Line-In Right Volume (NRV[4:0]) in 1.5 dB steps
6.1.9 MX12 CD Volume
Default: 8808h
Register 12h controls the CD input volume. Each step in bits 4:0 corresponds to a 1.5dB increase/decrease in volume for the right
channel, allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 corresponds to a 1.5dB increase/decrease in
volume for the left channel, allowing 32 levels of volume, from 00000 to 11111.
Bit Type Function
15 R/W
14:13
12:8 R/W
7:5
4:0 R/W
n For CLV/CRV: 00h +12 dB Gain
08h 0dB gain
1Fh -34.5dB Gain
Mute Control 0: Normal 1: Mute (-∞ dB)
Reserved
CD Left Volume (CLV[4:0]) in 1.5 dB steps
Reserved
CD Right Volume (CRV[4:0]) in 1.5 dB steps
Two-Channel AC’97 2.3 Audio Codec Rev1.6
10
ALC203 DataSheet
6.1.10 MX16 AUX Volume
Default: 8808h
Register 16h controls the auxiliary input volume. Each step in bits 4:0 corresponds to a 1.5dB increase/decrease in volume for
the right channel, allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 corresponds to a 1.5dB
increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111.
Bit Type Function
15 R/W
14:13
12:8 R/W
7:5
4:0 R/W
n For ALV/ARV: 00h +12 dB Gain
08h 0dB gain
1Fh -34.5dB Gain
Mute Control 0: Normal 1: Mute (-∞ dB)
Reserved
AUX Left Volume (ALV[4:0]) in 1.5 dB steps
Reserved
AUX Right Volume (ARV[4:0]) in 1.5 dB steps
6.1.11 MX18 PCM_OUT Volume
Default: 8808h
Register 18h controls the PCM_OUT output volume. Each step in bits 4:0 corresponds to a 1.5dB increase/decrease in volume
for the right channel, allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 corresponds to a 1.5dB
increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111.
Bit Type Function
15 R/W
14:13
12:8 R/W
7:5
4:0 R/W
n For PLV/PRV: 00h +12 dB Gain
08h 0dB gain
1Fh -34.5dB Gain
Mute Control 0: Normal 1: Mute (-∞ dB)
Reserved
PCM Volume (PLV[4:0]) in 1.5 dB steps
Reserved
PCM Right Volume (PRV[4:0]) in 1.5 dB steps
Two-Channel AC’97 2.3 Audio Codec Rev1.6
11
ALC203 DataSheet
6.1.12 MX1A Record Select
Default: 0000h
Register 1Ah controls the record input source. Each bit in bits 2:0 selects a recording source for the right channel. Each bit in bits
10:8 selects a recording source for the left channel.
Bit Type Function
15:11
10:8 R/W
7:3
2:0 R/W
n For LRS
o For RRS
Reserved
Left Record Source Select (LRS[2:0])
Reserved
Right Record Source Select (RRS[2:0])
0 MIC
1 CD LEFT
2 Muted
3 AUX LEFT
4 LINE LEFT
5 STEREO MIXER OUTPUT LEFT
6 MONO MIXER OUTPUT
7 PHONE
0 MIC
1 CD RIGHT
2 Muted
3 AUX RIGHT
4 LINE RIGHT
5 STEREO MIXER OUTPUT RIGHT
6 MONO MIXER OUTPUT
7 PHONE
6.1.13 MX1C Record Gain for Stereo ADC
Default: 8000h
Register 1Ch controls the record gain. Each step in bits 3:0 corresponds to a 1.5dB increase/decrease in gain for the right
channel, allowing 16 levels of gain, from 0000 to 1111. Each step in bits 11:8 corresponds to a 1.5dB increase/decrease in gain
for the left channel, allowing 16 levels of gain, from 0000 to 1111.
Bit Type Function
15 R/W
14:12
11:8 R/W
7:4
3:0 R/W
nFor LRG/RRG: 0Fh +22.5dB
Mute Control 0: Normal 1: Mute (-∞ dB)
Reserved
Left Record Gain Select (LRG[3:0]) in 1.5 dB steps
Reserved
Right Record Gain Select (RRG[3:0]) in 1.5 dB steps
00h 0 dB (No Gain)
Two-Channel AC’97 2.3 Audio Codec Rev1.6
12
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