Realistic RadioShack TRC-469 Service Manual

U

TRC-469

•

CUSTOM MANUFACTURED FOR RADIO SHACK M A DIVISION OF TANDY CORPORATION

TABLE OF CONTENTS

1.

SPECIFICATIONS

2.

DISASSEMBLY INSTRUCTIONS
BLOCK DIAGRAM

3.

4.

CIRCUIT DESCRIPTIONS
PLL CIRCUIT
AMC CIRCUIT
RF ATTENUATOR CIRCUIT

5.

ALIGNMENT INSTRUCTIONS

6.

TROUBLE SHOOTING HINTS

7.

IC, TR, DIODE & LED LEAD IDENTIFICATION

8.

IC AND COMPOUND PARTS INTERNAL DIAGRAMS

9.

FLEXIBLE P.C. BOARD(TOP VIEW)

10.

SWITCH P.C. BOARD(ANL, PA-MON-CB)

11.

MAIN P.C. BOARD(TOP VIEW)

12.

MAIN P.C. BOARD(BOTTOM VIEW)

13.

ADDITIONAL PARTS ON THE BOTTOM

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3 4

5

6
7 10
7 9

10

10
11 - 14
14 16

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17

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18

19

19

20

21

22

14.

WIRING DIAGRAM

15.

ELECTRICAL PARTS LIST

16.

MECHANICAL PARTS LIST

17.

SCHEMATIC DIAGRAM

18.

EXPLODED VIEW

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SEPARATE SHEET
SEPARATE SHEET

24 - 32
33'34

23

1. SPECIFICATIONS

GENERAL:

Transmitter/Receiver

Communicating frequencies
Operating voltage

Temperature and Humidity Range
Transmitter/Receiver switching
Antenna

Microphone




Speaker
Size



Weight
Accessories





STANDARD TEST CONDITIONS:











Frequency synthesizing circuit with digital

phase-locked loop

26.965 MHz to 27.405 MHz (all 40 channels)
11-16V DC (positive or negative ground)

-20°C to +60° C and 10% to 90%
Electronic (diode switching)

52 ohm (coaxial connector)



600 ohm Dynamic Type
8 ohm, 2 Watt
2-3/16" x 6-1/4- x

(5.5x 16 x 22.7 cm [HWD])
5 lbs. (approx. ) (2.3 kg)
DC Cord with in-line Fuse, Microphone and

Microphone Hanger and Mounting Brackets



(HWD) (approx.)

Battery supply voltage
Modulation



Audio output power
Audio output load

Antenna impedance









Ambient conditions

Temperature
Humidity





TRANSM ITTER:

Frequency Tolerance 25°C 13.8 V
RF Power Output
AMC Range 50% — 100% Mod

Modulation Frequency Response (-6 dB)

Lower Frequency

a.

Upper Frequency 2500 Hz

b.
Microphone Sensitivity 1 kHz 50% Mod
Modulation Distortion at 1 kHz 80% Mod
RF Power Output Uniformity Ch. to Ch.

Modulation Capability Positive/Negative

RF Power Output at 12.0 V
Battery Drain

at no Modulation

a.

at 80% Modulation .

b.



450 Hz

13.8V

1000 Hz, 30%
500 mW
8 ohm
50 ohm (non-inductive load)

25°C ±5°C
50% to 70%

UNIT

W

dB

dB
dB

mV

W

W

mA
mA

DC

NOMINAL

0.0005
4 (Max.)

36

-

6

-

6

1

3

0.2

95/95

2.7

950

1550

LIMIT

0.003

3.6 — 4.0
30

6 ± 3 dB

­6 ± 3 dB

-

2
8

0.5

80/85

2.2

1200
2000

3

RECEIVER:

(ANL: OUT)



UNIT



NOMINAL



LIMIT

Maximum Sensitivity

Sensitivity for 10 dB S/N
AGC Figure of Merit 50 mV
Overload AGC 50 mV — 1 V

Squelch Sensitivity at Threshold
Squelch Sensitivity at Tight
Adjacent Channel Selectivity

a. at ±10 kHz

Spurious Radiation
Spurious Response Attenuation

a. 455/2 kHz

Image Rejection Ratio

a. -910 kHz

IF Rejection Ratio

a.

10.695 MHz

b.

455 kHz
Cross Modulation
Desensitization (3 dB Desens.)

at 100 pV

Audio Power Output

a.

Maximum

b.

10% THD

Audio Frequency Response (-6 dB)

a.

Lower Freq.

b.

Upper Freq.

THD at 500 mW Audio Output

a.

Input 1 mV 30% Mod
b.
c.

Signal-to-Noise Ratio at 1000 pV
RF Gain Control Range
S-Meter Sensitivity at "S9"

Oscillator Drop-out Voltage

Battery Drain

a.

at no signal
b.

at Max. AF Output

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450 Hz

2500 Hz

50% Mod
80% Mod

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








pV

p

V
dB
dB

p

V

pV

dB
dB

dB

dB

dB
dB

dB

dB

W
W

dB

dB

%
%

%
dB
dB
p V

V

mA
mA

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

0.3

0.5
90

+4

1000

70
80

80

90

90

115

60

60

-6

-6

45
40

100

250
800

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


0.25


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5



4



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2



4



6


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7






0.5
1

80

+6

-2



2

355 — 2820

60

60

60

70

80
90

50

55

4
3

-6 ± 3 dB

-6 ± 3 dB

4
6

8
35
30
50 — 200
10

600

1500

PUBLIC ADDRESS:

Microphone Sensitivity for 4 W

Output Power at 1 kHz

Power Output

Maximum

a.
b.

10% THD

Audio Freq. Response (-6 dB)

a.

Lower Frequency

b.

Upper Frequency

Battery Drain

a.

at no signal

b.

at Max. AF Output

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

450 Hz

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

2500 Hz



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




4

mV

W
W

dB
dB

mA
mA

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




-6

-6

300

1000

4

5
4

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

10

4

3

-6 ± 3 dB

-6 ± 3 dB

700

1500

2. DISASSEMBLY INSTRUCTIONS

Figure 1

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Figure 2



Figure 3

t

TO REMOVE TOP AND BOTTOM COVER
(Figure 1 & 2):

Remove 4 screws from each side and a screw from top.
Remove 2 screws from rear of the chassis. Slide top and

bottom cover toward rear of the chassis and remove.

TO REMOVE FRONT PANEL
(Figure 3):

Remove 2 screws from each side.

Figure 4



Figure 5

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co

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O

0

Ei

<

C7

ce

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4. CIRCUIT DESCRIPTIONS

PLL CIRCUIT:

The PLL circuit used in TRC-469 consists of 7
major parts: Voltage Controlled Oscillator(VCO),
1/N Divider, Phase Detector, Low Pass Filter,

[FVCO[ BY TP-1

12.279: 12.7202

RX

TR22

TX 16.725 — 17.165 MHz [TX. MIXER}

BUFFERI

IC3

V.C.O.



BUFFER

12C1Li

a.

BY TR14

COLLECTOR

RX 16.270-16.710 MI

TR14

TX 16.72517.165 MHI"

[F1I BY TP-3

RX 910 ^ 1,350 kHz

TR15

MIXER

t__

TX 1,365 — 1,805 kHz

Reference Oscillator (10.24 MHz), 1/2048 divider

and Code Converter ROM(Read Only Memory).

[Fstc1)

15.360 MHz

.120 MHz

L19



r

I

1> 

IS Amp

3.8V

3.5V

1.5V

1.2V
CH1

TP2

0

RX = H

TR13

TX/RX

SW

TX = L

IC 4

PIN NO.

WAVE

FORM

IC4

PIN NO.

WAVE

FORM

NOTE:

22

21, 20, 7

+2.8V

+2.8V

+1.4V

RX . 910

—

1,350 kHz

TX = 1,365 — 1,805 kHz

c

.

,_______

10k4

CH

CH 1

H

CH 18

L

t

CH 23

H H

1



CH 40

L L L L

SCOPE WAVE FORMS FOR LEVEL REFERENCE

H = High (3.5V — 5 V)

L = Low (0V — 1V)

PIN NO. 1 through 4,5, & 6 are as in program
input data chart.

,



CH23



CH40

Filter

—

WAVE FORM OF IC 4

18,17

DV

2

18
L

L L

2.4V DC
—2.4V

19

3

1C

L

L

aVDC1 v

4

10

L

H

L

16,11

5V DC

15

H

=

LOCKED

L=
UNLOCKED

where
H

.

3.5

—

5V

L=

0

0 .

.= 1.0V

5

6

2A

2B

L

L

H

L

H

L

L

L

5.0V

3.5V

ov Low

IC4

13

10.240 MHz

9

H= RECEIVE

L = TRANSMIT
Where
FI = 3.5 — 5V

L = 0 — 1.0V

_

High

RX
TX

4.8V P.P.

10

12

10.240 MHz

5.120 MHz

V

ilter Amp

PHASE

DETECTOR

C.P

PROGRAMMABLE DIVIDER 10 Bit

t

0

CHANNEL SELECTOR

.*12

k

5 kHz

SW

CODE CONVERTER

(ROM)

000

SWITCH

Hz

11 Bit DIVIDER

1/2,043



t

T Q

REF. OSC

V DD

V DC V DD

KEYING RX = 8V

The VCO is an oscillator which controls oscillation
frequency in accordance with input voltage change.
The VCO output is mixed with a signal in the
transmitter or receiver circuitry. A portion of the

5V P.P.

VCO frequency is fed through TR14 Buffer Amp

--

and then added to TR 15. This frequency is mixed
with a 15.36 MHz frequency then goes to IC4
(1/N divider).

"N" for the 1/N divider is determined by Channel

4V P.P.

Selector Switch whose output is selected by a Code
Converter ROM.

As shown in the frequency chart, N is different
between transmit and receive mode since only one
crystal is used with this PLL circuitry.

The output from the 1/N divider is fed to Phase
Detector. On the other hand, the frequency
from the Reference OSC, 10.24 MHz, is divided
to 5 kHz by 1/2048 divider and applied to another
input of Phase Detector.

0-J

TX = CV

The Phase Detector detects the difference of these

two input signals and produces a voltage which

controls the VCO frequency.
The Low Pass Filter integrates the output of the

Phase Detector which controls the VCO frequency
and the 1/1\1 divider produces a 5 kHz frequency.

Thus the Phase Detector receives two input signals

(both 5 kHz). It compares the phase difference
between the two, generating an error voltage,

which acts on the VCO to bring the two frequen­cies exactly in-phase. When this condition occurs,
the PLL circuit is locked.

Fvco (the Frequency of the VCO) is changeable in

10 kHz increments, by varying the program divide

ratio, N.

For example, the divide ratio, N is programmed to

273 for channel No. 1 Transmit; therefore Fvco is
calculated as follows:

Fvco = 15,360 + 5 x 273 = 15,360 + 1,365

= 16,725 (kHz)

In the same manner, Fvco for channel No. 2
through No. 40 is determined as shown in Table A.

Transmitter Local Oscillator
The Transmitter local oscillator frequency of

10.240 MHz is produced by IC4 oscillator, IC4 and
crystal, X'tal 1.

Table A shows Frequency Chart of Fvco and
Divide Ratio vs. Antenna Frequency, and Program
input data.

CIRCUIT FOR DETERMINING

FREQUENCY:

Output Frequency of the Transmitter
Transmit frequency, Ft, is taken from the output

of the Transmitter Mixer IC1.
One of the inputs of IC1 is the 1st local frequency,

Fvco, which is produced by the PLL Local
Oscillator circuit. The other input is the trans­mitter local oscillator frequency of 10.240 MHz
produced by JC4.

The sum of these frequencies determines the trans­mit frequency as follows:

Ft = Fvco = 10.240 (MHz)

PLL Local Oscillator
Fvco, the output frequency of the VCO (Voltage

Controlled Oscillator), IC3, is fed to one of the
inputs of the PLL Mixer, TR15.

The offset frequency, Fstd, 15.360 MHz (10.240
MHz = 2 x 3) is fed to another input of TR 15.

The input frequency to the Programmable Divider,

Fl, is calculated as follows:

Channel Selection Program
The divide ratio of the Programmable Frequency

Divider in IC4 is determined through the Code

Converter and Transmit/Receive mode switch in

IC4 by the voltage supplied to the program input

terminals, Pin No. 1 through Pin No. 6 of IC4.
The program input voltage for Pins 1 through 6 is

supplied from the Channel Selector switch accord-

ing to the Channel Number.

The Transmit/Receive mode switch in IC4 changes
the divide ratio of the Programmable Divider by
changing Pin 9 voltage (High level for Receive, Low

level for Transmit), to produce a 455 kHz change
in VCO frequency when changing between the two
modes.

When changing between Receive and Transmit
modes, a varactor diode in the VCO IC, IC3, is
switched in or out, respectively.

The bias voltage on this varactor is so designed that
the VCO control voltage does not change when
switching between modes, thus reducing lock-up
time.

Fl = Fvco + Fstd (15.360 MHz)

F 1 is fed to the Programmable Divider in the PLL
IC, IC4 and divided by N, through the Pro-

grammable Divider.
The 10.240 MHz frequency produced by the Re-

ference Oscillator in IC4 is divided by 2,048 (the

Reference Frequency Divider in IC4) and the

resultant frequency, F2, is:

F2 = 10.240 MHz = 2,048 = 5 kHz

The output frequency of the Programmable Di­vider is compared with F2 at the Phase Detector in

IC4. When the frequency and phase of these two
signals are precisely the same, the PLL circuit is
"locked".

Therefore, Fvco is determined by the following
formula.

Fvco = Fstd (15,360 kHz) + 5 x N (kHz)

CIRCUIT FOR PREVENTION OF UNAUTHORIZED FREQUENCY EMISSION:

This Transceiver has a built-in circuit which pre­vents transmission of unauthorized frequencies
during the time when the PLL circuit is not locked
or when the Channel Selector switch is between
channels.

When the PLL circuit is not locked or the program
data input is not for channel 1 — 40, pin 15 in IC4
produces a low level digital control signal. This

signal is fed to the base of RF signal Disable

Transistor, TR 16 (INSTANT STOP).

When the Channel Selector is switched from one

input (other than data required for channels

1 — 40). However, between channels, the Channel
Selector produces a control signal at ground
potential, and this signal is fed to the base of

RF signal Disable Transistor, TR 16.

In either case, when the base of TR16 is at low
level, TR16 will not conduct and thus reduces the

supply voltage to the Amplifier stage inside IC1

to zero. This eliminates the RF signal output, and
prevents any transmission on unauthorized fre-

quencies.

channel to another, it may produce a non-valid

TABLE A: FREQUENCY CHART OF Fvco AND DIVIDE RATIO N

Antenna

Frequency

(MHz)

26.965

26.975

26.985

27.005

27.015

27.025

27.035

27.055

27.065

27.075

27.085

27.105

27.115

27.125

27.135

27.155

27.165

27.175

27.185

27.205

27.215

27.225

27.255

27.235

27.245

27.265

27.275

27.285

27.295

27.305

27.315

27.325

27.335

27.345

27.355

27.365

27.575

27.385

27.395

27.405

Channel
Number

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

Divide

Ratio

(N)
273

275
277
281
283
285
287
291
293
295
297
301
303
305
307
311
313
315
317
321
323
325
331
327
329
333
335
337
339
341
343
345
347
349
351
353
355
357
359
361

For Transmit

F1

(kHz)

1,365
1,375
1,385
1,405
1,415
1,425
1,435
1,455
1,465
1,475
1,485
1,505
1,515
1,525
1,535
1,555
1,565
1,575
1,585
1,605
1,615
1,625
1,655
1,635
1,645
1,665
1,675
1,685
1,695
1,705
1,715
1,725
1,735
1,745
1,755
1,765
1,775
1,785
1,795
1,805

VCO

Frequency

(MHz)

16.725

16.735

16.745

16.765

16.775

16.785

16.795

16.815

16.825

16.835

16.845

16.865

16.875

16.885

16.895

16.915

16.925

16.935

16.945

16.965

16.975

16.985

17.015

16.995

17.005

17.025

17.035

17.045

17.055

17.065

17.075

17.085

17.095

17.105

17.115

17.125

17.135

17.145

17.155

17.165

Divide

Ratio

(N)
182

184
186
190
197
194
196
200
202
204
206
210
212
214
216
220
222
224
226
230
232
234
240
236
238
242
244
246
248
250
252
254
256
258
260
262
264
266
268
270

For Receive

F1

(kHz)

910
920
930
950
960
970

980
1,000
1,010
1,020
1,030
1,050
1,060
1,070
1,080
1,100

1,110
1,120
1,130
1,150
1,160
1,170
1,200
1,180
1,190
1,210
1,220
1,230
1,240
1,250
1,260
1,270
1,280
1,290
1,300
1,310
1,320
1,330
1,340
1,350

VCO

Frequency

(MHz)

16.270

16.280

16.290

16.310

16.320

16.330

16.340

16.360

16.370

16.380

16.390

16.410

16.420

16.430

16.440

16.460

16.470

16.480

16.490

16.510

16.520

16.530

16.560

16.540

16.550

16.570

16.580

16.590

16.600

16.610

16.620

16.630

16.640

16.650

16.660

16.670

16.680

16.690

16.700

16.710

1A

Program input data

1B

1C

HL
L
H H
L L
HL
L
H H H
L
HL
L
HL
L
H H
L
HL
L
H
L
HL
L
HL
L
HH
L
HL HL
L
H H
L L
HL
L L
HL
L
H H
L
HL
L
H
Lit_
HL
L

HL

H H

L

L

HL

L

HH
H H
L L

L

HL

L

H

HL

L

HH
H

L

L

L L
HL
HL

L
L
L
L

L
HL
HL

L
L
L L L

L
HL

H
H
L
L
L
L

L
HL
HL

H
L
L
L

1D

L
L

L
L
HL
HL
L
L
L
L

L
L
HH
H
L

L
L

L
L
HL
HL
L
L
L
L

L
L
H
H
L

2A

L
L
L
L L
L
L
L

HL
HL
HL
HL
HL
HL
HL
HL

H
L

L
L
L
L
L
L

H
HH
HH
HH
HH
HH
HH
HH
H
H
L

2B

L
L
L

L
L
L
L
L

L
L
H
H
H
H
H
H
H
H
H
H
H

H
H
L

AMC(Automatic Modulation Control) CIRCUIT:

The modulation control used in the TRC-469
functions as follows: Modulation signals from the
mic are amplified by TR19 and IC2 and fed to the
Transmitter's final RF Amplifier stage through
Modulation Transformer Ti.

The level shift diode D19 (an 8-volt Zener diode)

"shifts" any voltage that exceeds a predetermined

level and this voltage is fed to the base of TR20
through D17 rectifier diode.

When the modulation signal from the mic increases
past this predetermined voltage level, D17 applies
a voltage to TR20, which causes base current flow.
This reduces the equivalent C-E resistance of
TR20. Note that R110 and TR20 C-E resistance
forms a voltage divider for the audio signal applied
to TR 19 Mic Amp. Thus this circuitry effectively

limits the level of modulation. VR5 sets the pre-

determined level which causes D17 to conduct.

RF (Radio Frequency) ATTENUATOR CIRCUIT:

To TX Amp

TR19

Mic. Amp

AMC control

Power Amp

IC2

Modulation line

TR20

R110



sMAP 

D17

— D18

T1
Modulation
Transformer

D19
Level shift Diode

0

Modulation signal
from the microphone

VR5
AMC control

This unit incorporates an RF attenuator circuit
using P-I-N diodes; The Equivalent RF resistance of
a P-1-N diode is controlled by the current which
flows into the diode. Thus any receiver audio dis­tortion caused by excess input signal from the
antenna or cross modulation caused by RF gain
can be prevented by these P-I-N diodes.

Since reverse-AGC is used with this Transceiver,
the voltage on the AGC line becomes lower with
strong antenna input signals (with no input signal,
approximately 1.4 volts appears on the AGC line).

Furthermore, with no input signal, current from

the AGC line flows into the base of TR 1 which
turns TR1 "on", causes collector current 1
flow and thus D23 will not conduct; therefore, no
current will flow into D1 and D2 P-I-N diodes. As
a result, there is no attenuation of the input signal
from the antenna.

With a strong input signal, the voltage on the AGC

line decreases which turns TR1 "off" and decreases
1

2

current, which increases the collector voltage of
TR1, current I
current 1

3

will flow into D1 and D2 P-I-N diodes.

1

will flow through D23, and

Thus, the equivalent RF resistance of P-I-N diodes
will drop and the excess input from the antenna to
TR2 will be bypassed by these diodes.

In addition to the above, the attenuation level is
controlled by changing VR1 (RF Gain) manually,
which causes 1

4

current to flow, which varies the

attenuation level of Dl.

2

to

ANT 4 

VR101

RF

GAIN

ANT matching circuit

Vcc

TR1



Cl



*TX Power AMP

TR2. RF AMP

C144

T1

AGC LINE

* D1, D2 : PIN diode