Rainbow Electronics W78C52D User Manual

Preliminary W78C52D

INT2

8-BIT MICROCONTROLLER

GENERAL DESCRIPTION

The W78C52D microcontroller supplies a wider frequency and supply voltage range than most 8-bit
microcontrollers on the market. It is compatible with the industry standard 80C52 microcontroller
series. The W78C52D contains four 8-bit bidirectional parallel ports, one extra 4-bit bit-addressable

I/O port (Port 4) and two additional external interrupts (
watchdog timer and a serial port. These peripherals are supported by a eight-source, two-level
interrupt capability. There are 256 bytes of RAM and an 8K byte mask ROM for application programs.

The W78C52D microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.

FEATURES

• Fully static design

• Supply voltage of 4.5V to 5.5V

•

DC-40 MHz operation

• 256 bytes of on-chip scratchpad RAM

• 8K bytes of on-chip mask ROM

• 64K bytes program memory address space

• 64K bytes data memory address space

• Four 8-bit bidirectional ports

• Three 16-bit timer/counters

• One full duplex serial port

• Eight-source, two-level interrupt capability

• One extra 4-bit bit-addressable I/O port

, INT3 ), three 16-bit timer/counters, one

• Two additional external interrupts

• Watchdog timer

• EMI reduction mode

•

Built-in power management

• Code protection

• Packages:

− DIP 40: W78C52D-24/40

− PLCC 44: W78C52DP-24/40

− QFP 44: W78C52DF-24/40

INT2 / INT3

Publication Release Date: December 1998

- 1 - Revision A1

PIN CONFIGURATIONS

40-Pin DIP (W78C52D)

T2, P1.0

T2EX, P1.1

P1.2
P1.3

P1.4
P1.5

P1.6

P1.7
RST

RXD, P3.0
TXD, P3.1

INT0, P3.2

INT1, P3.3

T0, P3.4
T1, P3.5

WR, P3.6

RD, P3.7

XTAL2
XTAL1

VSS

Preliminary W78C52D

VDD1
2

3
4

5
6
7

8
9

10
11

12
13

14
15

16
17

18
19

20

40
39

P0.0, AD0

38

P0.1, AD1

P0.2, AD2

37
36

P0.3, AD3

P0.4, AD4

35
34

P0.5, AD5

P0.6, AD6

33
32

P0.7, AD7

31

EA

30

ALE

29

PSEN

28

P2.7, A15

27

P2.6, A14

26

P2.5, A13

P2.4, A12

25
24

P2.3, A11

P2.2, A10

23
22

P2.1, A9

P2.0, A8

21

44-Pin PLCC (W78C52DP)

P

P

P

1

1

1

.

.

.

2

3

4

6543

7

P1.5

8

P1.6

9

P1.7

10

RST

RXD, P3.0

INT2, P4.3

TXD, P3.1

INT0, P3.2

INT1, P3.3

T0, P3.4

T1, P3.5

11

12

13
14

15

16
17

X

P

P

T

3

3

A

.

.

L

7

6

2

,

,

/

/

R

W

D

R

/

T

I

2

N

T

E

T

2

X

3

,

,

,

P

P

P

1

1

4

.

.

.

0

1

2

2 1 44 43 42

X

V

P

T

S

4

A

S

.

L

0

1

44-Pin QFP (W78C52DF)

/

T

I

2

N

T

E

A

A

A

A

D

D

D

D

3

1

2

0

,

,

,

,

P

P

P

P

0

0

V

0

0

.

.

D

.

.

3

1

D

2

0

40

41

39

P0.4, AD4

38

P0.5, AD5

37

P0.6, AD6

36

P0.7, AD7

35

EA

34

P4.1

33

ALE

32

PSEN

31

P2.7, A15

30

P2.6, A14

29

P2.5, A13

2827262524232221201918

P

P

P

P

P

2

2

2

2

2
.
0
,
A
8

.

.

.

.

4

3

2

1

,

,

,

,

A

A

A

A

1

1

9

1

2

1

0

P1.5
P1.6

P1.7
RST

RXD, P3.0

TXD, P3.1

INT0, P3.2

INT1, P3.3

T0, P3.4
T1, P3.5

1
2

3

4
5

6
7
8
9
10

11

P
1
.
4

44

12

P
3
.
6
,
/
W
R

P
1
.
3

43 42 41

P
3
.
7
,
/
R
D

2

X

,

,

P

P

P

1

1

1

.

.

.

0

2

1

40 39 38 37 36 35

V

X

X

S

T

T

A

S

A

L

L

1

2

T
3
,
P

V

4

D

.

D

2

P

P

2

4

.

.

0

0

,
A
8

A

A

A

A

D

D

D

D

3

2

1

0

,

,

,

,

P

P

P

P

0

0

0

0

.

.

.

.

3

2

1

0

34

33

P0.4, AD4

32

P0.5, AD5

31

P0.6, AD6

30

P0.7, AD7

29

EA

28

P4.1INT2, P4.3

27

ALE

26

PSEN

25

P2.7, A15

24

P2.6, A14

23

P2.5, A13

22212019181716151413

P

P

P

P

2

2

2

2

.

.

.

.

3

4

2

1

,

,

,

,

A

A

A

A

1

1

1

9

2

1

0

- 2 -

Preliminary W78C52D

EA

PIN DESCRIPTION

P0.0−P0.7

Port 0, Bits 0 through 7. Port 0 is a bidirectional I/O port. This port also provides a multiplexed low
order address/data bus during accesses to external memory.

P1.0−P1.7

Port 1, Bits 0 through 7. Port 1 is a bidirectional I/O port with internal pull-ups. Pins P1.0 and P1.1
also serve as T2 (Timer 2 external input) and T2EX (Timer 2 capture/reload trigger), respectively.

P2.7

−

P2.0

Port 2, Bits 0 through 7. Port 2 is a bidirectional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.

P3.0−P3.7

Port 3, Bits 0 through 7. Port 3 is a bidirectional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:

PIN ALTERNATE FUNCTION

P3.0 RXD Serial Receive Data
P3.1 TXD Serial Transmit Data
P3.2

P3.3

P3.4 T0 Timer 0 Input
P3.5 T1 Timer 1 Input
P3.6

P3.7

INT0 External Interrupt 0

INT1 External Interrupt 1

WR Data Write Strobe

RD Data Read Strobe

P4.0

−

P4.3

Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative function pins. It can
be used as general I/O pins or external interrupt input sources (

External Address Input, active low. This pin forces the processor to execute out of external ROM.
This pin should be kept low for all W78C31 operations.

RST

Reset Input, active high. This pin resets the processor. It must be kept high for at least two machine
cycles in order to be recognized by the processor.

ALE

Address Latch Enable Output, active high. ALE is used to enable the address latch that separates the
address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is
skipped during external data memory accesses. ALE goes to a high impedance state during reset with
a weak pull-up.

- 3 - Revision A1

INT2 / INT3 ).

Publication Release Date: December 1998

Preliminary W78C52D

PSEN

PSEN

Program Store Enable Output, active low. PSEN enables the external ROM onto the Port 0
address/data bus during fetch and MOVC operations.

reset with a weak pull-up.

XTAL1

Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock.

XTAL2

Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1.

VSS, VDD

Power Supplies. These are the chip ground and positive supplies.

BLOCK DIAGRAM

goes to a high impedance state during

P1.0

~

P1.7

P3.0
~
P3.7

P4.0
~
P4.3

INT2

INT3

Port

1

Port

Port

Port 1

Latch

ACC

Interrupt

Timer

2

Timer

0

Timer

1

UART

3

4

Port 3

Latch

Port 4
Latch

XTAL1 PSENALE GNDVDDRSTXTAL2

Oscillator

PSW

Instruction

Decoder

&

Sequencer

Bus & Clock

Controller

ALU

Reset Block

T2T1

SFR RAM

Address

256 bytes

RAM & SFR

8K bytes

ROM

Watchdog

Timer

B

Stack

Pointer

Power control

Port 0

Latch

DPTR

Temp Reg.

PC

Incrementor

Addr. Reg.

Port 2
Latch

Port
0

Port
2

P0.0
~
P0.7

P2.0
~
P2.7

- 4 -

Preliminary W78C52D

FUNCTIONAL DESCRIPTION

The W78C52D architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 256 bytes of RAM, three timer/counters, one watchdog timer and a serial port. The
processor supports 111 different opcodes and references both a 64K program address space and a
64 K data storage space.

Timers 0, 1, and 2

Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer
0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer
1 are the same as in the W78C51. Timer 2 is a special feature of the W78C52D: it is a 16-bit
timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2
can operate as either an external event counter or as an internal timer, depending on the setting of
bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate
generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1.

Clock

The W78C52D is designed to be used with either a crystal oscillator or an external clock. Internally,
the clock is divided by two before it is used. This makes the W78C52D relatively insensitive to duty
cycle variations in the clock.

Crystal Oscillator

The W78C52D incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias
when the crystal frequency is above 24 MHz.

External Clock

An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input one level of greater than 3.5 volts when V

= 5 volts.

DD

Power Management

Idle Mode

The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.

Power-down Mode

When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks, including the oscillator are stopped. The only way to exit power-down mode is
by a reset.

Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to

Publication Release Date: December 1998

- 5 - Revision A1

Preliminary W78C52D

INT2

deglitch the reset line when the W78C52D is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are
initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the
other SFR registers except SBUF to 00H. SBUF is not reset.

New Defined Peripheral

In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupts

INT2 , INT3 have been added to either the PLCC or QFP package. And description follows:

1.

Two additional external interrupts,
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register
is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.

***XICON - external interrupt control (C0H)

PX3: External interrupt 3 priority high if set

EX3: External interrupt 3 enable if set

IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced

IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software

PX2: External interrupt 2 priority high if set

EX2: External interrupt 2 enable if set

IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced

IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software

Eight-source interrupt informations:

/ INT3

INT2 and INT3 , whose functions are similar to those of external

PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2

INTERRUPT

SOURCE

External Interrupt 0 03H 0 (highest) IE.0 TCON.0

Timer/Counter 0 0BH 1 IE.1 -

External Interrupt 1 13H 2 IE.2 TCON.2

Timer/Counter 1 1BH 3 IE.3 -

Serial Port 23H 4 IE.4 -

Timer/Counter 2 2BH 5 IE.5 -

External Interrupt 2 33H 6 XICON.2 XICON.0

External Interrupt 3 3BH 7 (lowest) XICON.6 XICON.3

VECTOR

ADDRESS

POLLING

SEQUENCE WITHIN

PRIORITY LEVEL

ENABLE

REQUIRED

SETTINGS

INTERRUPT

TYPE

EDGE/LEVEL

- 6 -

Preliminary W78C52D

2. PORT4

Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are

alternative function pins. It can be used as general I/O pins or external interrupt input sources (

INT3 ).
Example: P4 REG 0D8H
MOV P4, #0AH ; Output data "A" through P4.0−P4.3.

MOV A, P4 ; Read P4 status to Accumulator.
SETB P4.0 ; Set bit P4.0
CLR P4.1 ; Clear bit P4.1

Watchdog Timer

The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide
the system clock. The divider output is selectable and determines the time-out interval. When the
time-out occurs a system reset can also be caused if it is enabled. The main use of the Watchdog
timer is as a system monitor. This is important in real-time control applications. In case of power
glitches or electro-magnetic interference, the processor may begin to execute errant code. If this is
left unchecked the entire system may crash. The watchdog time-out selection will result in different
time-out values depending on the clock speed. The Watchdog timer will de disabled on reset. In
general, software should restart the Watchdog timer to put it into a known state. The control bits that
support the Watchdog timer are discussed below.

INT2 /

Watchdog Timer Control Register

Bit: 7 6 543210

ENW CLRW WIDL - - PS2 PS1 PS0

Mnemonic: WDTC Address: 8FH

ENW : Enable watch-dog if set.
CLRW: Clear watch-dog timer and prescaler if set. This flag will be cleared automatically
WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled

under IDLE mode. Default is cleared.

PS2, PS1, PS0: Watch-dog prescaler timer select. Prescaler is selected when set PS2~0 as follows:

PS2 PS1 PS0 PRESCALER SELECT

0 0 0 2
0 1 0 4
0 0 1 8
0 1 1 16
1 0 0 32
1 0 1 64
1 1 0 128
1 1 1 256

Publication Release Date: December 1998

- 7 - Revision A1

Preliminary W78C52D

The time-out period is obtained using the following formula:

1

14

2 1000 12

OSC

Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6
(CLRW). After 1 is written to this bit, the 14-bit timer , prescaler and this bit will be reset on the next
instruction cycle. The Watchdog timer is cleared on reset.

PRESCALER×× × × mS

WIDL

IDLE

OSC 1/12

Watchdog Timer Block Diagram

ENW

PRESCALER

CLRW

Typical Watchdog time-out period when OSC = 20 MHz

PS2 PS1 PS0 WATCHDOG TIME-OUT PERIOD

0 0 0 19.66 mS
0 1 0 39.32 mS
0 0 1 78.64 mS
0 1 1 157.28 mS
1 0 0 314.57 mS
1 0 1 629.14 mS
1 1 0 1.25 S
1 1 1 2.50 S

EXTERNAL

RESET

14-BIT TIMER

INTERNAL

RESET

CLEAR

Reduce EMI Emission

Because of the on-chip ROM, when a program is running in internal ROM space, the ALE will be
unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it
is not needed. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR,
which is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses
external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off
again after it has been completely accessed or the program returns to internal ROM code space.

AUXR - Auxiliary Register

Bit: 7 6 5 4 3 2 1 0

- - --- --AO

Mnemonic: AUXR Address: 8Eh

AO: Turn off ALE signal.

- 8 -

Preliminary W78C52D

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL MIN. MAX. UNIT

DC Power Supply

V

CC−VSS

Input Voltage VIN VSS -0.3 VCC +0.3 V

Operating Temperature TA 070

Storage Temperature TST -55 +150

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the

device.

DC CHARACTERISTICS

Vss = 0V ; TA = 25° C; unless otherwise specified.

PARAMETER SYM. SPECIFICATION TEST CONDITIONS

MIN. MAX. UNIT

Operating Voltage VDD 4.5 5.5 V

Operating Current IDD -20mAVDD = 5.5V, 20 MHz, no load

Idle Current IIDLE -6mAVDD = 5.5V, 20 MHz, no load

Power Down Current IPWDN -50

Input

Input Current

P1, P2, P3, P4

Input Leakage Current

EA

P0,

Input Current

RST

Logic 1-to-0 Transition Current

P1, P2, P3, P4

Input Low Voltage

RST

Input Low Voltage

P1, P2, P3, P4

Input Low Voltage

[*4]

XTAL1

IIN -50 +10

ILK -10 +10

IIN2 -10 +300

ITL -500 -

VIL2 0 0.8 V VDD = 4.5V

VIL1 0 0.8 V VDD = 4.5V

VIL3 0 0.8 V VDD = 4.5V

-0.3 +7.0 V

°C

°C

µA

µA

µA

µA

µA

VDD = 5.5V, no load

VDD = 5.5V

IN

= 0V or V

V

DD

VDD = 5.5V

V

SS < VIN < VDD

VDD = 5.5V

0 < V

IN < VDD

VDD = 5.5V

V

IN

= 2V

Publication Release Date: December 1998

- 9 - Revision A1

Preliminary W78C52D

DC Characteristics, continued

PARAMETER SYM. SPECIFICATION TEST CONDITIONS

MIN. MAX. UNIT

Input

Input High Voltage

P1, P2, P3, P4

Input High Voltage

RST

Input High Voltage

XTAL1

[*4]

Output Low Voltage

P1, P2, P3, P4

Output Low Voltage

P0, ALE,

PSEN

[*4]

Sink Current

P1, P2, P3, P4

Sink Current

P0, ALE,

PSEN

Output High Voltage

P1, P2, P3, P4

Output High Voltage

P0, ALE,

PSEN

[*4]

Source Current

P1, P2, P3, P4

Source Current

P0, ALE,

Notes:
*1. RST pin has an internal pull-down.
*2. Pins of P1 and P3 can source a transition current when they are being externally driven from 1 to 0.
*3. RST is a Schmitt trigger input and XTAL1 is a CMOS input.

*4. P0, P2, ALE and

PSEN

are tested in the external access mode.

PSEN

VIH1 2.4 VDD

VV

+0.2

VIH2 3.5 VDD

VV

+0.2

VIH3 3.5 VDD

VV

+0.2

Output

VOL1 - 0.45 V VDD = 4.5V

VOL2 - 0.45 V VDD = 4.5V

ISK1 48mA VDD = 4.5V

ISK2 816mA VDD = 4.5V

VOH1 2.4 - V VDD = 4.5V

VOH2 2.4 - V VDD = 4.5V

ISR1 -100 -250

µA

ISR2 -8 -14 mA VDD = 4.5V

DD = 5.5V

DD = 5.5V

DD = 5.5V

I

OL

= +2 mA

I

OL

= +4 mA

Vin = 0.45V

V

IN = 0.45V

OH

= -100 µA

I

OH

= -400 µA

I

VDD = 4.5V

V

IN = 2.4V

V

IN = 2.4V

- 10 -

Preliminary W78C52D

AC CHARACTERISTICS

The AC specifications are a function of the particular process used to manufacture the part, the
ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the
specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will
usually experience less than a ±20 nS variation. The numbers below represent the performance
expected from a 0.5 micron CMOS process when using 2 and 4 mA output buffers.

Clock Input Waveform

XTAL1

T

CH

F

OP,

T

CL

T

CP

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES

Operating Speed FOP 0 - 24 MHz 1

Clock Period TCP 25 - - nS 2

Clock High TCH 10 - - nS 3

Clock Low TCL 10 - - nS 3

Notes:

1. The clock may be stopped indefinitely in either state.

2. The T

CP specification is used as a reference in other specifications.

3. There are no duty cycle requirements on the XTAL1 input.

Program Fetch Cycle

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES

Address Valid to ALE Low TAAS

Address Hold from ALE Low TAAH

T

ALE Low to PSEN Low

PSEN Low to Data Valid

Data Hold after PSEN High

Data Float after PSEN High

APL

T

PDA --2 TCP nS 2

T

PDH 0 -1 TCP nS 3

T

PDZ 0 -1 TCP nS

ALE Pulse Width TALW

T

PSEN Pulse Width

Notes:

1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.

2. Memory access time is 3 T

3. Data have been latched internally prior to

4. "∆" (due to buffer driving delay and wire loading) is 20 nS.

CP.

PSW

PSEN going high.

1 TCP-∆

1 TCP-∆

1 TCP-∆

2 TCP-∆

3 TCP-∆

--nS4

- - nS 1, 4

--nS4

CP - nS 4

2 T

CP -nS4

3 T

Publication Release Date: December 1998

- 11 - Revision A1

Data Read Cycle

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES

T

ALE Low to RD Low

RD Low to Data Valid

Data Hold from RD High

Data Float from RD High

RD Pulse Width

Notes:

1. Data memory access time is 8 T

2. "∆" (due to buffer driving delay and wire loading) is 20 nS.

CP.

DAR

T

DDA --4 TCP nS 1

T

DDH 0-2 TCP nS

T

DDZ 0-2 TCP nS

T

DRD

Data Write Cycle

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

T

T

T

T

DAW

DAD

DWD

DWR

ALE Low to WR Low

Data Valid to WR Low

Data Hold from WR High

WR Pulse Width

3 TCP-∆

6 TCP-∆

3 TCP-∆

1 TCP-∆

1 TCP-∆

6 TCP-∆

Preliminary W78C52D

-

3 TCP+∆

CP -nS2

6 T

-

3 TCP+∆

--nS

--nS

CP -nS

6 T

nS 1, 2

nS

Note: "∆" (due to buffer driving delay and wire loading) is 20 nS.

Port Access Cycle

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Port Input Setup to ALE Low TPDS 1 TCP --nS

Port Input Hold from ALE Low TPDH 0--nS

Port Output to ALE TPDA 1 TCP --nS

Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to

ALE, since it provides a convenient reference.

- 12 -

TIMING WAVEFORMS

Program Fetch Cycle

XTAL1

ALE

PSEN

PORT 2

PORT 0

Code

Preliminary W78C52D

S1

S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6

T

ALW

T

APL

T

PSW

T

AAS

T

A0-A7

PDA

Data

T

PDH,TPDZ

A0-A7

Code

A0-A7

Data

T

AAH

A0-A7

Data Read Cycle

XTAL1

ALE

PSEN

PORT 2

PORT 0

RD

A0-A7

S2 S3S5 S6 S1S2 S3 S4S5 S6 S1S4

A8-A15

DATA

DAR

T

DDA

T

DRD

T

DDH,TDDZ

T

Publication Release Date: December 1998

- 13 - Revision A1

Timing Waveforms, continued

Data Write Cycle

XTAL1

ALE

PSEN

Preliminary W78C52D

S2 S3S5 S6 S1S2 S3 S4S1S5 S6S4

PORT 2

PORT 0

WR

Port Access Cycle

XTAL1

ALE

PORT

INPUT

SAMPLE

A8-A15

A0-A7

T

DAW

T

DAD

DATA OUT

T

DWR

T

DWD

S5 S6 S1

T

T

PDHPDS

T

PDA

DATA OUT

- 14 -

APPLICATION CIRCUITS

Expanded External Program Memory and Crystal

V

DD

31

EA

19

XTAL1

R

18

XTAL2

9

C2

RST

INT0

12
13

INT1

14

T0

15

T1

1

P1.0

2

P1.1

3

P1.2

4

P1.3

5

P1.4

6

P1.5

7

P1.6

8

P1.7

W78C52D

P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7

P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7

PSEN

ALE
TXD
RXD

RD
WR

AD0

39
38
37
36
35
34

33
32

21
22
23
24
25
26
27
28

17
16
29

30
11
10

AD1
AD2
AD3

AD4
AD5
AD6
AD7

A8
A9
A10
A11
A12

A13

A14
A15

AD0
AD1
AD2
AD3

AD4
AD5
AD6
AD7

GND

8.2 K

V

DD

10 u

CRYSTAL

C1

Preliminary W78C52D

4
7
8
13
14
17
18

3

1

11

D0
D1
D2
D3
D4
D5
D6
D7

OC
G

74HC373

2

Q0

5

Q1

6

Q2

9

Q3

12

Q4

15

Q5

16

Q6

19

Q7

A0

A10
A11
A12
A13
A14
A15

GND

10

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15

CE

OE

27512

O0
O1
O2
O3
O4
O5
O6
O7

A1

9

A2

8

A3

7

A4

6

A5

5

A6

4

A7

3

25

A8

24

A9

21
23
2
26
27

1

20
22

A0
A1
A2
A3
A4
A5
A6
A7

11

AD0

12

AD1

13

AD2

15

AD3

16

AD4

17

AD5

18

AD6

19

AD7

CRYSTAL C1 C2 R

16 MHz 30P 30P

24 MHz 15P 15P

33 MHz 10P 10P 6.8K

40 MHz 5P 5P 4.7K

Above table shows the reference values for crystal applications.

Note: C1, C2, R components refer to Figure A.

Figure A

−

−

Publication Release Date: December 1998

- 15 - Revision A1

Application Circuits, continued

Expanded External Data Memory and Oscillator

V

OSCILLATOR

DD

31

EA

19

XTAL1

18

XTAL2

9

RST

INT0

12
13

INT1

14

T0

15

T1

1

P1.0

2

P1.1

3

P1.2

4

P1.3

5

P1.4

6

P1.5

7

P1.6

8

P1.7

W78C52D

P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7

P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7

PSEN

RXD

WR

ALE

TXD

AD0

39

AD1

38

AD2

37

AD3

36

AD4

35

AD5

34
33

AD6

32

AD7

21

A8

A9

22
23

A10

24

A11

25

A12

26

A13

27

A14

28

RD

17
16
29
30
11
10

8.2 K

V

DD

10 u

AD0
AD1
AD2
AD3
AD4
AD5
AD6

AD7

GND

Preliminary W78C52D

3

D0 Q0

4

D1 Q1

7

D2 Q2

8

D3 Q3

13

D4 Q4

14

D5 Q5

17

D6 Q6

18

D7

1

OC
G 11

74HC373

A0

2

A1

5

A2

6

A3

9
12

A4
A5

15

A6

16

A7

19

Q7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14

GND

10

9
8
7
6
5
4

3
25
24
21
23

2
26

1

20
22
27

OE

20256

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

A10
A11
A12
A13
A14

CE

WR

D0
D1
D2
D3
D4
D5
D6
D7

11

AD0

12

AD1

13

AD2

15

AD3

16

AD4
AD5

17

AD6

18

AD7

19

Figure B

- 16 -

PACKAGE DIMENSIONS

40-pin DIP

40

1

E

S

A

2

A

L

D

B

e

B

1

Preliminary W78C52D

Dimension in inch Dimension in mm

Symbol

A
A
A
B
B
c

21

201

Base Plane

1

A

Seating Plane

1

E

eA

a

D
E
E
e
L

a

e
S

Notes:

1. Dimension D Max. & S include mold flash or

c

2. Dimension E1 does not include interlead flash.

3. Dimension D & E1 include mold mismatch and

4. Dimension B1 does not include dambar

5. Controlling dimension: Inches.

6. General appearance spec. should be based on

Nom.

Min.

0.010

1

0.150

2

0.016

1

0.008

0.540

1

1

0.120

A

tie bar burrs.

are determined at the mold parting line.

protrusion/intrusion.

final visual inspection spec.

Max. Max.

Min.

0.210

0.160

0.022

0.014

0.610

0.5500.545

0.110

0.140

0.670

0.090

.

0.254

3.81

0.406

0.203

14.986

13.72

2.286 2.54 2.7940.090 0.100

3.048

0.155

0.018

0.050 1.27

0.010

2.055 2.070 52.20 52.58

0.6000.590

0.130

015

0.6500.630 16.00 16.51

Nom.

3.937

0.457

0.254

15.24

13.84

3.302

5.334

4.064

0.559

1.3721.2190.0540.048

0.356

15.494

13.97

3.556

17.01

2.286

150

44-pin PLCC

7

17

L

θ

Seating Plane

H

D

D

e

44 40

G

D

b

b

1

61

Dimension in inch Dimension in mm

Symbol

39

H

E

E

29

2818

A

2

A

A

1

y

G

E

c

A

A

A

b
b
c
D
E
e
G
G
H
H
L

y

Notes:

1. Dimension D & E do not include interlead
flash.

2. Dimension b1 does not include dambar

protrusion/intrusion.

3. Controlling dimension: Inches

4. General appearance spec. should be based
on final visual inspection spec.

Nom.

Min.

0.185

0.020

1

0.150

0.145

0.026

0.016

0.008

0.648

0.050 BSC

0.590

0.590

0.680

0.680

0.090

0.028

0.018

0.010

0.653

0.610

0.690

0.690

0.100

0.155

0.032

0.022

0.014

0.658

0.6580.6530.648

0.630

0.6300.610

0.700

0.700

0.110

0.004

2

1

D

E

D

E

Nom.

Max. Max.

Min.

0.66

1.27

3.81

0.711

0.457

0.254

16.59

15.49

15.4914.99

17.53

2.54

BSC

4.699

3.937

0.813

0.559

0.356

16.71

16.7116.5916.46

16.00

16.00

17.78

17.7817.53

2.794

0.10

0.508

3.683

0.406

0.203

16.46

14.99

17.27

17.27

2.296

Publication Release Date: December 1998

- 17 - Revision A1

Package Dimensions, continued

44-pin QFP

H

D

44

1

11

12

Seating Plane

D

e

See Detail F

Preliminary W78C52D

Dimension in inch

34

Symbol

A

A

33

A

b
c
D

E

EH

E

e
H
H

L

L

22

b

c

A

A

2

A

1

y

θ

L

L

1

Detail F

y

θ

Notes:

1. Dimension D & E do not include interlead
flash.

2. Dimension b does not include dambar

protrusion/intrusion.

3. Controlling dimension: Millimeter

4. General appearance spec. should be based
on final visual inspection spec.

Nom.

Min.

--- ---

0.01 0.02 0.25

0.002

1

0.081

0.075

2

0.01

0.014

0.006 0.152

0.394

0.390

0.390

0.025

0.031

0.510 13.45

0.520

D

0.520

0.510

E

0.025

0.031

0.051 0.075 1.295

0.063

1

0

Dimension in mm

Max. Max.

---

0.087

0.018

0.0100.004

0.398

0.3980.394

0.036

0.530

0.530

0.037

0.003

Nom.

Min.

--- ---

0.05

1.90

0.25

9.9

9.9

0.635

12.95

12.95

0.65

7

0

2.05

0.35

10.00

10.00

13.2

0.80

---

0.5

2.20

0.45

0.2540.101

10.1

10.1

0.952

13.4513.2

0.8

0.95

1.6

1.905

0.08

7

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: [phone]
FAX: [phone]
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: [phone]
FAX: [phone]

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: [phone]
FAX: [phone]

Note: All data and specifications are subject to change without notice.

- 18 -

Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.

2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: [phone]
FAX: [phone]