W78C32C
8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The W78C32C microcontroller supplies a wider frequency range than most 8-bit microcontrollers on
the market. It is compatible with the industry standard 80C32 microcontroller series.
The W78C32C contains four 8-bit bidirectional parallel ports, three 16-bit timer/counters, and a serial
port. These peripherals are supported by a six-source, two-level interrupt capability. There are 256
bytes of RAM, and the device supports ROMless operation for application programs.
The W78C32C microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
1.processor.
FEATURES
• 8-bit CMOS microcontroller
• Fully static design
•
Low standby current at full supply voltage
• DC-40 MHz operation
• 256 bytes of on-chip scratchpad RAM
• ROMless operation
• 64K bytes program memory address space
• 64K bytes data memory address space
• Four 8-bit bidirectional ports
• Three 16-bit timer/counters
• One full duplex serial port
• Boolean processor
• Six-source, two-level interrupt capability
• Built-in power management
• Packages:
− DIP 40: W78C32C-24/40
− PLCC 44: W78C32CP-24/40
− QFP 44: W78C32CF-24/40
Publication Release Date: July 1999
- 1 - Revision A2
PIN CONFIGURATIONS
40-Pin DIP (W78C32C)
W78C32C
T2, P1.0
T2EX, P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
WR, P3.6
RD, P3.7
XTAL2
XTAL1
Vss
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Vcc1
40
P0.0, AD0
39
P0.1, AD1
38
P0.2, AD2
37
P0.3, AD3
36
35
P0.4, AD4
34
P0.5, AD5
P0.6, AD6
33
32
P0.7, AD7
31
EA
30
ALE
29
PSEN
28
P2.7, A15
27
P2.6, A14
26
P2.5, A13
25
P2.4, A12
24
P2.3, A11
23
P2.2, A10
22
P2.1, A9
21
P2.0, A8
44-Pin PLCC (W78C32CP) 44-Pin QFP (W78C32CF)
P1.5
P1.6
P1.7
RST
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
T
2
T
E
2
X
,
,
P
P
P
P
P
1
1
1
.
.
.
0
1
2NC
2 1 44 43 42
X
V
X
T
S
T
A
S
A
L
L
1
2
V
C
C
N
P
C
2
.
0
,
A
8
1
1
.
.
3
4
6543
7
8
9
10
11
12
NC
13
14
15
16
17
P
P
3
3
.
.
7
6
,
,
/
/
R
W
D
R
A
A
A
A
D
D
D
D
3
2
1
0
,
,
,
,
P
P
P
P
0
0
0
0
.
.
.
.
3
2
1
0
40
41
P0.4, AD4
39
38
P0.5, AD5
37
P0.6, AD6
36
P0.7, AD7
35
EA
34
NC
33
ALE
32
PSEN
31
P2.7, A15
30
P2.6, A14
29
P2.5, A13
2827262524232221201918
P
P
P
P
2
2
2
2
.
.
.
.
4
3
2
1
,
,
,
,
A
A
A
A
1
1
1
9
2
1
0
P1.5
P1.6
P1.7
RST
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
NC
1
2
3
4
5
6
7
8
9
10
11
P
1
.
4
12
P
3
.
6
,
/
W
R
P
P
1
1
.
.
2NC
3
43 42 41
X
P
T
3
A
.
L
7
2
,
/
R
D
T
2
T
E
2
X
,
,
P
P
1
1
.
.
0
1
40 39 38 37 36
X
V
N
T
S
C
A
S
L
1
V
C
C
P
P
2
2
.
.
1
0
,
,
A
A
9
8
A
A
A
A
D
D
D
D
3
2
1
0
,
,
,
,
P
P
P
P
0
0
0
0
.
.
.
.
3
2
1
0
34
3544
P0.4, AD4
33
32
P0.5, AD5
31
P0.6, AD6
30
P0.7, AD7
29
EA
28
NC
27
ALE
26
PSEN
25
P2.7, A15
24
P2.6, A14
23
P2.5, A13
22212019181716151413
P
P
P
2
2
2
.
.
.
4
3
2
,
,
,
A
A
A
1
1
1
2
1
0
- 2 -
W78C32C
EA
PIN DESCRIPTION
P0.0
−
P0.7
Port 0, Bits 0 through 7. Port 0 is a bidirectional I/O port. This port also provides a multiplexed low
order address/data bus during accesses to external memory.
P1.0−P1.7
Port 1, Bits 0 through 7. Port 1 is a bidirectional I/O port with internal pull-ups. Pins P1.0 and P1.1
also serve as T2 (Timer 2 external input) and T2EX (Timer 2 capture/reload trigger), respectively.
P2.0−P2.7
Port 2, Bits 0 through 7. Port 2 is a bidirectional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.
P3.0
−
P3.7
Port 3, Bits 0 through 7. Port 3 is a bidirectional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:
PIN ALTERNATE FUNCTION
P3.0 RXD Serial Receive Data
P3.1 TXD Serial Transmit Data
P3.2
P3.3
P3.4 T0 Timer 0 Input
P3.5 T1 Timer 1 Input
P3.6
P3.7
External Address Input, active low. This pin forces the processor to execute out of external ROM.
This pin should be kept low for all W78C32C operations.
INT0
External Interrupt 0
INT1
External Interrupt 1
WR
Data Write Strobe
RD
Data Read Strobe
RST
Reset Input, active high. This pin resets the processor. It must be kept high for at least two machine
cycles in order to be recognized by the processor.
ALE
Address Latch Enable Output, active high. ALE is used to enable the address latch that separates the
address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is
skipped during external data memory accesses. ALE goes to a high state during reset with a weak
pull-up.
Publication Release Date: July 1999
- 3 - Revision A2
W78C32C
PSEN
Program Store Enable Output, active low.
address/data bus during fetch and MOVC operations.
weak pull-up.
XTAL1
Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock.
XTAL2
Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1.
VSS, VCC
Power Supplies. These are the chip ground and positive supplies.
BLOCK DIAGRAM
PSEN
enables the external ROM onto the Port 0
PSEN
goes to a high state during reset with a
RAM
256
Bytes
CPU
Data Bus
CORE
Interrupt
SFR
Timer 2
Serial
Port
Timer 0
Timer 1
INT 0
INT 1
Port 0
Port 1
Alternate
Port 2
Port 3
Alternate
- 4 -
W78C32C
FUNCTIONAL DESCRIPTION
The W78C32C architecture consists of a core controller surrounded by various registers, four general
purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports
111 different instruction and references both a 64K program address space and a 64K data storage
space.
Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2.
The operations of Timer 0 and Timer 1 are the same as in the W78C31. Timer 2 is a special feature
of the W78C32C: it is a 16-bit timer/counter that is configured and controlled by the T2CON register.
Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer,
depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, autoreload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that
of Timers 0 and 1.
Clock
The W78C32C is designed to be used with either a crystal oscillator or an external clock. Internally,
the clock is divided by two before it is used. This makes the W78C32C relatively insensitive to duty
cycle variations in the clock.
Crystal Oscillator
The W78C32C incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias
when the crystal frequency is above 24 MHz.
External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input one level of greater than 3.5 volts.
Power Management
Idle Mode
The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.
Power-down Mode
When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks, including the oscillator are stopped. The only way to exit power-down mode is
by a reset.
Publication Release Date: July 1999
- 5 - Revision A2
W78C32C
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running.
An internal trigger circuit in the reset line is used to deglitch the reset line when the W78C32C is used
with an external RC network. The reset logic also has a special glitch removal circuit that ignores
glitches on the reset line.
During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of
bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL MIN. MAX. UNIT
CC
DC Power Supply V
Input Voltage VIN V
Operating Temperature TA 0 70
Storage Temperature TST -55 +150
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of
the device.
DC CHARACTERISTICS
V
VCC
SS = 5V
−
Operating Voltage VDD
Operating Current IDD No load
Idle Current I
Power Down Current I
Input Current
P1, P3
Input Current
RST
Input Leakage Current
(*1)
P0
Output Low Voltage
P1, P2
Output Low Voltage
ALE,
10%, TA = 25° C, FOSC = 20 MHz unless otherwise specified.
±
PARAMETER SYM. TEST CONDITIONS SPECIFICATION UNIT
IDLE
Idle mode
PWDN
IN1
I
VDD = 5.5V
IN2
I
(*2)
VDD = 5.5V
LK
I
VDD = 5.5V
OL1
VDD = 4.5V
(*1)
PSEN
, P3
, P0
(*1)
V
OL2
VDD = 4.5V
V
−
VSS -0.3 +7.0 V
SS
-
DD
V
= 5.5V
DD
V
= 5.5V
Power-down mode
DD
= 5.5V
V
IN
= 0V or VDD
V
IN
= VDD
V
IN<VDD
0V<V
OL1
I
= +2 mA
OL2
I
= +4 mA
-0.3 V
CC
+0.3 V
MIN. TYP.
°
C
°
C
MAX.
4.5 5 5.5 V
- - 30 mA
- - 6 mA
- - 50
-75 - +10
- +184 +350
-10 - +10
- - 0.45 V
- - 0.45 V
µ
A
µ
A
µ
A
µA
- 6 -
W78C32C
DC Characteristics, continued
PARAMETER SYM. TEST CONDITIONS SPECIFICATION UNIT
MIN. TYP. MAX.
Output High Voltage
P1, P3
Output High Voltage
PSEN
ALE,
, P0
(*1)
, P2
(*1)
Input Low Voltage
P1, P3
Input Low Voltage
XTAL1, RST
(*3)
Input High Voltage
P1, P3
Input High Voltage
XTAL1, RST
Notes:
1. P0 and P2 are in external access mode.
2. RST pin has an internal pull-down resistor of about 30K Ω.
3. XTAL1 is a CMOS input and RST is a Schmitt trigger input.
(*3)
AC CHARACTERISTICS
The AC specifications are a function of the particular process used to manufacture the part, the
ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the
specifications can be expressed in terms of multiple input clock periods (T
usually experience less than a ±20 nS variation. The numbers below represent the performance
expected from a 0.5 micron CMOS process when using 2 and 4 mA output buffers.
OH1
V
VDD = 4.5V
OH1
I
= -100 µA
OH2
VDD = 4.5V
V
OH2
I
IL1
V
VDD = 4.5V 0 - 0.8 V
IL2
VDD = 4.5V 0 - 0.8 V
V
IH1
V
VDD = 5.5V 2.4 - V
IH2
VDD = 5.5V 3.5 - V
V
= -400 µA
2.4 - - V
2.4 - - V
DD
+0.2 V
DD
+0.2 V
CP
), and actual parts will
Clock Input Waveform
XTAL1
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES
Operating Speed FOP 0 - 40 MHz 1
Clock Period TCP 25 - - nS 2
Clock High TCH 10 - - nS 3
Clock Low TCL 10 - - nS 3
Notes:
1. The clock may be stopped indefinitely in either state.
CP specification is used as a reference in other specifications.
2. The T
3. There are no duty cycle requirements on the XTAL1 input.
- 7 - Revision A2
T
CH
OP,
F
TCP
T
CL
Publication Release Date: July 1999
Program Fetch Cycle
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES
PSEN
AAS
1 T
AAH
1 T
APL
T
PDA
T
PDH
T
PDZ
T
ALW
PSW
T
going high.
1 T
- - 2 TCP nS 2
0 - 1 TCP nS 3
0 - 1 TCP nS
2 T
3 T
Address Valid to ALE Low T
Address Hold after ALE Low T
ALE Low to
PSEN
Data Hold after
Data Float after
PSEN
Low
Low to Data Valid
PSEN
High
PSEN
High
ALE Pulse Width T
PSEN
Pulse Width
Notes:
1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 T
3. Data have been latched internally prior to
4. "∆" ( due to buffer driving delay and wire loading) is 20 nS.
CP
.
Data Read Cycle
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE
DAR
ALE Low to RD Low
RD
Low to Data Valid
Data Hold after RD High
Data Float after
RD
Pulse Width
Notes:
1. Data memory access time is 8 T
2. "∆" (due to buffer driving delay and wire loading) is 20 nS.
RD
High
CP.
T
T
T
T
T
DDA
DDH
DDZ
DRD
3 T
- - 4 TCP nS 1
0 - 2 TCP nS
0 - 2 TCP nS
6 T
CP
CP
CP
CP
CP
CP
CP
-∆
-∆
-∆
-∆
-∆
-∆
-∆
W78C32C
- - nS 4
- - nS 1, 4
- - nS 4
CP
2 T
- nS 4
CP
3 T
- nS 4
S
nS 1, 2
∆
6 T
-
CP
CP+
3 T
- nS 2
Data Write Cycle
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
DAW
ALE Low to
Data Valid to
Data Hold from
WR
Pulse Width
Note: "∆" ( due to buffer driving delay and wire loading) is 20 nS.
WR
WR
Low
Low
WR
High
T
T
T
T
DAD
DWD
DWR
3 T
1 T
1 T
6 T
- 8 -
CP
CP
CP
CP
-∆
-∆
-∆
-∆
-
3 T
CP+
nS
∆
- - nS
- - nS
CP
6 T
- nS
W78C32C
Port Access Cycle
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Port Input Setup to ALE Low T
Port Input Hold from ALE Low T
Port Output to ALE T
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
TIMING WAVEFORMS
Program Fetch Cycle
S1
S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
XTAL1
ALE
PSEN
PORT 2
T
AAH
PORT 0
A0-A7
Code
PDS
1 TCP - - nS
PDH
0 - - nS
PDA
1 TCP - - nS
T
ALW
T
APL
T
PSW
T
AAS
T
PDA
Data
T
PDH,
A0-A7
T
PDZ
Code
A0-A7
Data
A0-A7
Data Read Cycle
XTAL1
ALE
PSEN
PORT 2
A0-A7
PORT 0
T
RD
DAR
A8-A15
T
DDA
DATA
T
DDH,TDDZ
T
DRD
Publication Release Date: July 1999
- 9 - Revision A2
S2 S3S5 S6 S1S2 S3 S4S5 S6 S1S4
Timing Waveforms, continued
Data Write Cycle
XTAL1
ALE
PSEN
W78C32C
S2 S3S5 S6 S1S2 S3 S4S1S5 S6S4
PORT 2
PORT 0
WR
Port Access Cycle
XTAL1
ALE
PORT
INPUT
SAMPLE
T
A8-A15
A0-A7
T
DAW
S5 S6 S1
PDS
T
T
PDH
DAD
DATA OUT
T
DWR
T
DWD
T
PDA
DATA OUT
- 10 -
TYPICAL APPLICATION CIRCUIT
Using External Program Memory and Crystal
V
8.2 K
CC
10 u
CRYSTAL
C1
C2
31
EA
19
XTAL1
R
18
XTAL2
9
RST
INT0
12
13
INT1
14
T0
15
T1
1
P1.0
P1.1
2
P1.2
3
P1.3
4
P1.4
5
P1.5
6
P1.6 7
P1.7 8
W78C32C
PSEN
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
ALE
TXD
RXD
AD0
39
38
AD1
37
AD2
36
AD3
35
AD4
AD5
34
33
AD6
32
AD7
21
A8
22
A9
23
A10
24
A11
25
A12
A13
26
27
A14
28
A15
RD
17
16
WR
29
30
11
10
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
W78C32C
D0
D1
D2
D3
D4
D5
D6
D7
OC
G
74LS373
2
Q0
5
Q1
6
Q2
9
Q3
12
Q4
15
Q5
16
Q6
19
Q7
A0
10
A10
A13
GND
A11
A12
A14
A15
A0
A1
9
A1
A2
8
A2
A3
7
A3
A4
6
A4
A5
5
A5
A6
4
A6
A7
3
A7
A8
25
A8
A9
24
A9
21
A10
23
A11
2
A12
26
A13
27
A14
1
A15
20
CE
22
OE
27512
A1
A2
A3
A4
A5
A6
A7
AD0A0
11
O0
12
AD1
O1
13
AD2
O2
15
AD3
O3
16
AD4
O4
AD5
17
O5
18
AD6
O6
AD7
19
O7
3
4
7
8
13
14
17
18
1
11
Figure A
CRYSTAL C1 C2 R
16 MHz 30P 30P -
24 MHz 15P 15P -
33 MHz 10P 10P 6.8K
40 MHz 5P 5P 6.8K
Above table shows the reference values for crystal applications.
Note: C1, C2, R components refer to Figure A.
Publication Release Date: July 1999
- 11 - Revision A2
Expanded External Data Memory and Oscillator
V
8.2 K
CC
OSCILLATOR
10 u
31
EA
19
XTAL1
18
XTAL2
9
RST
INT0
12
13
INT1
14
T0
15
T1
1
P1.0
2
P1.1
3
P1.2
4
P1.3
5
P1.4
6
P1.5
7
P1.6
8
P1.7
W78C32C
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0 21
P2.1
P2.2 23
P2.3
P2.4 25
P2.5 26
P2.6
P2.7
RD
WR
PSEN
ALE
TXD
RXD
39
38
37
36
35
34
33
32
22
24
27
28
17
16
29
30
11
10
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A8
A9
A10
A11
A12
A13
A14
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
Figure B
W78C32C
3
D0
Q0
4
D1
Q1
7
D2
Q2
8
D3
Q3
13
D4
Q4
14
D5
Q5
17
D6
Q6
18
D7
Q7
1
OC
G 11
74LS373
A0
A1
A2
A4
A5
A6
A9
A11
A13
GND
A3
A7
A8
A10
A12
A14
10
A0
9
A1
8
A2
7
A3
6
A4
5
A5
4
A6
3
A7
25
A8
24
A9
21
A10
23
A11
2
A12
26
A13
1
A14
20
CE
22
OE
27
WR
20256
2
A0
5
A1
6
A2
9
A3
12
A4
15
A5
16
A6
19
A7
11
D0
D1
D2
D3
D4
D5
D6
D7
AD0
12
AD1
13
AD2
15
AD3
16
AD4
17
AD5
AD6
18
AD7
19
- 12 -
PACKAGE DIMENSIONS
40-pin DIP
40 21
1
E
1
S
A
2
A
L
D
B
e
1
B
1
W78C32C
Dimension in inch Dimension in mm
Symbol
Min. Nom. Max. Max.Nom.Min.
A
1
A
2
A
B
1
B
c
D
E
E
1
e
1
L
a
e
A
20
Base Plane
1
A
Seating Plane
E
eA
a
S
Notes:
1. Dimension D Max. & S include mold flash or
tie bar burrs.
c
2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and
are determined at the mold parting line.
4. Dimension B1 does not include dambar
protrusion/intrusion.
5. Controlling dimension: Inches.
6. General appearance spec. should be based on
final visual inspection spec.
0.210
0.010
0.150
0.155
0.160
0.016
0.018
0.022
0.050 1.27
0.0540.048
0.010
0.014
0.008
2.055 2.070
0.610
0.6000.590
0.540
0.545
0.550
0.110
0.120
0.130
0.140
015
0.630 16.00
0.670
0.650
0.090
.
0.254
3.81
0.406
0.203
14.986
13.72
2.286 2.54 2.7940.090 0.100
3.048
3.937
0.457
0.254
52.20
15.24
3.302
16.51
5.334
4.064
0.559
1.3721.219
0.356
52.58
15.494
13.9713.84
3.556
150
17.01
2.286
44-pin PLCC
H
D
D
e
44 40
G
D
Dimension in inch Dimension in mm
Symbol
Min. Nom. Max. Max.Nom.Min.
39
H
E
E
29
2818
2A
A
b
b
1
A
1
y
G
E
c
A
A
1
A
2
b
1
b
c
D
E
e
G
D
G
E
H
D
H
E
L
y
Notes:
1. Dimension D & E do not include interlead
flash.
2. Dimension b1 does not include dambar
protrusion/intrusion.
3. Controlling dimension: Inches
4. General appearance spec. should be based
on final visual inspection spec.
0.020
0.145
0.026
0.016
0.008
0.648
0.648
0.590
0.590
0.680
0.680
0.090
0.150
0.028
0.018
0.010
0.653
0.653
0.050 BSC
0.610
0.690
0.690
0.100
0.185
0.155
0.032
0.022
0.014
0.658
0.658
0.630
0.6300.610
0.700
0.700
0.110
0.004
0.508
3.683
0.66
0.406
0.203
16.46
16.46
14.99
17.27
17.27
2.296
4.699
3.81
3.937
0.711
0.813
0.559
0.457
0.254
0.356
16.59
16.71
16.59
16.71
1.27
BSC
16.00
15.49
16.0015.4914.99
17.78
17.53
17.7817.53
2.794
2.54
0.10
Publication Release Date: July 1999
61
7
17
L
θ
Seating Plane
- 13 - Revision A2
Package Dimensions, continued
44-pin QFP
H
D
D
44
1
11
12
e
Seating Plane
See Detail F
W78C32C
Dimension in inch Dimension in mm
34
33
EEH
22
b
c
A
A
2
A
1
y
θ
L
L
1
Detail F
Symbol
A
A
A
b
c
D
E
e
H
H
L
L
y
θ
Notes:
1. Dimension D & E do not include interlead
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Controlling dimension: Millimeter
4. General appearance spec. should be based
on final visual inspection spec.
Nom.
Min.
0.002
1
0.075
2
0.01
0.390
0.390
0.025
0.510 13.45
D
0.510
E
0.025
0.051 0.075 1.295
1
Max. Max.
---
0.01 0.02 0.25
0.081
0.087
0.014
0.018
0.006 0.152
0.0100.004
0.394
0.398
0.3980.394
0.036
0.031
0.520
0.530
0.520
0.530
0.031
0.037
0.063
0.003
0
7
Min.
--- --- --- --- ---
0.05
1.90
0.25
9.9
9.9
0.635
12.95
12.95
0.65
0
Nom.
2.05
0.35
10.00
10.00
0.80
13.2
0.8
1.6
0.5
2.20
0.45
0.2540.101
10.1
10.1
0.952
13.4513.2
0.95
1.905
0.08
7
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5792766
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
- 14 -
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798
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