The W49F020 is a 2-megabit, 5-volt only CMOS flash memory organized as 256K × 8 bits. The device
can be programmed and erased in-system with a standard 5V power supply. A 12-volt V
required. The unique cell architecture of the W49F020 results in fast program/erase operations with
extremely low current consumption (compared to other comparable 5-volt flash memory products). The
device can also be programmed and erased using standard EPROM programmers.
FEATURES
• Single 5-volt operations:
− 5-volt Read
− 5-volt Erase
− 5-volt Program
• Fast Program operation:
− Byte-by-Byte programming: 50 µS (max.)
• Fast Erase operation: 100 mS (typ.)
• Fast Read access time: 70/90 nS
• Endurance: 1K/10K cycles (typ.)
• Twenty-year data retention
•
Hardware data protection
• One 8K byte Boot Block with Lockout
protection
• Low power consumption
− Active current: 25 mA (typ.)
− Standby current: 20 µA (typ.)
•
Automatic program and erase timing with
internal V
• End of program or erase detection
− Toggle bit
− Data polling
• Latched address and data
• TTL compatible I/O
• JEDEC standard byte-wide pinouts
• Available packages: 32-pin DIP and 32-pin
TSOP and 32-pin-PLCC
PP generation
PP is not
Publication Release Date: October 1999
- 1 - Revision A1
Preliminary W49F020
CONTROL
OUTPUT
BUFFER
DECODER
MAIM MEMORY
248K BYTES
BOOT BLOCK
8K BYTES
PIN CONFIGURATIONS
1
NC
2
A16
3
A15
4
A12
5
A7
6
A6
7
A5
32-pin
8
A17
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A11
2
A9
3
A8
A13
5
A14
6
WE
V
DD
9
NC
10
A16
11
A15
12
A12
13
A7
14
A6
15
A5
16
A4
DIP
9
10
11
12
13
14
15
16
A
A
V
/
A
N
1
1
D
W
1
C
2
6
D
E
5
5
6
7
32-pin
8
PLCC
9
10
11
12
13
D
D
D
G
D
D
Q
Q
Q
Q
N
Q
4
1
2
D
5
3
32-pin
TSOP
BLOCK DIAGRAM
32
V
DD
31
WE
30
A17
29
A14
28
A13
27
A8
26
A9
25
A11
24
OE
23
A10
22
CE
21
DQ7
20
DQ6
19
DQ5
18
DQ4
17
DQ3
A
1
7
3031321234
A14
29
28
A13
27
A8
26
A9
25
A11
24
OE
23
A10
22
CE
21
DQ7
20191817161514
D
Q
6
V
DD
V
SS
CE
OE
WE
A0
.
.
A17
PIN DESCRIPTION
SYMBOL PIN NAME
A0−A17
32
OE
A10
31
30
CE
29
DQ7
28
DQ6
DQ5
27
DQ4
26
25
DQ3
GND
24
23
DQ2
22
DQ1
21
DQ0
20
A0
19
A1
18
A2
17
A3
DQ0−DQ7
CE
OE
WE
VDDPower Supply
GND Ground
NC No Connection
W49F020
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
DQ0
DQ7
.
.
3FFFF
02000
01FFF
00000
- 2 -
Preliminary W49F020
FUNCTIONAL DESCRIPTION
Read Mode
The read operation of the W49F020 is controlled by CE and OE, both of which have to be low for the
host to obtain data from the outputs.
de-selected and only standby power will be consumed.
from the output pins. The data bus is in high impedance state when either
timing waveforms for further details.
Boot Block Operation
There is an 8K-byte boot block in this device, which can be used to store boot code. The boot block
locates in the first 8K bytes of the memory with the address range from 0000(hex) to 1FFF(hex). For the
specific code, please see Command Codes for Boot Block Lockout Enable.
When the boot block is enabled, data for the designated block cannot be erased or programmed
(programming lockout); other memory locations can be changed by the regular programming method.
When the boot block programming lockout feature is activated, the chip erase function cannot erase the
boot block any longer.
In order to detect whether the boot block feature is set on the 8K-bytes block or not, users can perform
software command sequence to check it. First, enter the product identification mode (see Command
Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address
"0002 hex". If the output data is "1," the boot block programming lockout feature is activated; if the
output data is "0," the lockout feature is inactivated and the block can be erased/programmed.
To return to normal operation, perform a three-byte command sequence (or an alternate single-word
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.
CE is used for device selection. When CE is high, the chip is
OE is the output control and is used to gate data
CE or OE is high. Refer to the
Chip Erase Operation
The chip-erase mode can be initiated by a six-word command sequence. After the command loading
cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed
in a fast 100 mS (typical). The host system is not required to provide any control or timing during this
operation. If the boot block programming lockout is activated, only the data in the main memory blocks
will be erased to FF(hex), and the data in the boot block will not be erased (remains same as before the
chip erase operation). The entire memory array will be erased to FF hex by the chip erase operation if
the boot block programming lockout feature is not activated. Once the boot block lockout feature is
activated, the chip erase function erase the main memory block but not the boot block. The device will
automatically return to normal read mode after the erase operation completed. Data polling and/or
Toggle Bits can be used to detect end of erase cycle.
Program Operation
The W49F020 is programmed on a byte-by-byte basis. Program operation can only change logical data
"1" to logical data "0." The erase operation (changed entire data in main memory blocks and/or boot
block from "0" to "1") is needed before programming.
The program operation is initiated by a 4-word command cycle (see Command Codes for Byte
Programming). The device will internally enter the program operation immediately after the
byte-program command is entered. The internal program timer will automatically time-out (50 µS max. -
Publication Release Date: October 1999
- 3 - Revision A1
Preliminary W49F020
BP) when completing programming and return to normal read mode. Data polling and/or Toggle Bits
T
can be used to detect end of program cycle.
Hardware Data Protection
The integrity of the data stored in the W49F020 is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A
DD Power Up/Down Detection: The programming operation is inhibited when VDD is less than
(2) V
2.5V typical.
(3) Write Inhibit Mode: Forcing
prevents inadvertent writes during power-up or power-down periods.
(4) V
DD power-on delay: When VDD has reached its sense level, the device will automatically time-out
5 mS before any write (erase/program) operation.
Data Polling (DQ7)- Write Status Detection
The W49F020 features a data polling function which used to indicate the end of a program or erase
cycle. When the W49F020 is in the internal program or erase cycle, any attemption to read DQ
last word loaded will receive the complement of the true data. Once the program or erase cycle is
completed, DQ
become logical "1" or true data when the erase cycle has been completed.
7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and
Toggle Bit (DQ6)- Write Status Detection
In addition to data polling, the W49F020 provides another method for determining the end of a program
cycle. During the internal program or erase cycle, any consecutive attempts to read DQ
alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's
will stop. The device is then ready for the next operation.
WE pulse with less than 15 nS in duration will not initiate a write cycle.
OE low, CE high, or WE high will inhibit the write operation. This
7 of the
6 will produce
Product Identification
The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.
The manufacturer and device codes can be accessed by software or hardware operation. In software
access mode, a three-word (or JEDEC 3-word) command sequence can be used to access the product
ID. A read from address 0000H outputs the manufacturer code DA(hex); and a read from address
0001H outputs the device code 8C(hex) for W49F020. The product ID operation can be terminated by a
three-word command sequence or an alternated one-word command sequence (see Command
Definition table).
In the hardware access mode, access to the product ID will be activated by forcing
WE high, and raising A9 to 12 volts.
CE and OE low,
- 4 -
Preliminary W49F020
TABLE OF OPERATING MODES
Operating Mode Selection
(VHH = 12V ± 5%)
MODE PINS
CE OE WE
Read VIL VIL VIH AINDout
Write VIL VIH VIL AINDin
IH
Standby V
X X X High Z
Write Inhibit X VIL X X High Z/DOUT
X X V
IH X High Z/DOUT
Output Disable X VIH X X High Z
Product ID VIL VIL VIH
A0 = V
A9 = V
VIL VIL VIH
A0 = V
A9 = V
TABLE OF COMMAND DEFINITION
COMMAND
DESCRIPTION
Read 1
Chip Erase 6
Byte Program 4
Boot Block Lockout 6
Product ID Entry 3
Product ID Exit
Product ID Exit
Notes:
1. Address Format: A14−A0 (Hex); Data Format: DQ7-DQ0 (Hex)
2. Either one of the two Product ID Exit commands can be used.
Software Product Identification and Boot Block Lockout Detection Acquisition Flow
SOFTWARE PRODUCT
DETECTION EXIT (7)
Product
Identification
Entry (1)
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 90
to
address 5555
Pause 10 S
µ
Product
Identification
and Boot Block
Lockout Detection
Mode (3)
Read address = 00000
data = DA
Read address = 00001
data =8C
Read address = 00002
data in DQ0 = "1"/"0"
(2)
(2)
(4)
Product
Identification Exit(7)
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data F0
to
address 5555
Pause 10 S
Normal Mode
µ
(5)
Notes for software product identification/boot block lockout detection:
(1) Data Format: DQ7−DQ0 (Hex); Address Format: A14−A0 (Hex)
(2) A1−A17 = V
(3) The device does not remain in identification and boot block lockout detection mode if power down.
(4) If the output data in DQ0= " 1," the boot block programming lockout feature is activated; if the output data in DQ0= " 0," the lockout feature is
inactivated and the block can be programmed.
(5) The device returns to standard operation mode.
(6) Optional 1-word cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection.
; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.
3. There are two kinds of boot block in this device. The part number shown in the Ordering Information table is only for Bottom Boot
Block part, which is in the lower address range. For the requirement of the higher address range boot block, the Top Boot Block,
please contact Winbond FAE for details.
POWER
SUPPLY
CURRENT
MAX.
(mA)
STANDBY
DD
V
CURRENT
MAX.
A)
(
µ
32-pin TSOP (8 mm × 20 mm)
32-pin TSOP (8 mm × 20 mm)
32-pin TSOP (8 mm × 20 mm)
32-pin TSOP (8 mm × 20 mm)
PACKAGE CYCLE
1K
1K
10K
10K
- 18 -
PACKAGE DIMENSIONS
32-pin P-DIP
Preliminary W49F020
1E
2
A
A
L
32-pin PLCC
5
13
14
L
θ
Seating Plane
Dimension in inches
Symbol
Min. Nom. Max.Max.Nom.Min.
A
0.010
A
1
0.150
2
A
0.016
B
B1
c
32
1
S
e
G
D
B
1
e
1
B
H
E
E
324
30
1
20
b
1b
E
17
16
1A
Base Plane
Seating Plane
E
e
A
a
Symbol
29
D
H
D
21
2A
A
1
A
y
G D
Notes:
c
0.008
D
E
E
0.545
1
e
1
0.120
L
015
a
e
A
S
Notes:
1.Dimensions D Max. & S include mold flash or
tie bar burrs.
c
2.Dimension E1 does not include interlead flash.
3.Dimensions D & E1 include mold mismatch and
are determined at the mold parting line.
4.Dimension B1 does not include dambar
protrusion/intrusion.
5.Controlling dimension: Inches
6.General appearance spec. should be based on
final visual inspection spec.
Dimension in InchesDimension in mm
Min. Nom. Max.Max.Nom.Min.
A
0.020
A
1
A
2
1
0.016
0.008
0.547
0.447
0.490
D
0.390
E
0.585
D
0.485
E
0.075
y
θ
0.028
0.018
0.010
0.550
0.450
0.050
0.51
0.410
0.590
0.49
0.090
010100
b
b
c
D
E
e
G
G
H
H
L
1. Dimensions D & E do not include interlead flash.
2. Dimension b1 does not include dambar protrusion/intrusion.
3. Controlling dimension: Inches
4. General appearance spec. should be based on final
visual inspection sepc.
Dimension in mm
0.2105.33
0.25
0.155
0.160
3.81
3.94
14.99
4.06
0.41
0.46
0.56
0.20
0.25
15.49
15.24
14.10
13.9713.84
2.29 2.54 2.790.090 0.100
3.05
3.30
17.02
0.018
0.022
0.0501.27
0.0540.048
0.010
0.014
1.650 1.66041.91 42.16
0.610
0.6000.590
0.555
0.550
0.110
0.140
0.130
0.670
0.6500.63016.00 16.51
0.085
.
0.140
0.1150.105 0.110
0.0320.026
0.022
0.014
0.553
0.453
0.530
0.430
0.595
0.495
0.095
0.004
0.50
2.802.672.93
0.660.81
0.71
0.41
0.46
0.20
0.25
13.89
13.97
11.35
11.43
1.121.420.0440.056
1.27
12.9
12.45
9.91
10.41
14.86
14.99
12.32
12.45
1.91 2.29
3.56
0.56
0.35
14.05
11.51
13.46
10.92
15.11
12.57
2.41
0.10
1.371.22
0.36
3.56
150
2.16
Publication Release Date: October 1999
- 19 - Revision A1
Package Dimensions, continued
32-pin TSOP
M
e
0.10(0.004)
b
θ
L
L
1
Preliminary W49F020
H
D
D
c
E
A
A
2
1
A
Y
Dimension in Inches
Symbol
Min. Nom.
A
0.002
A
1
2
A
0.007 0.008
b
0.005 0.006
c
0.720 0.724
D
0.311 0.315
E
0.780 0.787
H
D
e
0.016 0.020
L
L
1
0.0000.004
Y
θ
Note:
Controlling dimension: Millimeters
__
__
____
__
0.020
__
0.031
__
1
3
Max.
0.047
0.006
0.0410.0390.037
0.009
0.007
0.728
0.319
0.795
0.024
__
__
18.30
19.80
5
Dimension in mm
Min. Nom.
__
__
0.05
0.95
0.17
0.20 0.23
0.12
0.15 0.17
18.40 18.50
7.90
8.00 8.10
20.00 20.20
__
0.50
0.40
0.50 0.60
__
0.80
__
0.00
1
3
Max.
1.20
0.15
1.051.00
__
__
0.10
5
- 20 -
Preliminary W49F020
VERSION HISTORY
VERSION DATE PAGE DESCRIPTION
A1 Oct. 1999 - Initial Issued
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798
Publication Release Date: October 1999
- 21 - Revision A1
Loading...
+ hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.