Rainbow Electronics W49F002U User Manual
W49F002U
256K × 8 CMOS FLASH MEMORY
GENERAL DESCRIPTION
The W49F002U is a 2-megabit, 5-volt only CMOS flash memory organized as 256K × 8 bits. The
device can be programmed and erased in-system with a standard 5V power supply. A 12-volt V
not required. The unique cell architecture of the W49F002U results in fast program/erase operations
with extremely low current consumption (compared to other comparable 5-volt flash memory
products). The device can also be programmed and erased using standard EPROM programmers.
FEATURES
•
•
Single 5-volt operations:
− 5-volt Read
− 5-volt Erase
− 5-volt Program
•
Fast Program operation:
− Byte-by-Byte programming: 35 µS (typ.)
•
Fast Erase operation: 100 mS (typ.)
•
Fast Read access time: 70/90/120 nS
•
Endurance: 10K cycles (typ.)
•
Ten-year data retention
•
Hardware data protection
•
One 16K byte Boot Block with Lockout
protection
•
Two 8K byte Parameter Blocks
Two Main Memory Blocks (96K, 128K) Bytes
•
Low power consumption
−
Active current: 25 mA (typ.)
−
Standby current: 20 µA (typ.)
•
Automatic program and erase timing with
internal V
•
End of program or erase detection
− Toggle bit
− Data polling
•
Latched address and data
•
TTL compatible I/O
•
JEDEC standard byte-wide pinouts
•
Available packages: 32-pin DIP and 32-pin
TSOP and 32-pin-PLCC
PP
generation
PP
is
Publication Release Date: April 2000
- 1 - Revision A2
W49F002U
6
Q
PIN CONFIGURATIONS
1
RESET
2
A16
3
A15
4
A12
5
A7
6
A6
7
A11
A13
A14
A17
WE
V
RESET
A16
A15
A12
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
2
A9
3
A8
5
8
DD
9
10
11
12
13
A7
14
A6
15
A5
16
A4
32-pin
8
DIP
9
10
11
12
13
14
15
16
/
R
E
A
A
V
A
S
1
1
D
W
E
1
T
2
6
D
E
5
5
6
7
8
32-pin
PLCC
9
10
11
12
13
D
D
G
D
D
Q
Q
N
Q
Q
1
2
D
4
3
32-pin
TSOP
BLOCK DIAGRAM
V
32
V
DD
31
WE
30
A17
29
A14
28
A13
27
A8
26
A9
25
A11
24
OE
23
A10
22
CE
21
DQ7
20
DQ6
19
DQ5
18
DQ4
17
DQ3
/
A
1
7
3031321234
29
A14
28
A13
27
A8
26
A9
25
A11
24
OE
23
A10
22
CE
21
DQ7
20191817161514
D
D
Q
Q
5
6
32
OE
A10
31
30
CE
29
DQ7
DQ6
28
DQ5
27
DQ4
26
DQ3
25
GND
24
2
D
23
22
DQ1
21
DQ0
20
A0
19
A1
A2
18
17
A3
DD
V
SS
CE
WE
OE
CONTROL
OUTPUT
BUFFER
RESET
BOOT BLOCK
16K BYTES
PARAMETER
BLOCK1
8K BYTES
PARAMETER
BLOCK2
8K BYTES
MAIN MEMORY
BLOCK1
96K BYTES
MAIN MEMORY
BLOCK2
128K BYTES
A17
A0
.
DECODER
.
PIN DESCRIPTION
SYMBOL PIN NAME
RESET
A0−A17
DQ0−DQ7
CE
OE
WE
VDD Power Supply
GND Ground
Reset
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
DQ0
.
.
DQ7
3FFFF
3C000
3BFFF
3A000
39FFF
38000
37FFF
20000
1FFFF
00000
- 2 -
W49F002U
FUNCTIONAL DESCRIPTION
Read Mode
The read operation of the W49F002U is controlled by
the host to obtain data from the outputs.
is de-selected and only standby power will be consumed.
data from the output pins. The data bus is in high impedance state when either
Refer to the timing waveforms for further details.
CE
is used for device selection. When CE is high, the chip
Reset Operation
The reset input pin can be used in some application. When
in normal operation mode. When
at high impedance state. As the high state re-asserted to the RESET pin, the device will return to
read or standby mode, it depends on the control signals. When the system drives the RESET pin low
for at least a period of 500 nS, the device immediately terminates any operation in progress duration
of the
applying the 12V to
lockout function is enabled.
RESET pulse. The other function for RESET pin is temporary reset the boot block. By
RESET
RESET
pin, the boot block can be reprogrammed even though the boot block
pin is at low state, it will halts the device and all outputs are
Boot Block Operation
There is one 16K-byte boot block in this device, which can be used to store boot code. It is located in
the last 16K bytes with the address range of the boot block is 3C000(hex) to 3FFFF(hex).See
Command Code sequence for Boot Block Lockout Enable for the specific code. Once this feature is
set the data for the designated block cannot be erased or programmed (programming lockout); other
memory locations can be changed with the regular programming method. Once the boot block
programming lockout feature is activated, the chip erase function can no longer erase the boot block.
There is one condition that the lockout feature can be overridden. Just apply 12V to
lockout feature will temporarily be inactivated and the block can be erased/programmed. Once the
RESET
In order to detect whether the boot block feature is set on the 16K-bytes block, users can perform
software command code sequence: enter the product identification mode (see Command Codes for
Identification/Boot Block Lockout Detection for specific code), and then read from address "0002
(hex)". If the DQ
DQ0
erased/programmed.
To return to normal operation, perform a three-byte command code sequence (or an alternate singlebyte command) to exit the identification mode. For the specific code, see Command Code for
Identification/Boot Block Lockout Detection.
pin return to TTL level, the lockout feature will be activated again.
0
of output data is "1," the boot block programming lockout feature is activated; if the
of output data is "0 ," the lockout feature is inactivated and the block can be
CE
and OE, both of which have to be low for
OE
is the output control and is used to gate
CE
or OE is high.
RESET pin is at high state, the device is
RESET
pin, the
Chip Erase Operation
The chip-erase mode can be initiated by a six-byte command code sequence. After the command
loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be
completed as fast as 100 mS (typical). The host system is not required to provide any control or
timing during this operation. The entire memory array will be erased to FF hex. by the chip erase
Publication Release Date: April 2000
- 3 - Revision A2
W49F002U
operation if the boot block programming lockout feature is not activated. Once the boot block lockout
feature is activated, the whole chip erase function will erase the two main memory blocks and the two
parameter blocks but not the boot block. The device will automatically return to normal read mode
after the erase operation. Data polling and/or Toggle Bits can be used to detect end of erase cycle.
Sector Erase Operation
There are four sectors: two main memory blocks and two parameters blocks which can be erased
individually by initiating a six-byte command code sequence. Sector address is latched on the falling
edge of
in this cycle. After the command loading cycle, the device enters the internal sector erase mode,
which is automatically timed and will be completed as fast as 100 mS (typical). The host system does
not require to provide any control or timing during this operation. The device will automatically return
to normal read mode after the erase operation. Data polling and/or Toggle Bits can be used to detect
the end of erase cycle.
When different sector address is loaded in the sixth cycle for sector erase command, the
correspondent sectors will be erased automatically; that these sections will be erased independedntly.
For detail sector to be erased information, please refer to the
Program Operation
The W49F002U is programmed on a byte-by-byte basis. Program operation can only change logical
data "1" to logical data "0". The erase operation (changed entire data in two main memory blocks and
two parameter blocks and/or boot block from "0" to "1") is needed before programming.
The program operation is initiated by a 4-byte command code sequence (see Command Codes for
Byte Programming). The device will internally enter the program operation immediately after the byteprogram command is entered. The internal program timer will automatically time-out (50 µS max. T
be used to detect end of program cycle.
WE
signal in the sixth cycle while the data input "30(hex)" is latched at the rising edge of WE
Table of Command Definition
BP
). Once completed, the device returns to normal read mode. Data polling and/or Toggle Bits can
.
Hardware Data Protection
The integrity of the data stored in the W49F002U is also hardware protected in the following ways:
WE
(1) Noise/Glitch Protection: A
DD
(2) V
2.5V typical.
(3) Write Inhibit Mode: Forcing
prevents inadvertent writes during power-up or power-down periods.
(4) V
5 mS before any write (erase/program) operation.
Power Up/Down Detection: The programming operation is inhibited when VDD is less than
DD
power-on delay: When VDD has reached its sense level, the device will automatically time-out
pulse of less than 15 nS in duration will not initiate a write cycle.
OE
low, CE high, or WE high will inhibit the write operation. This
Data Polling (DQ7)- Write Status Detection
The W49F002U includes a data polling feature to indicate the end of a program or erase cycle.
When the W49F002U is in the internal program or erase cycle, any attempt to read DQ
byte loaded will receive the complement of the true data. Once the program or erase cycle is
completed, DQ
and become logical "1" or true data when the erase cycle has been completed.
- 4 -
7
will show the true data. Note that DQ7 will show logical "0" during the erase cycle,
7
of the last
Toggle Bit (DQ6)- Write Status Detection
W49F002U
In addition to data polling, the W49F002U provides another method for determining the end of a
program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ
6
will
produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between
0's and 1's will stop. The device is then ready for the next operation.
Product Identification
The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.
The manufacturer and device codes can be accessed by software or hardware operation. In the
software access mode, a three-byte (or JEDEC 3-byte) command sequence can be used to access
the product ID. A read from address 0000H outputs the manufacturer code DA(hex). A read from
address 0001H outputs the device code 0B(hex). The product ID operation can be terminated by a
three-byte command code sequence or an alternate one-byte command code sequence (see
Command Definition table).
In the hardware access mode, access to the product ID is activated by forcing
CE
and OE low, WE
high, and raising A9 to 12 volts.
TABLE OF OPERATING MODES
Operating Mode Selection
(VHH = 12V ± 5%)
MODE PINS
Read VIH VIL VIL VIH AIN Dout
Write VIH VIL VIH VIL AIN Din
Standby VIH VIH X X X High Z
Write Inhibit VIH X VIL X X High Z/DOUT
V
Output Disable VIH X VIH X X High Z
Reset Mode VIL X X X X High Z
Product ID VIH VIL VIL VIH
V
RESET
CE OE WE
IH
X X VIH X High Z/DOUT
IH
VIL VIL VIH
ADDRESS DQ.
A0 = V
A9 = V
A0 = V
A9 = V
IL
; A1−A17 = VIL;
HH
IH
; A1−A17 = VIL;
HH
Manufacturer Code DA (Hex)
Device Code 0B (Hex)
Publication Release Date: April 2000
- 5 - Revision A2
TABLE OF COMMAND DEFINITION
W49F002U
(1)
COMMAND NO.
OF
DESCRIPTION
Cycles Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Read 1 AIN D
1ST
CYCLE
OUT
2ND
CYCLE
3RD
CYCLE
4TH
CYCLE
5TH
CYCLE
6TH
CYCLE
Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10
Sector Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA
(3)
30
Byte Program 4 5555 AA 2AAA 55 5555 A0 AIN DIN
Boot Block Lockout 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40
Product ID Entry 3 5555 AA 2AAA 55 5555 90
Product ID Exit
Product ID Exit
Notes:
1. Address Format: A14−A0 (Hex); Data Format: DQ7-DQ0 (Hex)
2. Either one of the two Product ID Exit commands can be used.
3. SA means: Sector Address
If SA is within 3C000 to 3FFFF (Boot Block address range), and the Boot Block programming lockout feature is activated,
nothing will happen and the device will go back to read mode after 100nS.
If the Boot Block programming lockout feature is not activated, this command will erase Boot Block.
If SA is within 3A000 to 3BFFF (Parameter Block1 address range), this command will erase PB1.
If SA is within 38000 to 39FFF (Parameter Block2 address range), this command will erase PB2.
If SA is within 20000 to 37FFF (Main Memory Block1 address range), this command will erase MMB1.
If SA is within 00000 to 1FFFF (Main Memory Block2 address range), this command will erase MMB2.
(2)
3 5555 AA 2AAA 55 5555 F0
(2)
1 XXXX F0
- 6 -
Command Codes for Byte Program
COMMAND SEQUENCE ADDRESS DATA
0 Write 5555H AAH
1 Write 2AAAH 55H
2 Write 5555H A0H
3 Write Programmed-address Programmed-data
Byte Program Flow Chart
Byte Program
Command Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
W49F002U
Load data A0
to
address 5555
Load data Din
to
programmed-
address
Pause T
BP
Exit
Notes for software program code:
Data Format: DQ7−DQ0 (Hex)
Address Format: A14−A0 (Hex)
Publication Release Date: April 2000
- 7 - Revision A2
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