Rainbow Electronics W29EE512 User Manual

W29EE512

64K × 8 CMOS FLASH MEMORY

GENERAL DESCRIPTION

The W29EE512 is a 512K bit, 5-volt only CMOS flash memory organized as 64K × 8 bits. The device
can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not
required. The unique cell architecture of the W29EE512 results in fast program/erase operations with
extremely low current consumption (compared to other comparable 5-volt flash memory products).
The device can also be programmed and erased using standard EPROM programmers.

FEATURES

•

Single 5-volt program and erase operations

•

Fast page-write operations

− 128 bytes per page

− Page program cycle: 10 mS (max.)

− Effective byte-program cycle time: 39 µS

− Optional software-protected data write

•

Fast chip-erase operation: 50 mS

•

Read access time: 70/90/120 nS

•

Typical page program/erase cycles: 1K/10K

•

Ten-year data retention

•

Software and hardware data protection

•

Low power consumption

−

Active current: 50 mA (max.)

−

Standby current: 100 µA (max.)

•

Automatic program timing with internal VPP

generation

•

End of program detection

−

Toggle bit

−

Data polling

•

Latched address and data

•

TTL compatible I/O

•

JEDEC standard byte-wide pinouts

•

Available packages: 32-pin PLCC, TSOP and
VSOP

Publication Release Date: April 2000

- 1 - Revision A6

W29EE512

E

1

2

3

678

DQ1

DQ2

V

NC

A13

CC

1

3

456

DQ1

DQ2

VWENC

CC

CE

OE

WE

PIN CONFIGURATIONS

A

V

/

A

1

C

W

1

N
C

32-pin
PLCC

G

D

N

Q

D

3

32-pin
TSOP

32-pin
VSOP

N

C

C

3031321234

1817161514

2019

D

D

D

Q

Q

Q

4

5

6

2NC

5

5

A7

6

A6

7

A5

8

A4

9

A3

10

A2

11

A1

12

A0

13

DQ0

D

D

Q

Q

1

2

A11

A9
A8

5

A14

WE

9

NC

10

NC

11

A15

12

A12

13

A7

14

A6

15

A5

16

A4

A11

2

A9

A8
A13
A14

8
9

NC

10

NC

11

A15

12

A12

13

A7

14

A6

15

A5

A4

16

BLOCK DIAGRAM

V

DD

V

SS

29

A14

28

A13

27

A8

26

A9

25

A11

24

OE

23

A10

22

CE

21

DQ7

CE
OE

WE

A0

.
.

CONTROL

DECODER

OUTPUT
BUFFER

CORE

ARRAY

A15

32

OE
A10

31
30

CE
DQ7

29

DQ6

28

DQ5

27

DQ4

26

DQ3

25

GND

24
23
22

DQ0

21
20

A0
A1

19

A2

18

A3

17

32

OE
A10

31
30

CE

29

DQ7
DQ6

28

DQ5

27
26

DQ4

25

DQ3
GND

24
23
22
21

DQ0

20

A0

19

A1

18

A2

17

A3

PIN DESCRIPTION

SYMBOL PIN NAME

A0−A15

DQ0−DQ7

CC

V

GND Ground

Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
Power Supply

NC No Connection

DQ0

.
.

DQ7

- 2 -

W29EE512

FUNCTIONAL DESCRIPTION

Read Mode

The read operation of the W29EE512 is controlled by CE and OE, both of which have to be low for
the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip
is de-selected and only standby power will be consumed. OE is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either CE or OE is high.

Refer to the timing waveforms for further details.

Page Write Mode

The W29EE512 is programmed on a page basis. Every page contains 128 bytes of data. If a byte of
data within a page is to be changed, data for the entire page must be loaded into the device. Any byte
that is not loaded will be erased to "FFh" during programming of the page.

The write operation is initiated by forcing CE and WE low and OE high. The write procedure consists
of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the device.
Step 2 is an internal programming cycle, during which the data in the page buffers are simultaneously
written into the memory array for non-volatile storage.

During the byte-load cycle, the addresses are latched by the falling edge of either CE or WE,
whichever occurs last. The data are latched by the rising edge of either CE or WE, whichever occurs

first. If the host loads a second byte into the page buffer within a byte-load cycle time (T

µ

S, after the initial byte-load cycle, the W29EE512 will stay in the page load cycle. Additional bytes
can then be loaded consecutively. The page load cycle will be terminated and the internal
programming cycle will start if no additional byte is loaded into the page buffer A7 to A15 specify the
page address. All bytes that are loaded into the page buffer must have the same page address. A0 to
A6 specify the byte address within the page. The bytes may be loaded in any order; sequential loading
is not required.

In the internal programming cycle, all data in the page buffers, i.e., 128 bytes of data, are written
simultaneously into the memory array. Before the completion of the internal programming cycle, the
host is free to perform other tasks such as fetching data from other locations in the system to prepare
to write the next page.

BLC

) of 200

Software-protected Data Write

The device provides a JEDEC-approved optional software-protected data write. Once this scheme is
enabled, any write operation requires a series of three-byte program commands (with specific data to
a specific address) to be performed before the data load operation. The three-byte load command
sequence begins the page load cycle, without which the write operation will not be activated. This
write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by
noise during system power-up and power-down.

The W29EE512 is shipped with the software data protection enabled. To enable the software data
protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The
device will then enter the software data protection mode, and any subsequent write operation must be
preceded by the three-byte program command cycle. Once enabled, the software data protection will
remain enabled unless the disable commands are issued. A power transition will not reset the
software data protection feature. To reset the device to unprotected mode, a six-byte command
sequence is required.

Publication Release Date: April 2000

- 3 - Revision A6

W29EE512

Hardware Data Protection

The integrity of the data stored in the W29EE512 is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.

CC

(2) V

2.5V.
(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This

prevents inadvertent writes during power-up or power-down periods.

Data Polling (DQ7)-Write Status Detection

The W29EE512 includes a data polling feature to indicate the end of a programming cycle. When the
W29EE512 is in the internal programming cycle, any attempt to read DQ7 of the last byte loaded
during the page/byte-load cycle will receive the complement of the true data. Once the programming
cycle is completed. DQ7 will show the true data.

Toggle Bit (DQ6)-Write Status Detection

In addition to data polling, the W29EE512 provides another method for determining the end of a
program cycle. During the internal programming cycle, any consecutive attempts to read DQ6 will
produce alternating 0's and 1's. When the programming cycle is completed, this toggling between 0's
and 1's will stop. The device is then ready for the next operation.

Power Up/Down Detection: The programming operation is inhibited when VCC is less than

5-Volt-only Software Chip Erase

The chip-erase mode can be initiated by a six-byte command sequence. After the command loading
cycles, the device enters the internal chip erase mode, which is automatically timed and will be
completed in 50 mS. The host system is not required to provide any control or timing during this
operation.

Product Identification

The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.

The manufacturer and device codes can be accessed by software or hardware operation. In the
software access mode, a six-byte command sequence can be used to access the product ID. A read
from address 0000H outputs the manufacturer code (DAh). A read from address 0001H outputs the
device code (C8h). The product ID operation can be terminated by a three-byte command sequence.

In the hardware access mode, access to the product ID is activated by forcing CE and OE low, WE
high, and raising A9 to 12 volts.

- 4 -

TABLE OF OPERATING MODES

CE OE WE

Operating Mode Selection

(Operating Range = 0 to 70° C (Ambient Temperature), VCC = 5V ±10%, VSS = 0V, VHH = 12V)

MODE PINS

W29EE512

ADDRESS DQ.

IL

IL

IH

Read V
Write V
Standby V

IL

IH

Write Inhibit X V

V

IH

V

X X X High Z

IL

X X V

IH

Output Disable X V
5-Volt Software Chip Erase V
Product ID V

V

IL
IL

IL

IH

V

IL

V

IL

V

V

V

V

IN

A

IL

IN

V

A

Dout
Din

X X High Z/D

IH

X High Z/D

X X High Z

IL

V

IH

IH

IN

A
A0 = VIL; A

HH

A9 = V
A0 = VIH; A

HH

A9 = V

1

−

A15 = VIL;

1

−

A15 = VIL;

IN

D
Manufacturer Code

DA (Hex)
Device Code

C8 (Hex)

OUT
OUT

Publication Release Date: April 2000

- 5 - Revision A6

W29EE512

Software Data Protection

Command Codes for Software Data Protection

BYTE SEQUENCE TO ENABLE PROTECTION TO DISABLE PROTECTION

0 Write 5555H AAH 5555H AAH
1 Write 2AAAH 55H 2AAAH 55H
2 Write 5555H A0H 5555H 80H
3 Write - - 5555H AAH
4 Write - - 2AAAH 55H
5 Write - - 5555H 20H

Software Data Protection Acquisition Flow

ADDRESS DATA ADDRESS DATA

Software Data Protection
Enable Flow

Disable Flow

(Optional page-load

Notes for software program code:
Data Format: DQ7−DQ0 (Hex)

Address Format: A14−A0 (Hex)

operation)

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data A0

to

address 5555

Sequentially load

up to 128 bytes

of page data

Pause 10 mS

Exit

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 20

to

address 5555

Pause 10 mS

Exit

- 6 -

Command Codes for Software Chip Erase

BYTE SEQUENCE ADDRESS DATA

0 Write 5555H AAH
1 Write 2AAAH 55H
2 Write 5555H 80H
3 Write 5555H AAH
4 Write 2AAAH 55H
5 Write 5555H 10H

Software Chip Erase Acquisition Flow

Load data AA

address 5555

Load data 55

address 2AAA

W29EE512

to

to

Notes for software chip erase:
Data Format: DQ7−DQ0 (Hex)
Address Format: A14−A0 (Hex)

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 10

to

address 5555

Pause 50 mS

Exit

Publication Release Date: April 2000

- 7 - Revision A6

W29EE512

Command Codes for Product Identification

BYTE

SEQUENCE

0 Write 5555H AAH 5555H AAH 5555H AAH
1 Write 2AAAH 55H 2AAAH 55H 2AAAH 55H
2 Write 5555H 90H 5555H 80H 5555H F0H
3 Write - - 5555H AAH - ­4 Write - - 2AAAH 55H - ­5 Write - - 5555H 60H - -

Software Product Identification Acquisition Flow

ALTERNATE SOFTWARE (5)
PRODUCT IDENTIFICATION

ADDRESS DATA ADDRESS DATA ADDRESS DATA

Product Identification Entry (1)

ENTRY

Pause 10 µS Pause 10 µS Pause 10 µS

Product Identification Mode (2,3)

Load data AA

to

address 5555

SOFTWARE PRODUCT

IDENTIFICATION ENTRY

Product Identification Exit (1)

SOFTWARE PRODUCT

IDENTIFICATION EXIT

Load data 55

to

address 2AAA

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 60

to

address 5555

Pause 10 S

µ

Read address = 0

data = DA

Read address = 1

data = C8

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data FO

to

address 5555

Pause 10 S

Normal Mode

µ

(4)

Notes for software product identification:
(1) Data format: DQ7−DQ0 (Hex); address format: A14−A0 (Hex).
(2) A1−A16 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.
(3) The device does not remain in identification mode if power down.
(4) The device returns to standard operation mode.
(5) This product supports both the JEDEC standard 3 byte command code sequence and original 6 byte command code
sequence. For new designs, Winbond recommends that the 3 byte command code sequence be used.

- 8 -

DC CHARACTERISTICS

CE

CE

CE

Output High Voltage

Absolute Maximum Ratings

PARAMETER RATING UNIT

Power Supply Voltage to V
Operating Temperature 0 to +70
Storage Temperature -65 to +150
D.C. Voltage on Any Pin to Ground Potential except A9 -0.5 to V
Transient Voltage (¡Õ20 nS ) on Any Pin to Ground Potential

ss

Potential -0.5 to +7.0 V

CC

-1.0 to V

CC

W29EE512

°C
°C

+1.0 V
+1.0 V

Voltage on A9 and OE Pin to Ground Potential

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.

Operating Characteristics

(VCC = 5.0V ±10%, VSS = 0V, TA = 0 to 70° C)

Power Supply

Current

Standby Vcc

Current (TTL Input)

Standby Vcc

Current (CMOS

Input)

Input Leakage

Current

Output Leakage

Current

Input Low Voltage V

Input High Voltage V

Output Low Voltage V

Output High Voltage V

CMOS

PARAMETER SYM.

CC

I

ISB1

ISB2

LI

I

LO

I

IL

IH

OL
OH1
OH2

V

-0.5 to 12.5 V

TEST CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

= OE = VIL, WE = VIH, all I/Os open

- - 50 mA

Address inputs = VIL/VIH, at f = 5 MHz

= VIH, all I/Os open

IH

Other inputs = VIL/V

CC

= V

-0.3V, all I/Os open

Other inputs = V

IN

V

= GND to V

IN

V

= GND to V

OL

I

= 2.1 mA - - 0.45 V

OH

I

= -0.4 mA 2.4 - - V

IOH = -100 µA; VCC = 4.5V

CC

-0.3V/GND

CC

CC

- - - 0.8 V

- 2.0 - - V

- 2 3 mA

- 20 100

- - 10

- - 10

4.2 - - V

µ

A

µ

A

µ

A

Publication Release Date: April 2000

- 9 - Revision A6

W29EE512

Power-up Timing

PARAMETER SYMBOL TYPICAL UNIT

Power-up to Read Operation TPU.READ 100
Power-up to Write Operation TPU.WRITE 5 mS

CAPACITANCE

(VCC = 5.0V, TA = 25° C, f = 1 MHz)

PARAMETER SYMBOL CONDITIONS MAX. UNIT

I/O

I/O Pin Capacitance C
Input Capacitance C

IN

AC CHARACTERISTICS

AC Test Conditions

PARAMETER CONDITIONS

Input Pulse Levels 0V to 3V
Input Rise/Fall Time
Input/Output Timing Level 1.5V/1.5V
Output Load 1 TTL Gate and CL = 100 pF/30 pF

I/O

V

= 0V 12 pF

VIN = 0V 6 pF

<

5 nS

µ

S

AC Test Load and Waveform

D

OUT

(For 90 nS/120 nS)

100 pF
30 pF

(For 70 nS)

Input

3V

0V

- 10 -

1.5V

Test Point

+5V

Output

1.5V

1.8

Kohm

1.3

Kohm

Test Point

Read Cycle Timing Parameters

CE

OE

WE

WE

OE

OE

CE

WE

WE

(VCC = 5.0V ±10%, VCC = 5.0 ±5% for 70 nS, VSS = 0V, TA = 0 to 70° C)

PARAMETER SYM. W29EE512-70 W29EE512-90 W29EE512-12 UNIT

W29EE512

Read Cycle Time T
Chip Enable Access Time T
Address Access Time T
Output Enable Access Time T

CHZ

High to High-Z Output

High to High-Z Output

T

T

OHZ

Output Hold from Address Change T

MIN. MAX. MIN. MAX. MIN. MAX.

RC

70 - 90 - 120 - nS

CE

- 70 - 90 - 120 nS

AA

- 70 - 90 - 120 nS

OE

- 35 - 40 - 50 nS

- 25 - 25 - 30 nS

- 25 - 25 - 30 nS

OH

0 - 0 - 0 - nS

Byte/Page-write Cycle Timing Parameters

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

WC

T

T
T
T

T

T

T

AS
AH
CS

CH

OES

OEH

CP

WP

WPH

DS
DH

BLC

- - 10 mS

0 - - nS

50 - - nS

0 - - nS
0 - - nS
0 - - nS

0 - - nS
90 - - nS
90 - - nS

100 - - nS

35 - - nS

0 - - nS

- - 200

µ

S

Write Cycle (Erase and Program) T
Address Setup Time T
Address Hold Time T

and CE Setup Time

and CE Hold Time
High Setup Time
High Hold Time

Pulse Width

Pulse Width

High Width

Data Setup Time T
Data Hold Time T
Byte Load Cycle Time T

Notes: All AC timing signals observe the following guidelines for determining setup and hold times:

(1) High level signal's reference level is VIH.

(2) Low level signal's reference level is VIL.

Publication Release Date: April 2000

- 11 - Revision A6

W29EE512

DATA

OE

OE

OE

OE

OE

Polling Characteristics

(1)

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

T
T

DH
OEH

OE
WR

Data Hold Time T

Hold Time

(2)

to Output Delay

Write Recovery Time T

Notes:
(1) These parameters are characterized and not 100% tested.
(2) See TOE spec in A.C. Read Cycle Timing Parameters.

Toggle Bit Characteristics

(1)

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Data Hold Time T

Hold Time

(2)

to Output Delay
High Pulse

Write Recovery Time T

Notes:
(1) These parameters are characterized and not 100% tested.

(2) See TOE spec in A.C. Read Cycle Timing Parameters

DH
OEH

T

OE

T

OEHP

T

WR

.

10 - - nS
10 - - nS

- - - nS

0 - - nS

10 - - nS
10 - - nS

- - - nS

150 - - nS

0 - - nS

- 12 -

TIMING WAVEFORMS

WE

OEH

Read Cycle Timing Diagram

Address A15-0

CE

OE

V

WE

DQ7-0

IH

High-Z

W29EE512

T

RC

T

CE

T

OE

T

OHZ

T

OH

Data Valid

TAA

Data Valid

T

CHZ

High-Z

Controlled Write Cycle Timing Diagram

T

AS

Address A15-0

CE

OE

WE

DQ7-0

T

CS

T

OES

T

T

AH

T

CH

T

T

T

WP

T

DS

Data Valid

WPH

T

DH

WC

Internal write starts

Publication Release Date: April 2000

- 13 - Revision A6

Timing Waveforms, continued

CE

Controlled Write Cycle Timing Diagram

AS

T

Address A15-0

CE

T

OES

OE

WE

DQ7-0

High Z

W29EE512

T

T

AH

T

T

CP

Data Valid

T

DS

CPH

T

OEH

T

DH

Internal write starts

WC

Page Write Cycle Timing Diagram

Address A15-0

DQ7-0

CE

OE

WE

WP

T

T

WPH

Byte 0 Byte 1

- 14 -

BLC

T

Byte 2

Byte N-1

WC

T

Byte N

Internal write starts

Timing Waveforms, continued

DATA

Polling Timing Diagram

Address A15-0

WE

CE

OE

DQ7

W29EE512

TOEH

T

DH

T

OE

HIGH-Z

T

WR

Toggle Bit Timing Diagram

WE

CE

OE

DQ6

OEH

T

DH

T

OE

T

HIGH-Z

TWR

Publication Release Date: April 2000

- 15 - Revision A6

Timing Waveforms, continued

Page Write Timing Diagram Software Data Protection Mode

Byte/page load
cycle starts

Address A15-0

Three-byte sequence for

software data protection mode

5555

2AAA

5555

W29EE512

T

WC

DQ7-0

CE

OE
WE

AA 55 A0

T

T

WP

SW0

BLC

T

WPH

SW1

SW2

Word 0

Reset Software Data Protection Timing Diagram

Six-byte sequence for resetting

software data protection mode

Address A15-0

DQ7-0

5555 2AAA

AA

5555

55 80 AA

5555 2AAA 5555

Word N-1

55

Word N
(last word)

20

Internal write starts

WC

T

CE

OE

WE

T

WP

SW0

T

BLC

WPH

T

SW1

SW2

- 16 -

SW3

SW4

SW5

Internal programming starts

Timing Waveforms, continued

5-Volt-only Software Chip Erase Timing Diagram

W29EE512

Address A15-0

DQ7-0

CE

OE

WE

5555 2AAA 5555

55 80

AA

T

WP

SW0

T

BLC

T

WPH

SW2

SW1

Six-byte code for 5V-only

software chip erase

2AAA

5555

AA

SW3 SW4 SW5

T

WC

5555

55

10

Internal programming starts

Publication Release Date: April 2000

- 17 - Revision A6

ORDERING INFORMATION

ACCESS

S)

W29EE512

PART NO.

TIME

(n

W29EE512P-70 70 50 100 32-pin PLCC 1K
W29EE512P-90 90 50 100 32-pin PLCC 1K
W29EE512P-12 120 50 100 32-pin PLCC 1K
W29EE512T-70 70 50 100 Type one TSOP 1K
W29EE512T-90 90 50 100 Type one TSOP 1K
W29EE512T-12 120 50 100 Type one TSOP 1K
W29EE512Q-70 70 50 100 Type one VSOP 1K
W29EE512Q-90 90 50 100 Type one VSOP 1K
W29EE512P-70B 70 50 100 32-pin PLCC 10K
W29EE512P-90B 90 50 100 32-pin PLCC 10K
W29EE512P-12B 120 50 100 32-pin PLCC 10K
W29EE512T-70B 70 50 100 Type one TSOP 10K
W29EE512T-90B 90 50 100 Type one TSOP 10K
W29EE512T-12B 120 50 100 Type one TSOP 10K
W29EE512Q-70B 70 50 100 Type one VSOP 10K
W29EE512Q-90B 90 50 100 Type one VSOP 10K

POWER SUPPLY

CURRENT MAX.

(mA)

STANDBY VCC

CURRENT MAX.

(µA)

PACKAGE CYCLE

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.

- 18 -

PACKAGE DIMENSIONS

32-pin PLCC

H

E

E

1

324

30

5

13

14 20

L

e

θ

Seating Plane

b

1b

EG

W29EE512

0.140

0.1150.105 0.110

0.0320.026

0.022

0.014

0.553

0.453

0.530

0.430

0.595

0.495

0.095

0.004

°

10

Dimension In mm

0.50

2.802.67 2.93

0.66 0.81

0.71

0.41

0.46

0.20

0.25

13.89

13.97

11.35

11.43

1.12 1.420.044 0.056

1.27

12.95

12.45

9.91

10.41

14.86

14.99

12.32

12.45

1.91 2.29

°

0

14.05

11.51

13.46

10.92

15.11

12.57

3.56

0.56

0.35

2.41

0.10

°

10

Dimension In Inches

Symbol

29

D

D

H D

21

G

c

Min. Nom. Max. Max.Nom.Min.

A

0.020

A

1

A

2

b

1

0.016

b

0.008

c

0.547

D

0.447

E

e

0.490

GD

0.390

G

E

0.585

D

H

0.485

HE

0.075

L

y

°

0

θ

0.028

0.018

0.010

0.550

0.450

0.050

0.510

0.410

0.590

0.490

0.090

Notes:

2A

A

1

A

y

1. Dimensions D & E do not include interlead flash.

2. Dimension b does not include dambar protrusion/intrusion.

3. Controlling dimension: Inches.

4. General appearance spec. should be based on fina visual
inspection sepc.

32-pin TSOP

H

D

D

c

M

e

E

0.10(0.004)

b

A

A

θ

L

L

1

2

A

1

Y

- 19 - Revision A6

Symbol

A
A
A

b

c
D
E

H
e

L
L

Y

θ

1

2

D

1

Dimension In Inches

Min. Nom.

__

__

__

0.002

0.037

0.039

0.007 0.008

0.005 0.006

0.720 0.724

0.311 0.315

0.780 0.787

__

0.020

0.016 0.020

__

0.031

0.000 0.004
1

3

Dimension In mm

0.20 0.23

0.15 0.17

18.40 18.50

8.00 8.10

20.00 20.20

0.50

0.50 0.60

0.80

1

Max.

__

1.20

__

0.15

1.051.00

__

__

____

0.10
5

3

Min. Nom.

Max.

__

0.047

0.006

0.05

0.95

0.041

0.17

0.009

0.12

0.007

18.30

0.728

7.90

0.319

19.80

0.795

__

__

0.40

0.024

__

__

0.00

5

Note:
Controlling dimension: Millimeters

Publication Release Date: April 2000

Package Dimensions, continued

32-pin VSOP

M

e

0.10(0.004)

b

θ

L

W29EE512

H

D

D

A

A

1

E

Y

Dimension In Inches

Symbol

Min. Nom.

__

A

0.002

A

1

b

0.006 0.008

D

0.484 0.488

0.311 0.315

E

0.543 0.551

H

D

__

e

0.020 0.024

L

0.004 0.008

Y

0 5

θ

Note:
Controlling dimension: Millimeters

__
__

0.020

__

Max.

0.047

0.006

0.010

0.492

0.319

0.559

__

0.028

Dimension In mm

Min. Nom.

__

__

__

0.05

0.15

0.20 0.25

12.30

12.40 12.50

7.90

8.00 8.10

13.80

14.00

__

0.50

0.50

0.60 0.70

____

0.10

__

0

Max.

1.20

0.15

14.20

__

0.20
5

- 20 -

VERSION HISTORY

VERSION DATE PAGE DESCRIPTION

A5 Mar. 1998 6 Add. pause 10 mS

7 Add. pause 50 mS

8
1, 2, 18, 19 Eliminate 600 mil DIP, 450 mil SOP packages

A6 Apr. 2000 1, 2, 18, 20 Add 32-pin VSOP package

3, 11

Correct the time from 10 mS to 10 µS

Change Byte Load Cycle Time from 150 µS to 200 µS

W29EE512

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: [phone]
FAX: [phone]
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: [phone]
FAX: [phone]

Note: All data and specifications are subject to change without notice.

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: [phone]
FAX: [phone]

Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.

2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: [phone]

FAX: [phone]

Publication Release Date: April 2000

- 21 - Revision A6