Rainbow Electronics W29C040 User Manual

W29C040

512K × 8 CMOS FLASH MEMORY

GENERAL DESCRIPTION

The W29C040 is a 4-megabit, 5-volt only CMOS page mode EEPROM organized as 512K × 8 bits.
The device can be written (erased and programmed) in-system with a standard 5V power supply. A
12-volt VPP is not required. The unique cell architecture of the W29C040 results in fast write (erase/
program) operations with extremely low current consumption compared to other comparable 5-volt
flash memory products. The device can also be written (erased and programmed) by using standard
EPROM programmers.

FEATURES

• Single 5-volt write (erase and program)

operations

• Fast page-write operations

− 256 bytes per page

− Page write (erase/program) cycle: 5 mS

(typ.)

− Effective byte-write (erase/program) cycle
time: 19.5 µS

− Optional software-protected data write

• Fast chip-erase operation: 50 mS

• Two 16 KB boot blocks with lockout

• Typical page write (erase/program) cycles:

1K/10K (typ.)

• Read access time: 90/120 nS

• Ten-year data retention

• Software and hardware data protection

• Low power consumption

− Active current: 25 mA (typ.)

− Standby current: 20 µA (typ.)

• Automatic write (erase/program) timing with

internal VPP generation

• End of write (erase/program) detection

− Toggle bit

− Data polling

• Latched address and data

• All inputs and outputs directly TTL compatible

• JEDEC standard byte-wide pinouts

• Available packages: TSOP and PLCC

Publication Release Date: May 1999

- 1 - Revision A5

W29C040

CE

OE

WE

PIN CONFIGURATIONS

A

A

V

/

A

A

1

1

C

W

1

1

2

6

C

E

8

5

5

A7

6

A6

7

A5
A4
A3
A2
A1
A0

DQ0

1

A11

2

A9

3

A8

4

A13

5

A14

6

A17

7

WE

8

V

CC

9

A18

10

A16

11

A15

12

A12

13

A7

14

A6

15

A5

16 A3

A4

32-pin

8

PLCC

9
10
11
12
13

14

D

D

G

D

D

Q

1

D

Q

N

Q

Q

Q

2

D

4

3

5

32-pin

TSOP

BLOCK DIAGRAM

V

CC

V

SS

A

1
7

3031321234

A14

29
28

A13

27

A8

26

A9

25

A11

24

OE

23

A10

22

CE

21

DQ7

201918171615

D
Q
6

32

OE
A10

31
30

CE
DQ7

29

DQ6

28

DQ5

27

DQ4

26

DQ3

25

GND

24

DQ2

23

DQ1

22

DQ0

21

A0

20
19

A1
A2

18
17

CE
OE

CONTROL

WE

A0

16K Byte Boot Block (Optional)

.
.

DECODER

.

A18

16K Byte Boot Block (Optional)

PIN DESCRIPTION

SYMBOL PIN NAME

A0−A18

DQ0−DQ7

Address Inputs
Data Inputs/Outputs
Chip Enable

OUTPUT
BUFFER

CORE

ARRAY

Output Enable

DQ0

.
.

DQ7

- 2 -

Write Enable

VCC Power Supply

GND Ground

W29C040

FUNCTIONAL DESCRIPTION

Read Mode

The read operation of the W29C040 is controlled by CE and OE, both Chip of which have to be low
for the host to obtain data from the outputs. CE is used for device selection. When CE is high, the
chip is de-selected and only standby power will be consumed. OE is the output control and is used to
gate data from the output pins. The data bus is in high impedance state when either CE or OE is

high.
Refer to the read cycle timing waveforms for further details.

Page Write Mode

The W29C040 is written (erased/programmed) on a page basis. Every page contains 256 bytes of
data. If a byte of data within a page is to be changed, data for the entire page must be loaded into the
device. Any byte that is not loaded will be erased to "FF hex" during the write operation of the page.

The write operation is initiated by forcing CE and WE low and OE high. The write procedure
consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the
device.

Step 2 is an internal write (erase/program) cycle, during which the data in the page buffers are
simultaneously written into the memory array for non-volatile storage.

During the byte-load cycle, the addresses are latched by the falling edge of either CE or WE,
whichever occurs last. The data are latched by the rising edge of either CE or WE, whichever

occurs first. If the host loads a second byte into the page buffer within a byte-load cycle time (TBLC) of
200 µS after the initial byte-load cycle, the W29C040 will stay in the page load cycle. Additional bytes
can then be loaded consecutively. The page load cycle will be terminated and the internal write
(erase/program) cycle will start if no additional byte is loaded into the page buffer. A8 to A18 specify
the page address. All bytes that are loaded into the page buffer must have the same page address.
A0 to A7 specify the byte address within the page. The bytes may be loaded in any order; sequential
loading is not required.

In the internal write cycle, all data in the page buffers, i.e., 256 bytes of data, are written
simultaneously into the memory array. The typical write (erase/program) time is 5 mS. The entire
memory array can be written in 10.4 seconds. Before the completion of the internal write cycle, the
host is free to perform other tasks such as fetching data from other locations in the system to prepare
to write the next page.

Software-protected Data Write

The device provides a JEDEC-approved optional software-protected data write. Once this scheme is
enabled, any write operation requires a three-byte command sequence (with specific data to a
specific address) to be performed before the data load operation. The three-byte load command
sequence begins the page load cycle, without which the write operation will not be activated. This
write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by
noise during system power-up and power-down.

The W29C040 is shipped with the software data protection enabled. To enable the software data
protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The
device will then enter the software data protection mode, and any subsequent write operation must be
preceded by the three-byte command sequence cycle. Once enabled, the software data protection

Publication Release Date: May 1999

- 3 - Revision A5

W29C040

WE

DATA

will remain enabled unless the disable commands are issued. A power transition will not reset the
software

data protection feature. To reset the device to unprotected mode, a six byte command sequence is
required. For information about specific codes, see the Command Codes for Software Data
Protection in the Table of Operating Modes. For information about timing waveforms, see the timing
diagrams below.

Hardware Data Protection

The integrity of the data stored in the W29C040 is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.

(2) VCC Power Up/Down Detection: The write operation is inhibited when VCC is less than 2.5V.
(3) Write Inhibit Mode: Forcing OE low, CE high, or

prevents inadvertent writes during power-up or power-down periods.

(4) VCC power-on delay: When VCC has reach its sense level, the device will automatically time-out

10 mS before any write (erase/program) operation.

high will inhibit the write operation. This

Chip Erase Modes

The entire device can be erased by using a six-byte software command code. See the Software Chip
Erase Timing Diagram.

Boot Block Operation

There are two boot blocks (16K bytes each) in this device, which can be used to store boot code. One
of them is located in the first 16K bytes and the other is located in the last 16K bytes of the memory.
The first 16K or last 16K of the memory can be set as a boot block by using a seven-byte command
sequence.

See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set
the data for the designated block cannot be erased or programmed (programming lockout); other
memory locations can be changed by the regular programming method. Once the boot block
programming lockout feature is activated, the chip erase function will be disabled. In order to detect
whether the boot block feature is set on the two 16K blocks, users can perform a six-byte command
sequence: enter the product identification mode (see Command Codes for Identification/Boot Block
Lockout Detection for specific code), and then read from address "00002 hex" (for the first 16K bytes)
or "7FFF2 hex" (for the last 16K bytes). If the output data is "FF hex," the boot block programming
lockout feature is activated; if the output data is "FE hex," the lockout feature is inactivated and the
block can be programmed.

To return to normal operation, perform a three-byte command sequence to exit the identification
mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection.

Data Polling (DQ7)- Write Status Detection

The W29C040 includes a data polling feature to indicate the end of a write cycle. When the
W29C040 is in the internal write cycle, any attempt to read DQ7 of the last byte loaded during the
page/byte-load cycle will receive the complement of the true data. Once the write cycle is completed.

DQ7 will show the true data. See the

Polling Timing Diagram.

- 4 -

W29C040

WE

CEOEWE

Toggle Bit (DQ6)- Write Status Detection

In addition to data polling, the W29C040 provides another method for determining the end of a write
cycle. During the internal write cycle, any consecutive attempts to read DQ6 will produce alternating
0's and 1's. When the write cycle is completed, this toggling between 0's and 1's will stop. The device
is then ready for the next operation. See Toggle Bit Timing Diagram.

Product Identification

The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.

The manufacturer and device codes can be accessed by software or hardware operation. In the
software access mode, a six-byte command sequence can be used to access the product ID. A read
from address "00000 hex" outputs the manufacturer code "DA hex." A read from address "00001 hex"
outputs the device code "46 hex." The product ID operation can be terminated by a three-byte
command sequence.

In the hardware access mode, access to the product ID is activated by forcing CE and OE low,
high, and raising A9 to 12 volts.

TABLE OF OPERATING MODES

Operating Mode Selection

Operating Range: 0 to 70° C (Ambient Temperature), VDD = 5V ±10%, VSS = 0V, VHH = 12V

MODE PINS

ADDRESS DQ.

Read VIL VIL VIH AIN Dout
Write VIL VIH VIL AIN Din
Standby VIH X X X High Z
Write Inhibit X VIL X X High Z/DOUT

X X VIH X High Z/DOUT
Output Disable X VIH X X High Z
Product ID VIL VIL VIH

VIL VIL VIH

A0 = VIL; A1−A18 = VIL;
A9 = VHH

A0 = VIH; A1−A18 = VIL;
A9 = VHH

Manufacturer Code DA
(Hex)

Device Code
46 (Hex)

Publication Release Date: May 1999

- 5 - Revision A5

W29C040

Command Codes for Software Data Protection

BYTE SEQUENCE TO ENABLE PROTECTION TO DISABLE PROTECTION

ADDRESS DATA ADDRESS DATA

0 Write 5555H AAH 5555H AAH
1 Write 2AAAH 55H 2AAAH 55H
2 Write 5555H A0H 5555H 80H
3 Write - - 5555H AAH
4 Write - - 2AAAH 55H
5 Write - - 5555H 20H

Software Data Protection Acquisition Flow

(Optional page-load

operation)

Software Data Protection
Enable Flow

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data A0

to

address 5555

Sequentially load

up to 256 bytes

of page data

Pause 10 mS

Exit

Software Data Protection
Disable Flow

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 20

to

address 5555

Notes for software program code:
Data Format: DQ7−DQ0 (Hex)
Address Format: A14−A0 (Hex)

Pause 10 mS

Exit

- 6 -

Command Codes for Software Chip Erase

BYTE SEQUENCE ADDRESS DATA

0 Write 5555H AAH
1 Write 2AAAH 55H
2 Write 5555H 80H
3 Write 5555H AAH
4 Write 2AAAH 55H
5 Write 5555H 10H

Software Chip Erase Acquisition Flow

Load data AA
address 5555

Load data 55

address 2AAA

W29C040

to

to

Notes for software chip erase:
Data Format: DQ7−DQ0 (Hex)

Address Format: A14−A0 (Hex)

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 10

to

address 5555

Pause 50 mS

Exit

Publication Release Date: May 1999

- 7 - Revision A5

W29C040

address 5555

Command Codes for Product Identification and Boot Block Lockout Detection

BYTE

SEQUENCE

ALTERNATE PRODUCT (7)
IDENTIFICATION/BOOT BLOCK
LOCKOUT DETECTION ENTRY

SOFTWARE PRODUCT
IDENTIFICATION/BOOT BLOCK
LOCKOUT DETECTION ENTRY

SOFTWARE PRODUCT

IDENTIFICATION/BOOT BLOCK

LOCKOUT DETECTION EXIT

ADDRESS DATA ADDRESS DATA ADDRESS DATA

0 Write 5555 AA 5555H AAH 5555H AAH
1 Write 2AAA 55 2AAAH 55H 2AAAH 55H
2 Write 5555 90 5555H 80H 5555H F0H
3 Write - - 5555H AAH - ­4 Write - - 2AAAH 55H - ­5 Write - - 5555H 60H - -

Pause 10 µS Pause 10 µS Pause 10 µS

Software Product Identification and Boot Block Lockout Detection Acquisition Flow

Product
Identification
Entry (1)

Load data AA

to

Load data 55

to

address 2AAA

Load data 80

to

address 5555

Product
Identification
and Boot Block
Lockout Detection
Mode (3)

Read address = 00000

data = DA

Read address = 00001

data = 46

(2)

(2)

Product
Identification
Exit (1)

Load data AA
address 5555

Load data 55

address 2AAA

to

to

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 60

to

address 5555

Pause 10 uS

Notes for software product identification/boot block lockout detection:
(1) Data Format: DQ7−DQ0 (Hex); Address Format: A14−A0 (Hex)
(2) A1−A18 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.

(3) The device does not remain in identification and boot block (address 0002 Hex/7FFF2 Hex respond to first 16K/last 16K) lockout detection

mode if power down.

(4), (5) If the output data is "FF Hex," the boot block programming lockout feature is activated; if the output data "FE Hex," the lockout feature is

inactivated and the block can be programmed.
(6) The device returns to standard operation mode.
(7) This product supports both the JEDEC standard 3 byte command code sequence and original 6 byte command code sequence. For new

designs, Winbond recommends that the 3 byte command code sequence be used.

Read address = 00002

data = FF/FE

Read address = 7FFF2

data = FF/FE

(4)

(5)

Load data F0

to

address 5555

Pause 10 uS

Normal Mode

(6)

- 8 -

Command Codes for Boot Block Lockout Enable

BYTE SEQUENCE BOOT BLOCK LOCKOUT FEATURE SET

0 Write 5555H AAH 5555H AAH
1 Write 2AAAH 55H 2AAAH 55H
2 Write 5555H 80H 5555H 80H
3 Write 5555H AAH 5555H AAH
4 Write 2AAAH 55H 2AAAH 55H
5 Write 5555H 40H 5555H 40H
6 Write 00000H 00H 3FFFFH FFH

ON FIRST 16K ADDRESS BOOT BLOCK

ADDRESS DATA ADDRESS DATA

Pause 10 mS Pause 10 mS

Boot Block Lockout Enable Acquisition Flow

Boot Block Lockout
Feature Set on First 16K
Address Boot Block

Boot Block Lockout
Feature Set on Last 16K
Address Boot Block

W29C040

BOOT BLOCK LOCKOUT FEATURE SET

ON LAST 16K ADDRESS BOOT BLOCK

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 40

to

address 5555

Load data 00

to

address 00000

Pause 10 mS

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 40

to

address 5555

Load data FF

to

address 3FFFF

Pause 10 mS

Notes for boot block lockout enable:

1. Data Format: DQ7−DQ0 (Hex)

2. Address Format: A14−A0 (Hex)

3. If you have any questions about this command sequence, please contact the local distributor or Winbond Electronics Corp.

Publication Release Date: May 1999

- 9 - Revision A5

W29C040

CE

CE

CE

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER RATING UNIT

Power Supply Voltage to Vss Potential -0.5 to +7.0 V
Operating Temperature 0 to +70
Storage Temperature -65 to +150
D.C. Voltage on Any Pin to Ground Potential Except A9 -0.5 to VDD +1.0 V
Transient Voltage (<20 nS ) on Any Pin to Ground Potential -1.0 to VDD +1.0 V

Voltage on A9 and OE Pin to Ground Potential

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the

device.

-0.5 to 12.5 V

°C
°C

Operating Characteristics

(VDD = 5.0V ±10%, VSS = 0V, TA = 0 to 70° C)

PARAMETER SYM. TEST CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

Power Supply Current

Standby VDD Current
(TTL input)

ICC

ISB1

= OE = VIL, WE = VIH,

all DQs open
Address inputs = VIL/VIH,

at f = 5 MHz

= VIH, all DQs open

Other inputs = VIL/VIH

- - 50 mA

- 2 3 mA

Standby VDD Current
(CMOS input)

Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output High Voltage

CMOS

ISB2

ILI VIN = GND to VDD - - 10
ILO VIN = GND to VDD - - 10
VIL
VIH
VOL IOL = 2.0 mA - - 0.45 V
VOH1
VOH2

= VDD -0.3V, all DQs

open

-

-

IOH = -400 µA
IOH = -100 µA; VCC = 4.5V

- 10 -

- 20 100

- - 0.8 V

2.0 - - V

2.4 - - V

4.2 - - V

µA

µA
µA

W29C040

Power-up Timing

PARAMETER SYMBOL TYPICAL UNIT

Power-up to Read Operation TPU. READ 100
Power-up to Write Operation TPU. WRITE 10 mS

CAPACITANCE

(VDD = 5.0V, TA = 25° C, f = 1 MHz)

PARAMETER SYMBOL CONDITIONS MAX. UNIT

DQ Pin Capacitance CDQ VDQ = 0V 12 pF
Input Pin Capacitance CIN VIN = 0V 6 pF

AC CHARACTERISTICS

AC Test Conditions

(VDD = 5.0V ±10% for 90,120 nS

PARAMETER CONDITIONS

Input Pulse Levels 0V to 3V

Input Rise/Fall Time <5 nS

Input/Output Timing Level 1.5V/1.5V

Output Load 1 TTL Gate and CL = 100 pF for 90/120/150 nS

µS

AC Test Load and Waveform

D

OUT

100 pF for 90/120 nS
(Including Jig and Scope)

Input

3V

0V

Test Point Test Point

+5V

1.8K

Ω

1.3K

Ω

Output

1.5V

1.5V

Publication Release Date: May 1999

- 11 - Revision A5

W29C040

CE

OE

WE

WE

OE

OE

CE

WE

WE

AC Characteristics, continued

Read Cycle Timing Parameters

(VDD = 5.0V ±10% for 90,120 and 150 nS, VSS = 0V, TA = 0 to 70° C)

PARAMETER SYM. W29C040-90 W29C040-12 UNIT

MIN. MAX. MIN. MAX.

Read Cycle Time TRC 90 - 120 - nS
Chip Enable Access Time TCE - 90 - 120 nS
Address Access Time TAA - 90 - 120 nS
Output Enable Access Time TOE - 40 - 50 nS

High to High-Z Output

High to High-Z Output

Output Hold from Address change TOH 0 - 0 - nS

Byte/Page-write Cycle Timing Parameters

TCHZ - 25 - 30 nS
TOHZ - 25 - 30 nS

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Write Cycle (erase and program) TWC - - 10 mS
Address Setup Time TAS 0 - - nS
Address Hold Time TAH 50 - - nS

and CE Setup Time

and CE Hold Time
High Setup Time
High Hold Time

Pulse Width

Pulse Width

High Width

TCS 0 - - nS
TCH 0 - - nS
TOES 0 - - nS
TOEH 0 - - nS
TCP 70 - - nS
TWP 70 - - nS
TWPH 100 - - nS

Data Setup Time TDS 50 - - nS
Data Hold Time TDH 0 - - nS
Byte Load Cycle Time TBLC - - 150

Notes:
All AC timing signals observe the following guideline for determining setup and hold times:

(1) High level signal's reference level is VIH
(2) Low level signal's reference level is VIL

µS

- 12 -

AC Characteristics, continued

DATA

OE

OE

OE

OE

OE

W29C040

Polling Characteristics

(1)

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Data Hold Time TDH 10 - - nS

Hold Time

to Output Delay

(2)

TOEH 10 - - nS
TOE - - - nS

Write Recovery Time TWR 0 - - nS

Notes:
(1) These parameters are characterized and not 100% tested.
(2) See TOE spec in A.C. Read Cycle Timing Parameters.

Toggle Bit Characteristics

(1)

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Data Hold Time TDH 10 - - nS

Hold Time

to Output Delay

High Pulse

(2)

TOEH 10 - - nS
TOE - - - nS
TOEHP 150 - - nS

Write Recovery Time TWR 0 - - nS

Notes:
(1) These parameters are characterized and not 100% tested.
(2) See TOE spec in A.C. Read Cycle Timing Parameters.

TIMING WAVEFORMS

Read Cycle Timing Diagram

Address A18-0

CE

OE

V

WE

DQ7-0

IH

High-Z

T

RC

T

CE

T

OE

T

OHZ

T

OH

AA

T

T

CHZ

Data ValidData Valid

High-Z

Publication Release Date: May 1999

- 13 - Revision A5

Timing Waveforms, continued

WE

CE

Controlled Write Cycle Timing Diagram

T

AS

Address A18-0

W29C040

T

T

AH

WC

CE

OE

WE

DQ7-0

T

CS

T

OES

T

WP

Controlled Write Cycle Timing Diagram

TAS

Address A18-0

CE

T

AH

T

CP

T

DS

Data Valid

T

CH

T

OEH

T

WPH

T

DH

T

WPH

Internal write starts

T

WC

DQ7-0

OE

WE

High Z

T

OES

T

CS TCH

Data Valid

- 14 -

T

OEH

T

DS

T

DH

Internal Write Starts

Timing Waveforms, continued

DATA

Page Write Cycle Timing Diagram

Address A18-0

DQ7-0

CE

W29C040

T

WC

OE

WE

TWP

Byte 0

Polling Timing Diagram

Address A18-0

WE

CE

T

OEH

OE

T

DH

DQ7

TBLC

T

WPH

Byte 1

T

OE

Byte 2

HIGH-Z

Byte N-1

Internal Write Start

T

WR

Byte N

Publication Release Date: May 1999

- 15 - Revision A5

Timing Waveforms, continued

Toggle Bit Timing Diagram

WE

W29C040

CE

OE

DQ6

TDH

T

OEH

T

OE

HIGH-Z

Page Write Timing Diagram Software Data Protection Mode

Byte/page load
cycle starts

Address A18-0

DQ7-0

CE

Three-byte sequence for

software data protection mode

2AAA

5555

AA 55 A0

5555

T

WR

WC

T

OE

WE

WP

T

SW0

T

WPH

BLC

T

Byte 0

SW2SW1

Byte N-1

Byte N

(Last Byte)

Internal write starts

- 16 -

Timing Waveforms, continued

Reset Software Data Protection Timing Diagram

W29C040

Six-byte sequence for resetting
software data protection mode

Address A18-0

DQ7-0

CE

OE
WE

5555

AA

T

WP

SW0

T

2AAA

WPH

55 80

TBLC

SW1

5555

SW2

5555 2AAA

SW3

5 Volt-only Software Chip Erase Timing Diagram

Six-byte code for 5V-only software
chip erase

AA 55

SW4

5555

20

SW5

Internal programming starts

WC

T

WC

T

Address A18-0

DQ7-0

CE

OE

WE

5555

AA

T

WP

SW0

T

WPH

2AAA

55

SW1

5555

T

BLC

80 AA

SW2

5555 2AAA

SW3

SW4

55

5555

10

SW5

Internal erasing starts

Publication Release Date: May 1999

- 17 - Revision A5

ORDERING INFORMATION

W29C040

PART NO. ACCESS

TIME

(nS)

W29C040T-90 90 50 100 Type one TSOP 1K
W29C040T-12 120 50 100 Type one TSOP 1K
W29C040P-90 90 50 100 32-pin PLCC 1K
W29C040P-12 120 50 100 32-pin PLCC 1K
W29C040T-90B 90 50 100 Type one TSOP 10K
W29C040T-12B 120 50 100 Type one TSOP 10K
W29C040P-90B 90 50 100 32-pin PLCC 10K
W29C040P-12B 120 50 100 32-pin PLCC 10K

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.

POWER

SUPPLY CURRENT

MAX. (mA)

STANDBY

VDD CURRENT

MAX. (µA)

PACKAGE CYCLING

- 18 -

PACKAGE DIMENSIONS

E

32-pin PLCC

H

E

1

324

30

5

13

L

θ

Seating Plane

14

e

EG

20

b
b

1

W29C040

Dimension in Inches Dimension in mm

Symbol

29

D

H D

21

2A

A

1

A

y

G D

c

Min. Nom. Max. Max.Nom.Min.

A

0.020

1

A
A

2

1

b

0.016

b

0.008

c

0.547

D

0.447

E

e

0.490

G

D

0.390

E

G

0.585

H

D

0.485

E

H

0.075

L

y

°

0

θ

0.028

0.018

0.010

0.550

0.450

0.050

0.510

0.410

0.590

0.490

0.090

0.140

0.1150.105 0.110

0.0320.026

0.022

0.014

0.553

0.453

0.530

0.430

0.595

0.495

0.095

0.004

°

10

0.50

0.66 0.81

0.41

0.20

13.89

11.35

1.12 1.420.044 0.056

12.45

9.91

14.86

12.32

1.91 2.29

°

0

2.802.67 2.93

0.71

0.46

0.25

13.97

11.43

1.27

12.95

10.41

14.99

12.45

14.05

11.51

13.46

10.92

15.11

12.57

3.56

0.56

0.35

2.41

0.10

°

10

Notes:

1. Dimensions D & E do not include interlead flash.

2. Dimension b1 does not include dambar protrusion/intrusion.

3. Controlling dimension: Inches.

4. General appearance spec. should be based on final
visual inspection sepc.

40-pin TSOP

1

e

M

0.10 (0.004)

b

θ

L

D

H

Dimension in Inches

D

c

E

Symbol

A
A
A

b

Min. Nom. Max.

1

0.002

2

c

0.72 0.724 0.728

D

0.390 0.394 0.398

E

H

D

0.780 0.787 0.795

e

L

A

2

A

1

A

L1

Y

L

Y

θ

Controlling dimension: Millimeters

0.020

1

0.000

0.020

0.024

0.031

0 3 5

Min. Nom. Max.

0.047

0.05

0.006

0.95

0.10 0.15 0.200.004 0.006 0.008

18.3

19.8

0.50

0.028

0.004

0.00

Dimension in mm

1.00

0.17 0.22 0.270.007 0.009 0.011

18.4

9.90

10

20.0

0.50

0.60

0.8

0

3

1.20

0.15

1.050.0410.0390.037

18.5

10.10

20.2

0.70

0.10
5

Publication Release Date: May 1999

- 19 - Revision A5

VERSION HISTORY

VERSION DATE PAGE DESCRIPTION

A1 Apr. 1997 - Initial Issued
A2 Nov. 1997 4, 8 Correct the address from 3FFF2 to 7FFF2

9 Correct the boot block from 8K to 16K

15 Modify page write cycle timing diagram waveform

1, 18 Delete cycling 100K item

6 Add. pause 10 mS
7 Add. pause 50 mS

W29C040

8

Correct the time from 10 mS to 10 µS

A3 June 1998 4 Correct power-on delay from 5 mS to 10 mS

11 Correct TPU.WRITE (Typ.) from 5 mS to 10 mS

A4 Oct. 1998 20 Correct 40-pin TSOP package drawing by 32-pin TSOP

9 Correct the address from 3FFFF to 7FFFF

A5 May 1999 1, 12, 18 Modify TACC:

90/120/150 nS à 90/120 nS binning

1, 2, 18, 19 Modify package:

PDIP/SOP/PLCC/TSOP à PLCC/TSOP

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: [phone]
FAX: [phone]
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: [phone]
FAX: [phone]

Note: All data and specifications are subject to change without notice.

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: [phone]
FAX: [phone]

Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.

2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: [phone]
FAX: [phone]

- 20 -