Rainbow Electronics W29C020C User Manual

W29C020C

256K x 8 CMOS FLASH MEMORY

GENERAL DESCRIPTION

The W29C020C is a 2-megabit, 5-volt only CMOS flash memory organized as 256K × 8 bits. The device can be written (erased and programmed) in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W29C020C results in fast write (erase/program) operations with extremely low current consumption compared to other comparable 5-volt flash memory products. The device can also be written (erased and programmed) by using standard EPROM programmers.

FEATURES

• Single 5-volt write (erase and program)

operations

• Fast page-write operations

− 128 bytes per page

− Page write (erase/program) cycle: 10 mS

(max.)

− Effective by te-write (erase/program) cycle time: 39 µS

− Optional software-protected data write

• Fast chip-erase operation: 50 mS

• Two 8 KB boot blocks with lockout

• Whole chip cycling:

10K (typ.)

• Read access time: 70/90/120 nS

• Twenty-year data retention

• Software and hardware data protection

• Low power consumption

− Active current: 25 mA (typ.)

− Standby current: 20 µA (typ.)

• Automatic write (erase/program) timing with

internal VPP generation

• End of write (erase/program) detection

− Toggle bit

− Data polling

• Latched address and data

• All inputs and outputs directly TTL compatible

• JEDEC standard byte-wide pinouts

• Available packages: 32-pin 600 mil DIP, 32-pin

TSOP, and 32-pin PLCC

Publication Release Date: April 1999

- 1 - Revision A1

PIN CONFIGURATIONS BLOCK DIAGRAM

123

910111213

1415163231

45678

ARRAY

CONTROL

BUFFER

WEA0A17

W29C020C

A16

A15

A12

A5 A4 A3 A2 A1 A0

DQ0 DQ1 DQ2 GND

A7 A6 A5 A4 A3 A2 A1 A0

DQ0

A11

A8 A13 A14 A17

A16

A15

A12

16 A3

32-pin

DIP

16N

5 6 7 8

32-pin PLCC

9 10 11 12 13

32-pin TSOP

A17

A14

A13

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

1 7

3031321234

A14

A13

A11

A10

DQ7

20191817161514

OUTPUT

DQ0

DQ7

8K Byte Boot Block (Optional)

. .

DECODER

CORE

8K Byte Boot Block (Optional)

PIN DESCRIPTION

SYMBOL PIN NAME

A0−A17 Address Inputs

A10

DQ7

DQ6

DQ5

DQ4

DQ3

GND

DQ2

DQ1

DQ0

18 17

DQ0−DQ7 Data Inputs/Outputs

Chip Enable Output Enable Write Enable

VDD Power Supply

GND Ground

NC No Connection

- 2 -

W29C020C

FUNCTIONAL DESCRIPTION

Read Mode

The read operation of the W29C020C is controlled by CE and OE , both of which have to be low for the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is deselected and only standby power will be consumed. OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE or OE is high.

Refer to the read cycle timing waveforms for further details.

Page Write Mode

The W29C020C is written (erased/programmed) on a page basis. Every page contains 128 bytes of data. If a byte of data within a page is to be changed, data for the entire page must be loaded into the device. Any byte that is not loaded will be erased to "FF hex" during the write operation of the page.

The write operation is initiated by forcing CE and WE low and OE high. The write procedure consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the device.

Step 2 is an internal write (erase/program) cycle, during which the data in the page buffers are simultaneously written into the memory array for non-volatile storage.

During the byte-load cycle, the addresses are latched by the falling edge of either CE or WE, whichever occurs last. The data are latched by the rising edge of either CE or WE, whichever occurs

first. If the host loads a second byte into the page buffer within a byte-load cycle time (TBLC ) of 200 µS after the initial byte-load cycle, the W29C020C will stay in the page load cycle. Additional bytes can then be loaded consecutively. The page load cycle will be terminated and the internal write (erase/program) cycle will start if no additional byte is loaded into the page buffer A7 to A17 specify the page address. All bytes that are loaded into the page buffer must have the same page address. A0 to A6 specify the byte address within the page. The bytes may be loaded in any order; sequential loading is not required.

In the internal write cycle, all data in the page buffers, i.e., 128 bytes of data, are written simultaneously into the memory array. Before the completion of the internal write cycle, the host is free to perform other tasks such as fetching data from other locations in the system to prepare to write the next page.

Software-protected Data Write

The device provides a JEDEC-approved optional software-protected data write. Once this scheme is enabled, any write operation requires a three-byte command sequence (with specific data to a specific address) to be performed before the data load operation. The three-byte load command sequence begins the page load cycle, without which the write operation will not be activated. This write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during system power-up and power-down.

The W29C020C is shipped with the software data protection enabled. To enable the software data protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The device will then enter the software data protection mode, and any subsequent write operation must be preceded by the three-byte command sequence cycle. Once enabled, the software data protection will remain enabled unless the disable commands are issued. A power transition will not reset the software data protection feature. To reset the device to unprotected mode, a six-byte command sequence is required. For information about specific codes, see the Command Codes for Software Data Protection in the Table of Operating Modes. For information about timing waveforms, see the timing diagrams below.

- 3 -

W29C020C

Hardware Data Protection

The integrity of the data stored in the W29C020C is also hardware protected in the following ways: (1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.

(2) VDD Power Up/Down Detection: The write operation is inhibited when VDD is less than 2.5V. (3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This

prevents inadvertent writes during power-up or power-down periods.

(4) VDD power-on delay: When VDD reaches its sense level, the device will automatically timeout for

5 mS before any write (erase/program) operation.

Chip Erase Modes

The entire device can be erased by using a six-byte software command code. See the Software Chip Erase Timing Diagram.

Boot Block Operation

There are two boot blocks (8K bytes each) in this device, which can be used to store boot code. One of them is located in the first 8K bytes and the other is located in the last 8K bytes of the memory. The first 8K or last 8K of the memory can be set as a boot block by using a seven-byte command sequence.

See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the data for the designated block cannot be erased or programmed (programming lockout); other memory locations can be changed by the regular programming method. Once the boot block programming lockout feature is activated, the chip erase function will be disabled. In order to detect whether the boot block feature is set on the two 8K blocks, users can perform a six-byte command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address "00002 hex" (for the first 8K bytes) or "3FFF2 hex" (for the last 8K bytes). If the output data is "FF hex," the boot block programming lockout feature is activated; if the output data is "FE hex," the lockout feature is deactivated and the block can be programmed.

To return to normal operation, perform a three-byte command sequence to exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection.

Data Polling (DQ7)- Write Status Detection

The W29C020C includes a data polling feature to indicate the end of a write cycle. When the W29C020C is in the internal write cycle, any attempt to read DQ7 from the last byte loaded during the page/byteload cycle will receive the complement of the true data. Once the write cycle is completed. DQ7 will

show the true data. See the DATA Polling Timing Diagram.

- 4 -

W29C020C

CEOEWE

Toggle Bit (DQ6)- Write Status Detection

In addition to data polling, the W29C020C provides another method for determining the end of a write cycle. During the internal write cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the write cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation. See Toggle Bit Timing Diagram.

Product Identification

The product ID operation outputs the manufacturer code and device code. The programming equipment automatically matches the device with its proper erase and programming algorithms.

The manufacturer and device codes can be accessed through software or by hardware operation. In the software access mode, a six-byte command sequence can be used to access the product ID. A read from address "00000 hex" outputs the manufacturer code "DA hex." A read from address "00001 hex" outputs the device code "45 hex." The product ID operation can be terminated by a three-byte command sequence.

In the hardware access mode, access to the product ID is activated by forcing CE and OE low, WE high, and raising A9 to 12 volts.

TABLE OF OPERATING MODES

Operating Mode Selection

Operating Range: 0 to 70° C (Ambient Temperature), VDD = 5V ±10%, VSS = 0V, VHH = 12V

MODE PINS

ADDRESS DQ.

Read VIL VIL VIH AIN Dout Write VIL VIH VIL AIN Din Standby VIH X X X High Z Write Inhibit X VIL X X High Z/DOUT

X X VIH X High Z/DOUT Output Disable X VIH X X High Z Product ID VIL VIL VIH A0 = VIL; A1−A17 = VIL;

A9 = VHH

VIL VIL VIH A0 = VIH; A1−A17 = VIL;

A9 = VHH

Manufacturer Code DA (Hex)

Device Code 45 (Hex)

Publication Release Date: April 1999

- 5 - Revision A1

W29C020C

address 5555

of page data

Pause 10 mS

Exit

Pause 10 mS

Exit

Command Codes for Software Data Protection

BYTE SEQUENCE TO ENABLE PROTECTION TO DISABLE PROTECTION

ADDRESS DATA ADDRESS DATA

0 Write 5555H AAH 5555H AAH 1 Write 2AAAH 55H 2AAAH 55H 2 Write 5555H A0H 5555H 80H 3 Write - - 5555H AAH 4 Write - - 2AAAH 55H 5 Write - - 5555H 20H

Software Data Protection Acquisition Flow

(Optional page-load

operation)

Software Data Protection Enable Flow

Load data AA

Load data 55

address 2AAA

Load data A0

address 5555

Sequentially load

up to 128 bytes

Software Data Protection Disable Flow

Load data AA

address 5555

Load data 55

address 2AAA

Load data 80

address 5555

Load data AA

Load data 55

address 2AAA

Load data 20

Notes for software program code: Data Format: DQ7−DQ0 (Hex) Address Format: A14−A0 (Hex)

- 6 -

Command Codes for Software Chip Erase

BYTE SEQUENCE ADDRESS DATA

0 Write 5555H AAH 1 Write 2AAAH 55H 2 Write 5555H 80H 3 Write 5555H AAH 4 Write 2AAAH 55H 5 Write 5555H 10H

Software Chip Erase Acquisition Flow

Load data AA

address 5555

Load data 55

address 2AAA

W29C020C

Notes for software chip erase: Data Format: DQ7−DQ0 (Hex) Address Format: A14−A0 (Hex)

Load data 80

address 5555

Load data AA

address 5555

Load data 55

address 2AAA

Load data 10

address 5555

Pause 50 mS

Exit

Publication Release Date: April 1999

- 7 - Revision A1

W29C020C

address 5555

address 2AAA

address 5555

address 2AAA

address 5555

Pause 10 S

Normal Mode

(6)

Pause 10 S

Command Codes for Product Identification and Boot Block Lockout Detection

BYTE

SEQUENCE

0 Write 5555 AA 5555H AAH 5555H AAH 1 Write 2AAA 55 2AAAH 55H 2AAAH 55H 2 Write 5555 90 5555H 80H 5555H F0H 3 Write - - 5555H AAH - 4 Write - - 2AAAH 55H - 5 Write - - 5555H 60H - -

Software Product Identification and Boot Block Lockout Detection Acquisition Flow

ALTERNATE PRODUCT (7)

IDENTIFICATION/BOOT BLOCK

LOCKOUT DETECTION ENTRY

SOFTWARE PRODUCT

IDENTIFICATION/BOOT BLOCK

LOCKOUT DETECTION ENTRY

SOFTWARE PRODUCT

IDENTIFICATION/BOOT BLOCK

LOCKOUT DETECTION EXIT

ADDRESS DATA ADDRESS DATA ADDRESS DATA

Pause 10 µS Pause 10 µS Pause 10 µS

Product Identification Entry (1)

Load data AA

Load data 55

Load data 80

Load data AA

Load data 55

Load data 60

Product Identification and Boot Block Lockout Detection Mode (3)

Read address = 00000

data = DA

Read address = 00001

data = 45

Read address = 00002

data = FF/FE

Read address = 3FFF2

data = FF/FE

(2)

(4)

(5)

Product Identification Exit (1)

Load data AA

address 5555

Load data 55

address 2AAA

Load data F0 address 5555

Notes for software product identification/boot block lockout detection: (1) Data Format: DQ7−DQ0 (Hex); Address Format: A14−A0 (Hex) (2) A1−A16 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification and boot block (address 0002 Hex/3FFF2 Hex respond to first 8K/last 8K) lockout detection

mode if power down. (4), (5) If the output data is "FF Hex," the boot block programming lockout feature is activated; if the output data "FE Hex," the lockout feature is inactivated and the block can be programmed. (6) The device returns to standard operation mode. (7) This product supports both the JEDEC standard 3 byte command code sequence and original 6 byte command code sequence. For new

designs, Winbond recommends that the 3 byte command code sequence be used.

- 8 -

Command Codes for Boot Block Lockout Enable

address 5555

address 2AAA

address 5555

address 2AAA

address 5555

address 00000

address 5555

address 2AAA

address 5555

address 2AAA

address 5555

address 3FFFF

BYTE SEQUENCE BOOT BLOCK LOCKOUT FEATURE SET

ON FIRST 8K ADDRESS BOOT BLOCK

ADDRESS DATA ADDRESS DATA

0 Write 5555H AAH 5555H AAH 1 Write 2AAAH 55H 2AAAH 55H 2 Write 5555H 80H 5555H 80H 3 Write 5555H AAH 5555H AAH 4 Write 2AAAH 55H 2AAAH 55H 5 Write 5555H 40H 5555H 40H 6 Write 00000H 00H 3FFFFH FFH

Pause 10 mS Pause 10 mS

Boot Block Lockout Enable Acquisition Flow

Boot Block Lockout Feature Set on First 8K Address Boot Block

Load data AA

Boot Block Lockout Feature Set on Last 8K Address Boot Block

Load data AA

W29C020C

BOOT BLOCK LOCKOUT FEATURE SET

ON LAST 8K ADDRESS BOOT BLOCK

Load data 55

Load data 80

Load data AA

Load data 55

Load data 40

Load data 00

Pause 10 mS

Load data 55

Load data 80

Load data AA

Load data 55

Load data 40

Load data FF

Pause 10 mS

Notes for boot block lockout enable:

1. Data Format: DQ7−DQ0 (Hex)

2. Address Format: A14−A0 (Hex)

3. If you have any questions about this commend sequence, please contact the local distributor or Winbond Electronics Corp.

Publication Release Date: April 1999

- 9 - Revision A1

W29C020C

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER RATING UNIT

Power Supply Voltage to VSS Potential -0.5 to +7.0 V Operating Temperature 0 to +70 °C Storage Temperature -65 to +150 °C D.C. Voltage on Any Pin to Ground Potential Except A9 -0.5 to VDD +1.0 V Transient Voltage (<20 nS ) on Any Pin to Ground Potential -1.0 to VDD +1.0 V

Voltage on A9 and OE Pin to Ground Potential

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

-0.5 to 12.5 V

Operating Characteristics

(VDD = 5.0V ±10%, VSS = 0V, TA = 0 to 70° C)

PARAMETER SYM. TEST CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

Power Supply Current

Standby VDD Current (TTL input)

Standby VDD Current (CMOS input)

Input Leakage Current Output Leakage Current

ICC

ISB1

ISB2

ILI VIN = GND to VDD - - 10 µA ILO VIN = GND to VDD - - 10 µA

= OE = VIL, WE = VIH,

all DQs open Address inputs = VIL/VIH,

at f = 5 MHz

= VIH, all DQs open

Other inputs = VIL/VIH

= VDD -0.3V, all DQs open

- - 50 mA

- 2 3 mA

- 20 100 µA

Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage

CMOS

VIL VIH VOL IOL = 2.0 mA - - 0.45 V VOH1 IOH = -400 µA 2.4 - - V VOH2 IOH = -100 µA; VCC = 4.5V 4.2 - - V

- 10 -

- - 0.8 V

2.0 - - V

W29C020C

Input

Power-up Timing

PARAMETER SYMBOL TYPICAL UNIT

Power-up to Read Operation TPU. READ 100 µS Power-up to Write Operation TPU. WRITE 5 mS

CAPACITANCE

(VDD = 5.0V, TA = 25° C, f = 1 MHz)

PARAMETER SYMBOL CONDITIONS MAX. UNIT

DQ Pin Capacitance CDQ VDQ = 0V 12 pF Input Pin Capacitance CIN VIN = 0V 6 pF

AC CHARACTERISTICS

AC Test Conditions

(VDD = 5.0V ±10% for 90 nS and 120 nS; VDD = 5.0V ±5% for 70 nS)

PARAMETER CONDITIONS

Input Pulse Levels 0V to 3V Input Rise/Fall Time <5 nS Input/Output Timing Level 1.5V/1.5V Output Load 1 TTL Gate and CL = 100 pF for 90/120 nS

CL = 30 pF for 70 nS

AC Test Load and Waveform

OUT

100 pF for 90/120 nS

30 pF for 70 nS

(Including Jig and Scope)

Test Point Test Point

+5V

1.8K

Ω

1.3K

Ω

Output

1.5V 1.5V

Publication Release Date: April 1999

- 11 - Revision A1

W29C020C

AC Characteristics, continued

Read Cycle Timing Parameters

(VDD = 5.0V ±10% for 90 nS and 120 nS; VDD = 5.0V ±5% for 70 nS, VSS = 0V, T A = 0 to 70° C)

PARAMETER SYM. W29C020C-70 W29C020C-90 W29C020C-12 UNIT

MIN. MAX. MIN. MAX. MIN. MAX.

Read Cycle Time TRC 70 - 90 - 120 - nS Chip Enable Access Time TCE - 70 - 90 - 120 nS Address Access Time TAA - 70 - 90 - 120 nS Output Enable Access Time TOE - 35 - 40 - 50 nS

High to High-Z Output

Output Hold from Address change TOH 0 - 0 - 0 - nS

Byte/Page-write Cycle Timing Parameters

TCHZ - 25 - 25 - 30 nS TOHZ - 25 - 25 - 30 nS

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Write Cycle (erase and program) TWC - - 10 mS Address Setup Time TAS 0 - - nS Address Hold Time TAH 50 - - nS

and CE Setup Time

and CE Hold Time High Setup Time High Hold Time

Pulse Width

High Width

Data Setup Time TDS 50 - - nS Data Hold Time TDH 0 - - nS Byte Load Cycle Time TBLC - - 150 µS

Note: All AC timing signals observe the following guideline for determining setup and hold times:

Reference level is VIH for high-level signal and VIL for low-level signal.

TCS 0 - - nS TCH 0 - - nS TOES 0 - - nS TOEH 0 - - nS TCP 70 - - nS TWP 70 - - nS TWPH 100 - - nS

- 12 -

AC Characteristics, continued

DATA

W29C020C

Polling Characteristics

(1)

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Data Hold Time TDH 10 - - nS

Hold Time to Output Delay

(2)

TOEH 10 - - nS TOE - - - nS

Write Recovery Time TWR 0 - - nS

Notes:

(1) These parameters are characterized and not 100% tested. (2) See TOE spec in A.C. Read Cycle Timing Parameters.

Toggle Bit Characteristics

(1)

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Data Hold Time TDH 10 - - nS

Hold Time to Output Delay High Pulse

(2)

TOEH 10 - - nS TOE - - - nS TOEHP 150 - - nS

Write Recovery Time TWR 0 - - nS

Notes:

(1) These parameters are characterized and not 100% tested. (2) See TOE spec in A.C. Read Cycle Timing Parameters.

TIMING WAVEFORMS

Read Cycle Timing Diagram

Address A17-0

DQ7-0

High-Z

OHZ

CHZ

Data ValidData Valid

High-Z

Publication Release Date: April 1999

- 13 - Revision A1

Timing Waveforms, continued

Controlled Write Cycle Timing Diagram

Address A17-0

W29C020C

DQ7-0

OES

Controlled Write Cycle Timing Diagram

Address A17-0

DQ7-0

High Z

TAS

OES

TAH

CS T CH

Data Valid

TDS

OEH

WPH

TWPH

OEH

Internal write starts

- 14 -

Internal Write Starts

Timing Waveforms, continued

DATA

Page Write Cycle Timing Diagram

Address A17-0

DQ7-0

W29C020C

TWC

TWP

Byte 0 Byte 1

Polling Timing Diagram

Address A17-0

OEH

DQ7

WPH

Byte 2

HIGH-Z

Byte N-1

Internal Write Start

Byte N

TBLC

Publication Release Date: April 1999

- 15 - Revision A1

Timing Waveforms, continued

Internal write starts

(last word)

SW2

SW1

DQ7-0

Toggle Bit Timing Diagram

W29C020C

DQ6

TOEH

HIGH-Z

Page Write Timing Diagram Software Data Protection Mode

Byte/page load cycle starts

Byte N-1

Address A17-0

Three-byte sequence for

software data protection mode

5555 5555

2AAA

BLC

SW0

WPH

Byte 0

Byte N

- 16 -

Timing Waveforms, continued

SW1

DQ7-0

Internal programming starts

Address A14-0

SW4

Internal erasing starts

2AAA

Reset Software Data Protection Timing Diagram

W29C020C

Address A14-0

5555 2AAA

TWP

TWPH

SW0

BLC

Software Chip Erase Timing Diagram

Six-byte sequence for resetting software data protection mode

5555 5555 2AAA 5555

80 AA 55

SW2

SW3 SW4 SW5

Six-byte code for 5V-only software chip erase

DQ7-0

5555

SW0

TWPH

5555 5555 2AAA 5555

55 80

TBLC

SW2

SW1

SW3

- 17 - Revision A1

SW5

Publication Release Date: April 1999

ORDERING INFORMATION

W29C020C

PART NO. ACCESS

TIME

(nS)

W29C020C-12 120 50 100 600 mil DIP 1K W29C020CP-12 120 50 100 32-pin PLCC 1K W29C020C-70B 70 50 100 600 mil DIP 10K W29C020C-90B 90 50 100 600 mil DIP 10K W29C020C-12B 120 50 100 600 mil DIP 10K W29C020CT70B 70 50 100 Type one TSOP 10K W29C020CT90B 90 50 100 Type one TSOP 10K W29C020CT12B 120 50 100 Type one TSOP 10K W29C020CP70B 70 50 100 32-pin PLCC 10K W29C020CP90B 90 50 100 32-pin PLCC 10K W29C020CP12B 120 50 100 32-pin PLCC 10K

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.

POWER

SUPPLY CURRENT

MAX. (mA)

STANDBY

VDD CURRENT

MAX. (µA)

PACKAGE CYCLING

- 18 -

PACKAGE DIMENSIONS

1.Dimensions D Max. & S include mold flash or

2.Dimension E1 does not include interlead flash.

3.Dimensions D & E1 include mold mismatch and

6.General appearance spec. should be based on

32-pin P-DIP

W29C020C

1 16

32-pin TSOP

0.10(0.004)

Dimension in inches

Symbol

Min. Nom. Max. Max.Nom.Min.

0.010

0.150

0.155

0.016

0.018

0.050 1.27

0.010

0.008

c D E

0.545 14.1013.9713.84

E1 e

0.120

0 15

1.650 1.660 41.91 42.16

0.6000.590 0.610

0.550

0.130

0.6500.630 16.00 16.51

Base Plane

Seating Plane

Notes:

tie bar burrs.

are determined at the mold parting line.

4.Dimension B1 does not include dambar protrusion/intrusion.

5.Controlling dimension: Inches.

final visual inspection spec.

Dimension in Inches

Symbol

Min. Nom. Max. Min. Nom. Max.

__ __ __ __

Note:

A A A

H D

b c D E

e L

__ __

0.002

0.007 0.008

0.005 0.006 0.007

0.720 0.724

0.311 0.315

0.780 0.787

0.020

0.016 0.020

0.031

0.000 0.004 1

Dimension in mm

0.210 5.33

0.25

0.160

3.81

0.022

0.41

0.0540.048

0.014

0.20

0.555

2.29 2.54 2.790.090 0.100 0.110

0.140

3.05

0.670

0.085 2.16

0.047

0.006

0.05

0.95

0.0410.0390.037

0.17

0.009

0.12

18.30

0.728

7.90

0.319

19.80

0.795

__ __

0.024

__ __

3 5

3.94

4.06

0.46

0.56

1.371.22

0.25

0.36

15.49

15.2414.99

3.30

3.56 150

17.02

Dimension in mm

1.20

0.15

1.051.00

0.20 0.23

0.15 0.17

18.40 18.50

8.00 8.10

20.00 20.20

0.50

0.40

0.50 0.60

0.80

____

0.00

3 5

0.10

Controlling dimension: Millimeters

Publication Release Date: April 1999

- 19 - Revision A1

Package Dimensions, continued

Notes:

bcDeH

32-pin PLCC

324

14 20

Seating Plane

b b

W29C020C

G D

Dimension in Inches Dimension in mm

Symbol

Min. Nom. Max. Max.Nom.Min.

0.020

A b

0.008

0.447

0.490

0.485

L y

1. Dimensions D & E do not include interlead flash.

2. Dimension b1 does not include dambar protrusion/intrusion.

3. Controlling dimension: Inches.

4. General appearance spec. should be based on final visual inspection sepc.

0.140

0.50

0.1150.105 0.110

0.0320.026 0.028

0.41 0.46 0.56

0.0220.0180.016

0.20

0.014

0.010

0.450

0.050

0.510

0.490



13.89 13.97 14.05

0.5530.5500.547

11.35

0.453

12.45 12.95 13.46

0.530

0.4300.4100.390

14.86 14.99 15.11

0.5950.5900.585

12.32

0.495

0.0950.0900.075

0.004



1.12 1.420.044 0.056

9.91 10.41 10.92

1.91 2.29

3.56

2.802.67 2.93

0.710.66 0.81

0.35

0.25

11.51

11.43

1.27

12.57

12.45

2.41

0.10



- 20 -

VERSION HISTORY

VERSION DATE PAGE DESCRIPTION

A1 Apr. 1999 - Initial Issued

W29C020C

Headquarters

No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502

Note: All data and specifications are subject to change without notice.

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064

Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.

2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666

FAX: 408-5441798

Publication Release Date: April 1999

- 21 - Revision A1

Rainbow Electronics W29C020C User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual