Rainbow Electronics ATF1504ASVL User Manual
Features
• High-density, High-performance, Electrically-erasable Complex
ProgrammableLogic D evice
– 3.0 to 3.6V Operating Range
– 64 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 44, 68, 84, 100 Pins
–15nsMaximumPin-to-pinDelay
– Registered Operation up to 77 MHz
– Enhanced Routing Resources
• In-System Programmability (ISP) via JTAG
• Flexible Logic Macrocell
– D/T/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Out put Slew Rate
– Programmable Out put Open-collector Option
– Maximum Logic Utilization by Burying a Register with a COM Output
• Advanced Power Management Features
– Automatic 5 µA Standby for “L” Version
– Pin-control led 100 µA Standby Mode (Typical)
– Programmable Pin-keeper Circuits on Inputs and I/Os
– Reduced-power Feature per Macrocell
• Avai lable in Commercial and Industrial Temperature Ranges
• Avai lable in 44-, 68-, and 84-lead PLCC; 44- and 100-lead TQFP; and 100-lead PQFP
• Advanced EE Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
• JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
• PCI-compliant
• Security Fuse Feature
Low-voltage,
Complex
Programmable
Logic Device
ATF1504ASV
ATF1504ASVL
Enhanced Features
• ImprovedConnectivity (Additional Feedback Routing, Alternate Input Routing)
• Output Enable Product Terms
• Transparent-latch Mode
• Combinatorial Output wi th Registered Feedback within Any Macrocell
• Three Global Clock Pins
• ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
• Fast Registered I nput from Product Term
• Programmable“Pin-keeper” Option
• V
Power-up Reset Option
CC
• Pull-up Option on JTAG Pins TMS and TDI
• Advanced Power Management Features
– Edge-controlled Power-down “L”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O
Rev. 1409H–PLD–09/02
1
I/O/TDI
GND
PD1/I/O
TMS/I/O
VCC
44-lead TQFP
Top View
I/O
I/O
I/O
VCC
GCLK2/OE2/I
GCLR/I
I/OE1
GCLK1/I
GND
GCLK3/I/O
I/O
4443424140393837363534
33
1
2
I/O
3
I/O
4
5
6
I/O
7
8
I/O
9
10
I/O
11
I/O
1213141516171819202122
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
PD2/I/O
I/O
32
I/O/TDO
31
I/O
30
I/O
29
VCC
28
I/O
27
I/O
26
I/O/TCK
25
I/O
24
GND
23
I/O
I/O
TDI/I/O
I/O
I/O
GND
PD1/I/O
I/O
I/O/TMS
I/O
VCC
I/O
I/O
44-lead PLCC
Top View
I/O
I/O
I/O
VCC
GCLK2/OE2/I
GCLR/I
OE1/I
GCLK1/I
65432
7
8
9
10
11
12
13
14
15
16
17
1819202122232425262728
I/O
I/O
1
4443424140
I/O
I/O
I/O
VCC
GND
PD2/I/O
GND
GCLK3/I/O
I/O
I/O
I/O
39
I/O
38
I/O/TDO
37
I/O
36
I/O
35
VCC
34
I/O
33
I/O
32
I/O/TCK
31
I/O
30
GND
29
I/O
I/O
VCCIO
I/O/TD1
GND
I/O/PD1
I/O/TMS
VCCIO
GND
68-lead PLCC
Top View
I/O
I/O
I/O
GND
I/O
I/O
VCCINT
GCLK2/OE2/I
GCLR/I
OE1/I
987654321
10
I/O
11
12
13
I/O
14
I/O
15
I/O
16
17
18
I/O
19
20
I/O
21
22
I/O
23
I/O
24
I/O
25
I/O
26
2728293031323334353637383940414243
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
GND
VCCINT
68676665646362
I/O
GCLK1/I
GND
GND
I/O/PD2
GCLK3/I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VCCIO
I/O
I/O
GND
I/O/TDO
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O/TCK
I/O
GND
I/O
I/O
I/O
I/O
VCCIO
I/O/TDI
GND
I/O/PD1
I/O/TMS
VCCIO
GND
84-lead PLCC
Top View
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCINT
GCLK2/OE2/I
I/GCLR
I/OE1
GCLK1/I
GND
987654321
11
10
12
I/O
13
14
15
I/O
16
I/O
17
I/O
18
I/O
19
20
21
I/O
22
I/O
23
24
I/O
25
I/O
26
27
I/O
28
I/O
29
I/O
30
I/O
31
I/O
32
333435363738394041424344454647484950515253
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
848382818079787776
I/O
I/O
I/O
GND
VCCINT
I/O/PD2
GCLK3/I/O
I/O
I/O
I/O
I/O
GND
VCCIO
1/O
I/O
I/O
I/O
I/O
I/O
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
VCCIO
I/O
I/O
GND
I/O/TDO
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O/TCK
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
2
ATF1504ASV(L)
1409H–PLD–09/02
ATF1504ASV(L)
VCCIO
I/O/TDI
GND
I/O/PD1
I/O/TMS
VCCIO
GND
100-lead PQF P
Top View
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
INPUT/GCLK1
GND
I/O/GCLK3
I/O
I/O
VCCIO
I/O
I/O
I/O
99989796959493929190898887868584838281
100
1
NC
2
NC
3
I/O
4
I/O
5
6
7
NC
8
I/O
9
NC
10
I/O
11
I/O
12
I/O
13
14
15
I/O
16
I/O
17
18
I/O
19
I/O
20
21
I/O
22
I/O
23
I/O
24
NC
25
I/O
26
NC
27
I/O
28
29
NC
30
NC
31323334353637383940414243444546474849
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
GND
VCCINT
GND
I/O/PD2
I/O
80
NC
79
NC
78
I/O
77
I/O
76
GND
75
I/O/TDO
74
NC
73
I/O
72
NC
71
I/O
70
I/O
69
I/O
68
VCCIO
67
I/O
66
I/O
65
I/O
64
I/O/TCK
63
I/O
62
I/O
61
GND
60
I/O
59
I/O
58
I/O
57
NC
56
I/O
55
NC
54
I/O
53
VCCIO
52
NC
51
NC
50
I/O
I/O
I/O
VCCIO
I/O/TDI
GND
I/O/PD1
I/O/TMS
VCCIO
NC
1
NC
2
3
4
NC
5
I/O
6
NC
7
I/O
8
I/O
9
I/O
10
11
12
I/O
13
I/O
14
15
I/O
16
I/O
17
18
I/O
19
I/O
20
I/O
21
NC
22
I/O
23
NC
24
I/O
25
I/O
9998979695949392919089888786858483828180797877
100
26272829303132333435363738394041424344454647484950
NC
NC
GND
100-lead TQFP
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Top View
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
I/O
I/O
I/O
VCCIO
INPUT/OE1
INPUT/GCLK1
GND
I/O
GND
VCCINT
I/O/GCLK3
I/O
I/O
I/O
GND
I/O/PD2
VCCIO
I/O
I/O
I/O
I/O
I/O
I/ONCNC
I/O
I/O
I/O
76
I/O
75
GND
74
I/O/TDO
73
NC
72
I/O
71
NC
70
I/O
69
I/O
68
I/O
67
VCCIO
66
I/O
65
I/O
64
I/O
63
I/O/TCK
62
I/O
61
I/O
60
GND
59
I/O
58
I/O
57
I/O
56
NC
55
I/O
54
NC
53
I/O
52
VCCIO
51
NC
NC
1409H–PLD–09/02
3
Description The ATF1504ASV(L) is a high-p erformance, high-density complex programmable logic
device (CPLD ) that u tilizesAtmel’sproven electr ically-erasable memory technology.
With 64 logic macrocells and up to 68 inputs, it easily integrateslogicfromseveral TTL,
SSI, MSI, LSI and classic PLDs. The ATF1504ASV(L)’s enhanced routing s w it c h matricesincrease usab le ga te count and the odds of su ccessful pin-lockeddesi gn
modifications.
The ATF1504ASV(L) has up to 68 bi-directional I /O pins and four dedicated input pins,
depending on the type of device package selected. Each dedicatedpincanalsoserve
as a global control signal, register clock, regis terreset or output enable. Each of these
control signals can be selectedforuse individually within each macrocell.
Each of the 64 macrocells generates a buriedfeedback that goestothe global bus.
Each input and I/Opinalsofeeds into the global bus. The switch ma trix in each logic
block thenselects 40 individual si gnals from the global bus. Each macrocell also generatesafoldbacklogicterm that goestoareg ional bus. Cascade logic between
macrocells in the ATF1504ASV(L) allows fast, efficient generation of comp lex logic functions. The ATF 1504ASV(L) contains four such logic chains, each capable of creating
sum term l ogic with a fan-in of up to 40 product term s.
The ATF1504ASV(L)macrocell, shownin Figure1,isflexibleenough to s upport highlycomplex logic functions operat ing at high speed. The macrocell consi sts of five sections:
product terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop,
output select and enable, an d logic array inputs.
4
ATF1504ASV(L)
1409H–PLD–09/02
Block Diagram
ATF1504ASV(L)
Product Terms and Select Mux
1409H–PLD–09/02
Unused product terms are automatically disabledbythe co m p i l ertodecrease power
consum ptio n. Asecurity fuse,whenprogrammed , pr otects the contents of the
ATF1504ASV(L). Two bytes(16bits)ofUserSignature are accessible to the userfor
purposes such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the security fuse.
The ATF 1504ASV( L)device is an in-system programmable (ISP)device. It usesthe
industry-st andard 4-pin JTAG interface (IEE E St d. 1149.1), and is fully-compliant with
JTAG’s Boundary-scan Description Language (BSDL). ISP allows the device to be programmed without removing it from the printed c ircuit board. I n addition to simplifying the
manufacturing flow, ISP also allows design modifications to be made in t he field via
software.
Each ATF1504ASV(L)macrocell has five product terms. Each product term receivesas
its inputs all signals from both the global bus and regional bus .
The product term select multiplexer(PTMUX) allocatesthe five product term s a s
neededtothe macrocell logic gates a nd control signal s . ThePTMUX programming is
determinedbythe design compiler, which selects the optimum macrocell configuration.
5
OR/XOR/CASCADE Logic The ATF1504ASV(L)’s logic structure is designedtoefficiently support all types of logic.
Within a single macrocell, all the product terms can be routedtothe OR gate,creating a
5-input AND/OR sum term. With the addition of t he CASIN from neigh boring macrocells,
this can beexpandedtoasmanyas40 product terms with little additio nal delay.
The macrocell’sXOR gate allows efficient im plementation of compare and arithmetic
functions. One input to the XOR comesfromthe OR sum term. The otherXOR input can
be a product term or a fixed high- or low-level. For co mbi natorial outputs, the fixedlevel
input allows polarity selection. For registered functions, the fixedlevels allow DeMorgan
minimization of product terms. The XOR gate is also usedtoemulate T- an d JK-type
flip-flops.
Flip-flop The ATF1504ASV(L)’s flip-flop has very flexible data and control functions. The data
input can come from eitherthe XOR gate,fromaseparat e product term o r directly from
the I/Opin. Selecting the sepa rate product term allows creation of a buriedregistered
feedback within a combinatorial output macrocell. (This feature is automatically implementedbythe fitter software). In ad dition to D,T,JKandSR operation, the flip-flop can
also be configured as a flow-through latch. In this mode, data passes through whenthe
clock is high and is latchedwhenthe clock is low.
The clock itself can eitherbe one of the Global C LK Signal (GCK[0 : 2]) or an individual
product term. The flip-flop changesstate on the clock’s rising edge. Whenthe GCK signal is usedasthe clock, one of the macrocell product terms c an be selectedasaclock
enable. Whenthe clock enable function is active and theenable signal (produc t term) is
low, all clock edgesare ignored. The flip-flop’s asynchronous resetsignal(AR)canbe
eitherthe G lobal Clear (GCLEAR), a product term, or always off. AR canalsobe a logic
OR of GCLEAR with a product term. The asy nc hronous preset(AP)canbe aproduct
term or always off.
Extra Feedback The ATF1504ASV(L)macrocell output can be selectedasregistered or combina to rial.
Theextra buriedfeedback si gnal can beeither combinatorial o r a registered signa l
regardl ess of wh etherthe output is combinatorial or registered. (This enhan cement
function is automatically implementedbythe fittersoftware.)Feedback o f a b uried
combinatorial output allows the creation of a second latch within a macrocell.
I/O Control The output enable multiplexer(MOE)controlsthe output enable sig nal. Each I/Ocanbe
individually configured as an input, output or for bi-directional operation. The output
enable for each macrocell can be selectedfromthe true or compliment of the tw o output
enable pins, a subsetofthe I/O pins, or a subsetofthe I/Omacrocells. This selection is
automatically done by the fitter software whenthe I/Oisconfigured as an input, all mac-
rocell resourcesare still available, including t he buriedfeedback, expander and cascade
logic.
Global Bus/Switch Matrix The global bus contains a ll input and I/O pin signals as well as the buriedfeedback sig-
nal from all 64 macrocells. The switch matrix in eac h logic block receivesasitsinputsall
signals from the global bus. Un der software control, up to 40 of these signals can be
selected as inputs t o the logic block.
Foldback Bus Each macrocell also generates a foldback product term. This signal goestothe regional
bus and is available to four macrocells. The foldback is an inverse polarity of one of the
macrocell’sproductterms. The four foldback terms in each r egion allow generation of
high fan-in sum terms (up to nine product terms) with little additional delay.
6
ATF1504ASV(L)
1409H–PLD–09/02
Figure 1. ATF1504ASV(L)Macrocell
ATF1504ASV(L)
Programmable Pin-keeper Option for Inputs and I/Os
The ATF1504ASV( L)offers the option of programming all input and I/Opinssothatpinkeepercircuitscanbe utilized.
Whenanypinisdrivenhighorlowandthen subsequently left floating, it will stay at that previous high- or low-level. This cir-
cuitry prevents unusedinputandI/Olines from floating to intermedi atevoltage levels, which causesunneces sary p ow er
consumption and system noise. The keepercircuitseliminate the needforexternal pull-up resistors and eliminate their DC
power consumption.
1409H–PLD–09/02
7
Input Diagram
I/O Diagram
Speed/Power Management
8
ATF1504ASV(L)
The ATF1504ASV(L) has several built-in speed and power management feat ur es. The
ATF1504ASV(L) co ntai ns circuitry that autom aticall y puts the device into a low power
standby mode when no lo gic transitions are oc curring. This not only reducespower consumption during inactive periods, but also provides proportional powersavi ngs for most
applications running at systemspeeds below 5 MHz. This feature may be selectedasa
device option.
To furtherreduc e power, eac h ATF1504ASV(L)macrocell has a reduced-powerbitfea-
ture. Thi s feature allows individual macrocells to be configured for maximum power
savings. This feature may be selectedasadesign option.
All ATF1504ASV(L)alsohave an optional power-down mode. In this mode,current
drops to below 5 mA. Whenthe power-dow n option is selected, either PD1 or PD2 pins
(or both) can be usedtopower down the part. The power-down option is selectedinthe
design source file. When enabled, the device goes into pow er down when either PD1 or
PD2 is high. In the pow er-down mode, all internal logic signals are latched and held, as
are any enabled outputs.
All pin transitions are ignored until thePDpin is brought low. Whenthe power-down fea-
ture is enabled, thePD1or PD2 pin c annot be used as a logic in put or output.However,
the pin’smacrocel l ma y still b e usedtogenerate buried foldback and cascade logic
signals.
1409H–PLD–09/02
ATF1504ASV(L)
All power-down AC c haracteristic parameters are computedfromexternal inpu t or I/O
pins, with reduced-powerbitturnedon. For macrocells in reduced-powermode
(reduced-powerbitturned on), t he reduced-power adder, t
parameters, which include the data paths t
LAD,tLAC,tIC,tACL,tACH
The ATF1504ASV(L)macrocell also has an option whereby the powercanbe reduced
on a permacrocell basis. By enabling this power-down option, macrocells that are not
used in an application can be turned down, thereby reducing the overall power consumption of the device.
Each output also has individual slewrate co ntrol. This may be usedtoreduce s yst em
noise by slowing down outputs that do not needtooperate at maximum speed. Outputs
default to slow switching, and may be specified as f as t switching in the design file.
,mustbe addedtothe AC
RPA
and t
SEXP
.
Design So ft ware Support
ATF1504ASV(L)designs are s upportedbyseveral industry standard third party tools.
Automatedfitters allow logic s yn thesi s usi n g a variety of high-leveldescription languages and formats.
Power-up Reset The ATF1504ASV is designed with a power-up reset, a feature critical for state machine
initialization. At a point delayedslightlyfromV
tialized, and the state of each output will depend on the polarity of its buffer.However,
due to the asynchronous nature of resetanduncertainty of how V
system, the following conditions are required:
1. The V
rise must be monotonic,
CC
2. Afterreset occurs, all input and feedback setup timesmustbe metbefore dr iving
the clock pin high, and,
3. The c lock must remain stable during T
D
The ATF1504ASV has two options for the hysteresis about the resetlevel, V
and Large. To ensure a robust operating environment in applications where the device
is operatednear 3.0V, Atmelrecommends that during the fitting process users configure
the device with thePower-up Resethysteresis settoLarge. For conversions, A tmel
POF2JED users should i nc lude the flag “-power_reset” on the command line after “filename.POF”. To allow the registers to be properly reinitializedwiththeLarge hysteresis
option selected, the following condition is added:
4. If V
falls below 2.0V, it must shut off completely before the device is turnedon
CC
again.
.
crossing V
CC
,allregisters will be ini-
RST
actually risesinthe
CC
RST
,Small
WhentheLarge hysteresisoptionisactive,I
is reducedbyseveral hundredmicro-
CC
amps as well.
Security Fuse Usage Asingle fuse is providedtoprevent unau thorized copying of the ATF1504ASV(L)fuse
patterns. Onc e programmed, fuseverify is inhibited.However, the16-bit User Signature
remains accessible.
1409H–PLD–09/02
9
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