Rainbow Electronics AT89S52 User Manual

Features

•Compatible with MCS-51® Products

•8K Bytes of In-System Programmable (ISP) Flash Memory

–Endurance: 1000 Write/Erase Cycles

•4.0V to 5.5V Operating Range

•Fully Static Operation: 0 Hz to 33 MHz

•Three-level Program Memory Lock

•256 x 8-bit Internal RAM

•32 Programmable I/O Lines

•Three 16-bit Timer/Counters

•Eight Interrupt Sources

•Full Duplex UART Serial Channel

•Low-power Idle and Power-down Modes

•Interrupt Recovery from Power-down Mode

•Watchdog Timer

•Dual Data Pointer

•Power-off Flag

Description

The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the indus- try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.

The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.

8-bit Microcontroller with 8K Bytes In-System Programmable Flash

AT89S52

Rev. 1919A-07/01

1

Pin Configurations

PDIP

(T2)

P1.0

1

40

VCC

(T2 EX) P1.1

2

39

P0.0

(AD0)

P1.2

3

38

P0.1

(AD1)

P1.3

4

37

P0.2

(AD2)

P1.4

5

36

P0.3

(AD3)

(MOSI) P1.5

6

35

P0.4

(AD4)

(MISO) P1.6

7

34

P0.5

(AD5)

(SCK) P1.7

8

33

P0.6

(AD6)

RST

9

32

P0.7

(AD7)

(RXD) P3.0

10

31

EA/VPP

(TXD) P3.1

11

30

ALE/PROG

P3.2

12

29

(INT0)

PSEN

P3.3

13

28

P2.7

(A15)

(INT1)

(T0)

P3.4

14

27

P2.6

(A14)

(T1)

P3.5

15

26

P2.5

(A13)

P3.6

16

25

P2.4

(A12)

(WR)

P3.7

17

24

P2.3

(A11)

(RD)

XTAL2

18

23

P2.2

(A10)

XTAL1

19

22

P2.1

(A9)

GND

20

21

P2.0

(A8)

TQFP

									(T2 EX)	(T2)		VCC	(AD0)	(AD1)	(AD2)	(AD3)
					P1.4		P1.3	P1.2	P1.1	P1.0	NC		P0.0	P0.1	P0.2	P0.3
			44			43		42	41	40	39	38	37	36	35	34
(MOSI) P1.5			1													33	P0.4		(AD4)
(MISO) P1.6			2													32	P0.5		(AD5)
(SCK) P1.7			3													31	P0.6		(AD6)
		RST	4													30	P0.7		(AD7)
(RXD) P3.0			5													29
																	EA/VPP
		NC	6													28	NC
(TXD) P3.1			7													27
																	ALE/PROG
		P3.2	8													26
	(INT0)																PSEN
		P3.3	9													25	P2.7		(A15)
	(INT1)
	(T0) P3.4		10													24	P2.6		(A14)
	(T1) P3.5		11													23	P2.5		(A13)
			12			13		14	15	16	17	18	19	20	21	22
					(WR) P3.6		(RD) P3.7	XTAL2	XTAL1	GND	GND	(A8) P2.0	(A9) P2.1	(A10) P2.2	(A11) P2.3	(A12) P2.4

				P1.4
			6
(MOSI) P1.5			7
(MISO) P1.6			8
(SCK) P1.7			9
		RST	10
(RXD) P3.0			11
		NC	12
(TXD) P3.1			13
		P3.2	14
	(INT0)
		P3.3	15
	(INT1)
	(T0) P3.4		16
	(T1) P3.5		17
			18
				(WR) P3.6

PLCC

		(T2 EX)	(T2)		VCC	(AD0)	(AD1)	(AD2)
P1.3	P1.2	P1.1	P1.0	NC		P0.0	P0.1	P0.2
5	4	3	2	1	44	43	42	41

19		20	21	22	23	24	25	26	27
	(RD) P3.7	XTAL2	XTAL1	GND	NC	(A8) P2.0	(A9) P2.1	(A10) P2.2	(A11) P2.3

P0.3 (AD3)
40	P0.4		(AD4)
39
38	P0.5		(AD5)
37	P0.6		(AD6)
36	P0.7		(AD7)
35
	EA/VPP
34	NC
33
	ALE/PROG
32
	PSEN
31	P2.7		(A15)
30	P2.6		(A14)
29	P2.5		(A13)
28
(A12) P2.4

2	AT89S52

AT89S52

Block Diagram

P0.0 - P0.7

P2.0 - P2.7

VCC

PORT 0 DRIVERS

PORT 2 DRIVERS

GND

		RAM ADDR.	RAM	PORT 0	PORT 2	FLASH
		REGISTER		LATCH	LATCH
	B				STACK		PROGRAM
		ACC					ADDRESS
	REGISTER				POINTER
							REGISTER
							BUFFER
		TMP2		TMP1
							PC
			ALU				INCREMENTER
				INTERRUPT, SERIAL PORT,
					AND TIMER BLOCKS
							PROGRAM
			PSW				COUNTER
PSEN
ALE/PROG	TIMING	INSTRUCTION					DUAL DPTR
	AND
		REGISTER
EA / VPP	CONTROL
RST
		WATCH	PORT 3		PORT 1	ISP	PROGRAM
		DOG	LATCH		LATCH	PORT	LOGIC
	OSC
			PORT 3 DRIVERS		PORT 1 DRIVERS
			P3.0	- P3.7	P1.0	- P1.7

3

Pin Description

VCC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.

Port 0 can also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups.

Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pullups are required during program verification.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.

In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table.

Port 1 also receives the low-order address bytes during Flash programming and verification.

Port Pin	Alternate Functions
P1.0	T2 (external count input to Timer/Counter 2),
	clock-out
P1.1	T2EX (Timer/Counter 2 capture/reload trigger
	and direction control)
P1.5	MOSI (used for In-System Programming)
P1.6	MISO (used for In-System Programming)
P1.7	SCK (used for In-System Programming)

Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.

Port 2 emits the high-order address byte during fetches from external program memory and during accesses to

external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.

Port 3

Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.

Port 3 also serves the functions of various special features of the AT89S52, as shown in the following table.

Port 3 also receives some control signals for Flash programming and verification.

Port Pin			Alternate Functions
P3.0			RXD (serial input port)
P3.1			TXD (serial output port)
P3.2							(external interrupt 0)
			INT0
P3.3							(external interrupt 1)
		INT1
P3.4			T0 (timer 0 external input)
P3.5			T1 (timer 1 external input)
P3.6					(external data memory write strobe)
			WR
P3.7				(external data memory read strobe)
			RD

RST

Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 96 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.

ALE/PROG

Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.

In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.

If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is

4	AT89S52

AT89S52

weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

PSEN

Program Store Enable (PSEN) is the read strobe to external program memory.

When the AT89S52 is executing code from external pro-

gram memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.

EA/VPP

External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH.

Table 1. AT89S52 SFR Map and Reset Values

Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.

EA should be strapped to VCC for internal program executions.

This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

0F8H									0FFH
0F0H	B								0F7H
	00000000
0E8H									0EFH
0E0H	ACC								0E7H
	00000000
0D8H									0DFH
0D0H	PSW								0D7H
	00000000
0C8H	T2CON	T2MOD	RCAP2L	RCAP2H	TL2	TH2			0CFH
	00000000	XXXXXX00	00000000	00000000	00000000	00000000
0C0H									0C7H
0B8H	IP								0BFH
	XX000000
0B0H	P3								0B7H
	11111111
0A8H	IE								0AFH
	0X000000
0A0H	P2		AUXR1				WDTRST		0A7H
	11111111		XXXXXXX0				XXXXXXXX
98H	SCON	SBUF							9FH
	00000000	XXXXXXXX
90H	P1								97H
	11111111
88H	TCON	TMOD	TL0	TL1	TH0	TH1	AUXR		8FH
	00000000	00000000	00000000	00000000	00000000	00000000	XXX00XX0
80H	P0	SP	DP0L	DP0H	DP1L	DP1H		PCON	87H
	11111111	00000111	00000000	00000000	00000000	00000000		0XXX0000

5

Special Function Registers

A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1.

Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.

User software should not write 1s to these unlisted locations, since they may be used in future products to invoke

Table 2. T2CON – Timer/Counter 2 Control Register

new features. In that case, the reset or inactive values of the new bits will always be 0.

Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 3) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.

Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.

T2CON Address = 0C8H

Reset Value = 0000 0000B

Bit Addressable

Bit

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2

CP/RL2

7

6

5

4

3

2

1

0

Symbol

Function

TF2

Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1

or TCLK = 1.

EXF2

Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.

When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be

cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).

RCLK

Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port

Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.

TCLK

Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port

Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.

EXEN2

Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer

2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.

TR2

Start/Stop control for Timer 2. TR2 = 1 starts the timer.

C/T2

Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered).

= 0

CP/RL2

Capture/Reload select. CP/RL2

= 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2

causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When

either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

6	AT89S52

AT89S52

Table 3a. AUXR: Auxiliary Register

AUXR

Address = 8EH

Reset Value = XXX00XX0B

Not Bit Addressable

–

–

–

WDIDLE

DISRTO

–

–

DISALE

Bit

7

6

5

4

3

2

1

0

–

Reserved for future expansion

DISALE

Disable/Enable ALE

DISALE

Operating Mode

0

ALE is emitted at a constant rate of 1/6 the oscillator frequency

1

ALE is active only during a MOVX or MOVC instruction

DISRTO

Disable/Enable Reset out

DISRTO

0

Reset pin is driven High after WDT times out

1

Reset pin is input only

WDIDLE

Disable/Enable WDT in IDLE mode

WDIDLE

0

WDT continues to count in IDLE mode

1

WDT halts counting in IDLE mode

Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the

appropriate value before accessing the respective Data Pointer Register.

Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and rest under software control and is not affected by reset.

Table 3b. AUXR1: Auxiliary Register 1

AUXR1

Address = A2H

Reset Value = XXXXXXX0B

Not Bit Addressable

–

–

–

–

–

–

–

DPS

Bit

7

6

5

4

3

2

1

0

–

Reserved for future expansion

DPS

Data Pointer Register Select

DPS

0

Selects DPTR Registers DP0L, DP0H

1

Selects DPTR Registers DP1L, DP1H

7

Memory Organization

MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.

Program Memory

If the EA pin is connected to GND, all program fetches are directed to external memory.

On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.

Data Memory

The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space.

When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing access of the SFR space.

For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).

MOV 0A0H, #data

Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).

MOV @R0, #data

Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.

8	AT89S52

Watchdog Timer

(One-time Enabled with Reset-out)

The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 13-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.

Using the WDT

To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 13-bit counter overflows when it reaches 8191 (1FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 8191 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 96xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.

WDT During Power-down and Idle

In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S52 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode.

AT89S52

To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode.

Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S52 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode.

With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.

UART

The UART in the AT89S52 operates the same way as the UART in the AT89C51 and AT89C52. For further information on the UART operation, refer to the ATMEL Web site (http://www.atmel.com). From the home page, select ‘Products’, then ‘8051-Architecture Flash Microcontroller’, then ‘Product Overview’.

Timer 0 and 1

Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For further information on the timers’ operation, refer to the ATMEL Web site (http://www.atmel.com). From the home page, select ‘Products’, then ‘8051-Architecture Flash Microcontroller’, then ‘Product Overview’.

Timer 2

Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.

Table 3. Timer 2 Operating Modes

RCLK +TCLK	CP/RL2			TR2	MODE
0	0			1	16-bit Auto-reload
0	1			1	16-bit Capture
1	X			1	Baud Rate Generator
X	X			0	(Off)

9