Rainbow Electronics ATF1502ASV User Manual

Features

• High-density, High-performance, Electrically- erasable Complex Programmable

Logic Device

– 3.0 to 3.6V Operating Range
– 32 Macrocell s
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
–44Pins
–15nsMaximumPin-to-pinDelay
– Registered Operation up to 77 MHz
– Enhanced Routing Resources

• In-System Programmability (ISP) via JTAG

• Flexible Logic Macrocell

– D/T Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic Utilization by Burying a Register with a COM Output

• Advanced Power Management Features

– Pin-controlled 0.75 mA Standby Mode
– ProgrammablePin-keeper Inputs and I/Os
– Reduced-power Feature per Macrocell

• Avai lable in Commercial and Industrial Temperature Ranges

• Avai lable in 44-lead PLCC and TQFP

• Advanced EEPROM Technol o gy

– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20-year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity

• JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Support ed

• PCI-compliant

• Security Fuse Feature

High­performance
EEPROM CPLD

ATF1502ASV

Enhanced Features

• ImprovedConnectivity (Additional Feedback Routing, Alternate Input Routing)

• Output Enable Product Ter ms

• D Latch Mode

• Combinatorial Output with Registered Feedback within Any Macrocell

• Three Global Clock Pins

• Fast Registered Input from Product Term

• Programmable“Pin-keeper” Option

• V

Power-up Reset Option

CC

• Pull-up Option on JTAG Pins TMS and TDI

• Advanced Power Management Features

– Individual Macrocell Power Option

Rev. 1615G–PLD–09/02

1

I/O/TDI

GND

PD1/I/O

TMS/I/O

VCC

I/O
I/O

I/O

I/O

I/O
I/O

44-lead TQFP

Top View

I/O

I/O

I/O

VCC

GCLK2/OE2/I

GCLR/I

4443424140393837363534

1
2
3
4
5
6
7
8
9
10
11

1213141516171819202122

I/O

I/O

I/O

I/O

VCC

GND

44-lead PLCC

Top View

I/OE1

I/O

GCLK1/I

GND

I/O

PD2/I/O

GCLK3/I/O

I/O

33
32
31
30
29
28
27
26
25
24
23

I/O

I/O

I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O

I/O

I/O

I/O

VCC

GCLK2/OE2/I

GCLR/I

OE1/I

GCLK1/I

GND

GCLK3/I/O

I/O

TDI/I/O

I/O
I/O

GND

PD1/I/O

I/O

I/O/TMS

I/O

VCC

I/O
I/O

65432

7
8
9
10
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12
13
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15
16
17

1819202122232425262728

I/O

I/O

I/O

I/O

GND

1

VCC

4443424140

I/O

I/O

I/O

PD2/I/O

39
38
37
36
35
34
33
32
31
30
29

I/O

I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O

Description The ATF1502ASV is a high-performance, high-density complex programmable logic

device (CPLD) that utilizes Atmel’s proven electrically-erasable technology. With 32
logic macrocells and up to 36 inputs, it easily integrates logic from several TTL, SSI,
MSI, LSI and classic PLDs. The ATF1502ASV’s enhanced routing switch matrices
increase usable gate count and the odds of successful pin-locked design modifications.

The ATF1502ASV has up to 32 bi-directional I /O pins and four dedicated input pins,
depending o n the type o f device package selected. Each dedicated pin can also serve
as a global control signal, registe r clock, regi ster reset or output enable. Each of these
control signals can be selected for use individua lly within each macrocell.

2

ATF1502ASV

1615G–PLD–09/02

Block Diagram

ATF1502ASV

B

32

Each of the 32 m acrocells generates a buried feedback that goes to the global bus.
Each input and I/O pin also feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus. Each macrocell also gener­ates a foldb ack l ogic term t hat g oes to a regional bus. C asca de l ogic between
macrocells in the ATF1502ASV allows fast, efficient generation of comp lex logic func ­tions. The ATF1502ASV contains four such logic chains, each capable of creating sum
termlogicwithafan-inofupto40 product terms.

The ATF1502ASV macrocell, shown in Figure 1, is flexible enough to support highly
complex logic funct ions operating at high speed. The macrocell c ons ists of five sections:
product terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop,
output select and enable, and logic array inputs.

1615G–PLD–09/02

Unused product terms are automatically disabled by the compiler to decrease power
consumption. A security fuse, when programmed, protects the contents of the
ATF1502ASV. Two bytes (16 bits) of User Signature are accessible to the user for pur­poses such as sto ring project name, part number, revision or date. The User Signature
is accessible regardless of the state of the sec urity fuse.

The ATF1502ASV device is an in-system programmable (ISP) device. It uses the i ndus­try standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s

3

Figure 1. ATF1502ASV Macrocell

Boundary-scan Description Language (BSDL). ISP allows the dev ice to be programmed
without removing it from the printed circuit board. In addition to simplifying the manufac­turing flow, ISP also allows design modifications to be made in the f ield via sof tware.

Product Terms and Select Mux

OR/XOR/ CASCADE Logic

4

ATF1502ASV

Each ATF1502ASV m ac r oc ell has five product terms. Each product term receives as its
inputs all signals from both the global bus and regional bus.

The product term select multiplexer (PTMUX ) allocates the five product terms as
needed to the macrocell logic gates and control signals. The PTMUX programming is
determined by the design compiler, which selects the optimum macrocell configuration.

The ATF1502ASV’s logic struc ture is design ed to efficiently suppo rt all types of logic.
Within a single macrocell, all the product terms can be routed to the O R gate, creating a
5-input AND/OR s um term. With the addition of the CA SIN from neighboring macrocells,
this can be expanded to as many as 40 product terms with little additional delay.

The macrocell’s XOR gate allows efficient implementation of compare and arithmetic
functions. One input t o the XOR comes from the OR sum term. The other XOR input c an
be a p roduct term or a fixed high or low level. For combinatorial outputs, the fixed level
input allows polarity selection. For registered functions, the fixed levels allow DeMorgan
minimization of product terms. The XOR gate is also used to emulate T- and JK-type
flip-flops.

1615G–PLD–09/02

ATF1502ASV

Flip-flop The ATF1502ASV’s flip-flop h as very flexible data and control functions. The dat a input

cancomefromeithertheXOR gate , fr om a separate product term or directly from the
I/O pin . Selecting the separate product term all ows creation of a buried registered feed­back within a combinatorial output macroc ell . (This feature is automatically implemented
by the fitter software). In addition to D, T, JK and SR operation, the flip-flop can also be
configured as a flow-through latch. In this mode, data passes through when the clock is
high and is latched when the clock is low.

The clock itself can be either one of the Global CLK signals (GCK[0 : 2]) or an individual
product term. The flip-flop changes state on the clock’s rising edge. When the GCK sig­nal is used as the clock, one of the macrocell product terms can be selected as a clock
enable. When the clock enable function is active and the enable signal (p ro duc t term) is
low, all clock edges are ignored. The flip-flop’s asynchronous reset signal (AR) can be
either the Global Clear (GCLEAR), a product term, or always off. AR can also be a logic
OR of GCLEAR with a product term. The asynchronous preset (AP) can be a product
term or always off.

Extra Feedback The ATF1502ASV macrocell output can be selected as registered or combinatorial.The

extra burie d feedback signal can be either com binatorial or a regist ered signal regard­less of whether the output is combinatorial or registered. (This enhancement function is
autom atical ly implemented by t he fitter soft ware.) Feedback of a buried combinatorial
output allow s the creation of a second latch within a macrocell.

I/O Control The outpu t enable multiplexer (MOE) controls the out put enable signal. Each I/O can be

individually configured as an input, output or for bi-directional operation. The output
enable for each macrocell can be selected from the true or compliment of the t wo output
enable pins, a subset of the I/O pins, or a subset of the I/O macroc ells. This selection is
automatically done by the fitter software when the I/O is configured as an input, all mac­rocell resources are still av ailab le, including the buried feedback, expander and cas ca de
logic.

Global Bus/Switch Matrix The global bus contains all i nput and I/O pin signals as well as the buried feed bac k sig-

nal from all 32 macrocells. The switch matrix in each logic block receives as its inputs all
signals from the global bus. Under software control, up to 40 of these signals can be
selected as inputs to the logic block.

Foldback Bus Each macrocell also generates a foldback product term. This signal goes to the regional

bus and is available to four macrocells. The foldback i s an inverse polarity of one of the
macro cell’s product term s . The four foldback ter ms in each region allow generation of
high fan-in sum terms (up to nine product terms) with little additional delay.

Programmable Pin­keeper Option for
Inputs and I/Os

The ATF1502ASV offers the option of programming all input and I/O pins so that pin­keeper circuits can be utilized. When any pin is driven high or low and then subse­quently left floating , it will stay at that previous high or low level. This circuitry prevent s
unused input and I/O lines from floating to intermediate voltage levels, which causes
unnecessary power consumption and system noise. The keeper circuits eliminate the
need for external pull-up resistors and eliminate their DC power consumption.

1615G–PLD–09/02

5

Input Diagram

V

CC

I/O Diagram

INPUT

DATA

OE

ESD

PROTECTION

CIRCUIT

V

CC

100K

PROGRAMMABLE

OPTION

I/O

V

CC

100K

Speed/Power Management

6

ATF1502ASV

PROGRAMMABLE

OPTION

The ATF1502ASV has several b uilt-in speed and power management features .
To further reduce power, eac h ATF1502ASV macrocell has a reduced-power bit feature.

To reduce power consumption this feature may be actived (by changing the default
value of OFF to ON) for any or all macrocells.

The ATF1502ASV also has an optional power-down mode. In this mode, current drops
to below 15 mA. When the power-down option is select ed, either PD 1 o r PD2 pins (or
both) can be used to power down the part. The power-down option is selected in the
design source file. When enabled, the device goes into power-down when either PD1 or
PD2 is high. In the power-down mode, all internal logic signals are latched and held, as
are any enabled outputs.

All pin transitions are ignored until the PD pin is brought low. When the power-down fea­ture is enabled, the P D1 or PD2 pin cannot be used as a logic input or output. However,
the pin’s macrocell may still be used to generate buried foldback and cascade logic
signals.

1615G–PLD–09/02

ATF1502ASV

All powe r-down AC cha racteristic parameters are computed from ext ernal inpu t or I/O
pins, with reduced-power bit turned on. F or macrocells in reduced-power mode
(reduced-power bit turned on), the reduced-power adder, t
parameters, which include the data paths t

LAD,tLAC,tIC,tACL,tACH

The ATF1502ASV macrocell also has an option whereby the power can be reduced on
a per-macrocell basis. By enabling this power-down option, macrocells that are not used
in an application can be turned down, thereby reducing the overall power consumption
of the device.

Each output also has i ndividual slew rate control. Thi s m ay be used to re duce system
noise by slowing down outputs that do not ne ed to op erate at m ax imu m speed. Outputs
default to slow switching, and may be specified as fast switching in the design file.

, must be added to the AC

RPA

and t

SEXP

.

Design Software Support

ATF1502ASV des igns are supported by several third-party tools. Automated fitters allow
logic synthesis using a variety of high-level description languages a nd formats.

Power-up Reset The ATF1502ASV is designed with a power-up reset, a feature critical for state machine

initialization. At a point delayed slightly from V
tialized, and the state of eac h o utput will depend on the polarity of its buffer. Howev er,
due to the asynchronous nature of reset and uncertainty of how V
system, the following conditions are required:

1. The V

rise must be m onotonic,

CC

2. After reset occurs, all input and feedback s et up times must be met before
driving the clock pin high, and,

3. The clock must remain stable during T

The ATF1502ASV has two options for the hysteresis about the reset level, V
and Large. To ensure a robust operating env ironment in applications where the dev ice
is operated near 3.0V, Atmel recommends that during the fitting p roce ss users configure
the device with the Power-up Reset hysteresis set to Large. For conversions, Atmel
POF2JED users should i nc lude the flag “-power_reset” on the command line after “file­name.POF”. To allow the registers to be properly reinitial ized with the Large hysteresis
option selec ted, the following condition is added:

4.IfV

falls below 2.0V, it must shut off completely before the device is turned

CC

on again.

When t he Large hysteresis opt ion is act ive, I
amps as well.

crossing V

CC

.

D

is reduced by several hundred micro-

CC

, all registers will be ini-

RST

actually rises in the

CC

RST

,Small

Security Fuse Usage A single fuse is provided to prevent unaut horized copying of the ATF1502ASV fuse pat-

terns. Once programmed, fuse verify is inhibited. However, the 16-bit User Signature
remains accessible.

Programming ATF1502ASV devices are in-system programmable (ISP) devices utilizing the 4-pin

JTAG protocol. This capability eliminates package handling normally required for pro-

gramming and facilitates rapid design iterations and field changes.
Atmel provides ISP hardware and software to allow programming of the ATF1502ASV

via t he PC. ISP is performed by using either a download cable, a comparable board
tester or a simple microprocessor interface.

1615G–PLD–09/02

7