Rainbow Electronics ATF1502ASL User Manual

Features

• High-density, High-performance, Electrically-erasable Complex Programmable

Logic Device

– 32 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
–44Pins
– 7.5 ns Maximum Pin-to-pin Delay
– Registered Operation up to 125 MHz
– Enhanced Routing Resources

• In-System Programmability (ISP) via JTAG

• Flexible Logic Macrocell

– D/T Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic Utilization by Burying a Register with a COM Output

• Advanced Power Management Features

• Automatic10µAStandbyfor“L”Version

• Pin-controlled 1 mA Standby Mode

• Programmable Pin-keeper Inputs and I/Os

• Reduced-power Feature per Macrocell

• Available in Commercial and Industrial Temperature Ranges

• Available in 44-lead PLCC and TQFP

• Advanced EEPROM Technology

– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20-year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity

• JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

• PCI-compliant

• Security Fuse Feature

High­performance
EEPROM CPLD

ATF1502AS
ATF1502ASL

Enhanced Features

• Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

• Output Enable Product Terms

• D Latch Mode

• Combinatorial Output with Registered Feedback within Any Macrocell

• Three Global Clock Pins

• ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O

(“L” versions)

• Fast Registered Input from Product Term

• Programmable “Pin-keeper” Option

• V

Power-up Reset Option

CC

• Pull-up Option on JTAG Pins TMS and TDI

• Advanced Power Management Features

– Input Transition Detection
– Power-down (“L” versions)
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O

Rev. 0995J–PLD–09/0 2

1

I/O/TDI

GND

PD1/I/O

TMS/I/O

VCC

TDI/I/O

PD1/I/O

I/O/TMS

I/O
I/O

I/O

I/O

I/O
I/O

I/O
I/O

GND

I/O

I/O

VCC

I/O
I/O

44-lead TQFP

Top Vi e w

I/O

I/O

I/O

VCC

GCLK2/OE2/I

GCLR/I

I/OE1

4443424140393837363534

1
2
3
4
5
6
7
8
9
10
11

1213141516171819202122

I/O

I/O

I/O

I/O

I/O

VCC

GND

44-lead PLCC

Top Vi e w

I/O

I/O

I/O

VCC

GCLK2/OE2/I

GCLR/I

OE1/I

65432

7
8
9
10
11
12
13
14
15
16
17

1819202122232425262728

1

4443424140

GCLK1/I

GND

I/O

PD2/I/O

GCLK1/I

GND

GCLK3/I/O

I/O

33
32
31
30
29
28
27
26
25
24
23

I/O

I/O

GCLK3/I/O

I/O

39
38
37
36
35
34
33
32
31
30
29

I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O

I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

GND

VCC

I/O

PD2/I/O

Description The ATF1502AS is a high-performance, high-density complex programmable logic device

(CPLD) that utilizes Atmel’s proven electrically-erasable technology. With 32 logic macrocells
and up to 36 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic
PLDs. The ATF1502AS’s enhanced routing switch matrices increase usable gate count and
the odds of successful pin-locked design modifications.

The ATF1502AS has up to 32 bi-directional I/O pins and four dedicated input pins, depending
on the type of device package selected. Each dedicated pin can also serve as a global control
signal, register clock, register reset or output enable. Each of these control signals can be
selected for use individually within each macrocell.

2

ATF1502AS(L)

0995J–PLD–09/02

Block Diagram

32

ATF1502AS(L)

B

Each of the 32 macrocells generates a buried feedback that goes to the global bus. Each input
and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40
individual signals from the global bus. Each macrocell also generates a foldback logic term
that goes to a regional bus. Cascade logic between macrocells in the ATF1502AS allows fast,
efficient generation of complex logic functions. The ATF1502AS contains four such logic
chains, each capable of creating sum term logic with a fan-in of up to 40 product terms.

The ATF1502AS macrocell, shown in Figure 1, is flexible enough to support highly complex
logic functions operating at high speed. The macrocell consists of five sections: product terms
and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select and
enable, and logic array inputs.

Unused product terms are automatically disabled by the compiler to decrease power con­sumption. A security fuse, when programmed, protects the contents of the ATF1502AS. Two
bytes (16 bits) of User Signature are accessible to the user for purposes such as storing
project name, part number, revision or date. The User Signature is accessible regardless of
the state of the security fuse.

The ATF1502AS device is an in-system programmable (ISP) device. It uses the industry stan­dard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundary­scan Description Language (BSDL). ISP allows the device to be programmed without remov­ing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also
allows design modifications to be made in the field via software.

0995J–PLD–09/02

3

Figure 1. ATF1502AS Macrocell

Product Terms and Select Mux

OR/XOR/ CASCADE Logic

Each ATF1502AS macrocell has five product terms. Each product term receives as its inputs
all signals from both the global bus and regional bus.

The product term select multiplexer (PTMUX) allocates the five product terms as needed to
the macrocell logic gates and control signals. The PTMUX programming is determined by the
design compiler, which selects the optimum macrocell configuration.

The ATF1502AS’s logic structure is designed to efficiently support all types of logic. Within a
single macrocell, all the product terms can be routed to the OR gate, creating a 5-input
AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be
expanded to as many as 40 product terms with little additional delay.

The macrocell’s XOR gate allows efficient implementation of compare and arithmetic func­tions. One input to the XOR comes from the OR sum term. The other XOR input can be a
product term or a fixed high or low level. For combinatorial outputs, the fixed level input allows
polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of
product terms. The XOR gate is also used to emulate T- and JK-type flip-flops.

Flip-flop The ATF1502AS’s flip-flop has very flexible data and control functions. The data input can

come from either the XOR gate, from a separate product term or directly from the I/O pin.
Selecting the separate product term allows creation of a buried registered feedback within a
combinatorial output macrocell. (This feature is automatically implemented by the fitter soft­ware). In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flow­through latch. In this mode, data passes through when the clock is high and is latched when
the clock is low.

4

ATF1502AS(L)

0995J–PLD–09/02

ATF1502AS(L)

The clock itself can be either one of the Global CLK signals (GCK[0 : 2]) or an individual prod­uct term. The flip-flop changes state on the clock’s rising edge. When the GCK signal is used
as the clock, one of the macrocell product terms can be selected as a clock enable. When the
clock enable function is active and the enable signal (product term) is low, all clock edges are
ignored. The flip-flop’s asynchronous reset signal (AR) can be either the Global Clear
(GCLEAR), a product term, or always off. AR can also be a logic OR of GCLEAR with a prod­uct term. The asynchronous preset (AP) can be a product term or always off.

Extra Feedback The ATF1502AS(L) macrocell output can be selected as registered or combinatorial. The

extra buried feedback signal can be either combinatorial or a registered signal regardless of
whether the output is combinatorial or registered. (This enhancement function is automatically
implemented by the fitter software.) Feedback of a buried combinatorial output allows the cre­ation of a second latch within a macrocell.

I/O Control The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be indi-

vidually configured as an input, output or for bi-directional operation. The output enable for
each macrocell can be selected from the true or compliment of the two output enable pins, a
subset of the I/O pins, or a subset of the I/O macrocells. This selection is automatically done
by the fitter software when the I/O is configured as an input, all macrocell resources are still
available, including the buried feedback, expander and cascade logic.

Global Bus/Switch Matrix

The global bus contains all input and I/O pin signals as well as the buried feedback signal from
all 32 macrocells. The switch matrix in each logic block receives as its inputs all signals from
the global bus. Under software control, up to 40 of these signals can be selected as inputs to
the logic block.

Foldback Bus Each macrocell also generates a foldback product term. This signal goes to the regional bus

and is available to four macrocells. The foldback is an inverse polarity of one of the macrocell’s
product terms. The four foldback terms in each region allow generation of high fan-in sum
terms (up to nine product terms) with little additional delay.

Programmable Pin-keeper Option for Inputs and I/Os

The ATF1502AS offers the option of programming all input and I/O pins so that pin-keeper cir­cuits can be utilized. When any pin is driven high or low and then subsequently left floating, it
will stay at that previous high or low level. This circuitry prevents unused input and I/O lines
from floating to intermediate voltage levels, which causes unnecessary power consumption
and system noise. The keeper circuits eliminate the need for external pull-up resistors and
eliminate their DC power consumption.

0995J–PLD–09/02

5

Input Diagram

I/O Diagram

Speed/Power Management

6

ATF1502AS(L)

The ATF1502AS has several built-in speed and power management features. The
ATF1502AS contains circuitry that automatically puts the device into a low-power standby
mode when no logic transitions are occurring. This not only reduces power consumption dur­ing inactive periods, but also provides proportional power savings for most applications
running at system speeds below 50 MHz. This feature may be selected as a design option.

To further reduce power, each ATF1502AS macrocell has a reduced-power bit feature. This
feature allows individual macrocells to be configured for maximum power savings. This feature
may be selected as a design option.

The ATF1502AS also has an optional power-down mode. In this mode, current drops to below
10 mA. When the power-down option is selected, either PD1 or PD2 pins (or both) can be
used to power down the part. The power-down option is selected in the design source file.
When enabled, the device goes into power-down when either PD1 or PD2 is high. In the
power-down mode, all internal logic signals are latched and held, as are any enabled outputs.

0995J–PLD–09/02

ATF1502AS(L)

All pin transitions are ignored until the PD pin is brought low. When the power-down feature is
enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s
macrocell may still be used to generate buried foldback and cascade logic signals.

All power-down AC characteristic parameters are computed from external input or I/O pins,
with reduced-power bit turned on. For macrocells in reduced-power mode (reduced-power bit
turned on), the reduced-power adder, t
include the data paths t

The ATF1502AS macrocell also has an option whereby the power can be reduced on a per­macrocell basis. By enabling this power-down option, macrocells that are not used in an appli­cation can be turned down, thereby reducing the overall power consumption of the device.

Each output also has individual slew rate control. This may be used to reduce system noise by
slowing down outputs that do not need to operate at maximum speed. Outputs default to slow
switching, and may be specified as fast switching in the design file.

LAD,tLAC,tIC,tACL,tACH

, must be added to the AC parameters, which

RPA

and t

SEXP

.

Design
Software

ATF1502AS designs are supported by several third-party tools. Automated fitters allow logic
synthesis using a variety of high-level description languages and formats.

Support

Power-up Reset The ATF1502AS is designed with a power-up reset, a feature critical for state machine initial-

ization. At a point delayed slightly from V
the state of each output will depend on the polarity of its buffer. However, due to the asynchro­nous nature of reset and uncertainty of how V
conditions are required:

1. The V

2. After reset occurs, all input and feedback setup times must be met before driving the
clock pin high, and,

3. The clock must remain stable during T

The ATF1502AS has two options for the hysteresis about the reset level, V
Large. During the fitting process users may configure the device with the Power-up Reset hys­teresis set to Large or Small. Atmel POF2JED users may select the Large option by including
the flag “-power_reset” on the command line after “filename.POF”. To allow the registers to be
properly reinitialized with the Large hysteresis option selected, the following condition is
added:

4. If V

When the Large hysteresis option is active, I
well.

rise must be monotonic,

CC

falls below 2.0V, it must shut off completely before the device is turned on again.

CC

crossing V

CC

actually rises in the system, the following

CC

.

D

is reduced by several hundred microamps as

CC

, all registers will be initialized, and

RST

RST

, Small and

Security Fuse Usage

A single fuse is provided to prevent unauthorized copying of the ATF1502AS fuse patterns.
Once programmed, fuse verify is inhibited. However, the 16-bit User Signature remains
accessible.

Programming ATF1502AS devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG pro-

tocol. This capability eliminates package handling normally required for programming and
facilitates rapid design iterations and field changes.

0995J–PLD–09/02

7

Atmel provides ISP hardware and software to allow programming of the ATF1502AS via the
PC. ISP is performed by using either a download cable, a comparable board tester or a simple
microprocessor interface.

When using the ISP hardware or software to program the ATF1502AS devices, four I/O pins
must be reserved for the JTAG interface. However, the logic features that the macrocells have
associated with these I/O pins are still available to the design for burned logic functions.

To facilitate ISP programming by the Automated Test Equipment (ATE) vendors, Serial Vector
Format (SVF) files can be created by Atmel-provided software utilities.

ATF1502AS devices can also be programmed using standard third-party programmers. With a
third-party programmer, the JTAG ISP port can be disabled, thereby allowing four additional
I/Opinstobeusedforlogic.

Contact your local Atmel representatives or Atmel PLD applications for details.

ISP Programming Protection

JTAG-BST/ISP Overview

The ATF1502AS has a special feature that locks the device and prevents the inputs and I/O
from driving if the programming process is interrupted for any reason. The inputs and I/O
default to high-Z state during such a condition. In addition, the pin-keeper option preserves the
previous state of the input and I/O PMS during programming.

All ATF1502AS devices are initially shipped in the erased state, thereby making them ready to
use for ISP.

Note: For more information refer to the “Designing for In-System Programmability with Atmel CPLDs”

application note.

The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the
ATF1502AS. The boundary-scan technique involves the inclusion of a shift-register stage
(contained in a boundary-scan cell) adjacent to each component so that signals at component
boundaries can be controlled and observed using scan testing methods. Each input pin and
I/O pin has its own boundary-scan cell (BSC) to support boundary-scan testing. The
ATF1502AS does not include a Test Reset (TRST) input pin because the TAP controller is
automatically reset at power-up. The five JTAG modes supported include:
SAMPLE/PRELOAD, EXTEST, BYPASS, IDCODE and HIGHZ. The ATF1502AS’s ISP can
be fully described using JTAG’s BSDL as described in IEEE Standard 1149.1b. This allows
ATF1502AS programming to be described and implemented using any one of the third-party
development tools supporting this standard.

The ATF1502AS has the option of using four JTAG-standard I/O pins for boundary-scan test­ing (BST) and in-system programming (ISP) purposes. The ATF1502AS is programmable
through the four JTAG pins using the IEEE standard JTAG programming protocol established
by IEEE Standard 1149.1 using 5V TTL-level programming signals from the ISP interface for
in-system programming. The JTAG feature is a programmable option. If JTAG (BST or ISP) is
not needed, then the four JTAG control pins are available as I/O pins.

8

ATF1502AS(L)

0995J–PLD–09/02

ATF1502AS(L)

JTAG Boundary-scan Cell (BSC) Testing

BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins)

The ATF1502AS contains up to 32 I/O pins and four input pins, depending on the device type
and package type selected. Each input pin and I/O pin has its own boundary-scan cell (BSC)
in order to support boundary-scan testing as described in detail by IEEE Standard 1149.1. A
typical BSC consists of three capture registers or scan registers and up to two update regis­ters. There are two types of BSCs, one for input or I/O pin, and one for the macrocells. The
BSCs in the device are chained together through the capture registers. Input to the capture
register chain is fed in from the TDI pin while the output is directed to the TDO pin. Capture
registers are used to capture active device data signals, to shift data in and out of the device
and to load data into the update registers. Control signals are generated internally by the
JTAG TAP controller. The BSC configuration for the input and I/O pins and macrocells is
shown below.

BSC Configuration for Macrocell

Note: 1. The ATF1502AS has a pull-up option on TMS and TDI pins. This feature is selected as a

design option.

TDO

0

D

Q

OEJ

OUTJ

TDI

1

CLOCK

TDI

0

1

0

1

Shift

BSC for I/O Pins and Macrocells

DQ

DQ

Capture

DR

TDO

Clock

DQ

DQ

Update

DR

0

1

0

1

Mode

Pin

0995J–PLD–09/02

9

PCI Compliance The ATF1502AS also supports the growing need in the industry to support the new Peripheral

Component Interconnect (PCI) interface standard in PCI-based designs and specifications.
The PCI interface calls for high current drivers, which are much larger than the traditional TTL
drivers. In general, PLDs and FPGAs parallel outputs to support the high current load required
by the PCI interface. The ATF1502AS allows this without contributing to system noise while
delivering low output to output skew. Having a programmable high drive option is also possible
without increasing output delay or pin capacitance. The PCI electrical characteristics appear
on the next page.

PCI Voltage-to­current Curves
for +5V
Signaling in
Pull-up Mode

PCI Voltage-to­current Curves
for +5V
Signaling in
Pull-down Mode

VCC

2.4

1.4

VCC

Voltage

DC
drive point

-2

Voltage

AC drive

point

AC drive

point

Pull Up

-44

Pull Down

Current (mA)

Test Point

-178

10

ATF1502AS(L)

2.2

0.55

DC
drive point

3,6

95

Test Point

Current (mA)

380

0995J–PLD–09/02

ATF1502AS(L)

PCI DC Characteristics (Preliminary)

Symbol Parameter Conditions Min Max Units

V

V

V

I

IH

I

IL

V

V

C

C

C

L

CC

IH

IL

OH

OL

IN

CLK

IDSEL

PIN

Supply Voltage 4.75 5.25 V

Input High Voltage 2.0 VCC+0.5 V

Input Low Voltage -0.5 0.8 V

Input High Leakage Current

Input Low Leakage Current

Output High Voltage I

Output Low Voltage I

(1)

(1)

VIN=2.7V 70 µA

VIN= 0.5V -70 µA

=-2mA 2.4 V

OUT

=3mA,6mA 0.55 V

OUT

Input Pin Capacitance 10 pF

CLK Pin Capacitance 12 pF

IDSEL Pin Capacitance 8 pF

Pin Inductance 20 nH

Note: 1. Leakage current is with pin-keeper off.

PCI AC Characteristics (Preliminary)

Symbol Parameter Conditions Min Max Units

I

OH(AC)

Switching
Current High
(Test High)

0<V

1.4 < V

≤ 1.4 -44 mA

OUT

<2.4 -44+(V

OUT

OUT

-1.4)

/0.024

mA

I

OL(AC)

Switching
Current Low
(Test Point)

I

CL

SLEW

SLEW

Low Clamp Current -5 < VIN≤ -1 -25 + (VIN+1)

Output Rise Slew Rate 0.4V to 2.4V load 1 5 V/ns

R

Output Fall Slew Rate 2.4V to 0.4V load 1 5 V/ns

F

Notes: 1. Equation A: I

2. Equation B: I

=11.9(V

OH

= 78.5 * V

OL

- 5.25) * (V

OUT

*(4.4-V

OUT

3.1 < V

OUT<VCC

V

= 3.1V -142 µA

OUT

V

>2.2V 95 mA

OUT

2.2 > V

0.1 > V

V

OUT

>0 V

OUT

> 0 Equation B mA

OUT

/0.023 mA

OUT

=0.71 206 mA

Equation A mA

/0.015

+ 2.45) for VCC>V

OUT

)for0V<V

OUT

OUT

< 0.71V.

OUT

>3.1V.

mA

0995J–PLD–09/02

11

Power-down Mode

The ATF1502AS includes an optional pin-controlled power-down feature. When this mode is
enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply
current is reduced to less than 5 mA. During power-down, all output data and internal logic
states are latched and held. Therefore, all registered and combinatorial output data remain
valid. Any outputs that were in a high-Z state at the onset will remain at high-Z. During
power-down, all input signals except the power-down pin are blocked. Input and I/O hold
latches remain active to ensure that pins do not float to indeterminate levels, further reducing
system power. The power-down pin feature is enabled in the logic design file. Designs using
the power-down pin may not use the PD pin logic array input. However, all other PD pin mac­rocell resources may still be used, including the buried feedback and foldback product term
array inputs.

Power-down AC Characteristics

(1)(2)

Symbol Parameter

t

IVDH

t

GVDH

t

CVDH

t

DHIX

t

DHGX

t

DHCX

t

DLIV

t

DLGV

t

DLCV

t

DLOV

Notes: 1. For slow slew outputs, add t

Valid I, I/O before PD High 7 10 15 25 ns

Valid OE

Valid Clock

(2)

before PD High 7 10 15 25 ns

(2)

before PD High 7 10 15 25 ns

I, I/O Don’t Care after PD High 12 15 25 35 ns

(2)

OE

Don’t Care after PD High 12 15 25 35 ns

(2)

Clock

Don’t Care after PD High 12 15 25 35 ns

PD Low to Valid I, I/O 1 1 1 1 µs

PD Low to Valid OE (Pin or Term) 1 1 1 1 µs

PD Low to Valid Clock (Pin or Term) 1 1 1 1 µs

PD Low to Valid Output 1 1 1 1 µs

.

SSO

2. Pin or product term.

Absolute Maximum Ratings*

Temperature Under Bias .................................. -40°C to +85°C

Storage Temperature ..................................... -65°C to +150°C

Voltage on Any Pin with

Respect to Ground .........................................-2.0V to +7.0V

Voltage on Input Pins
with Respect to Ground

During Programming.....................................-2.0V to +14.0V

Programming Voltage with

Respect to Ground .......................................-2.0V to +14.0V

-7 -10 -15 -25

UnitsMin Max Min Max Min Max Min Max

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any

(1)

other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device

(1)

Note: 1. Minimum voltage is -0.6V DC, which may under-

reliability.

shoot to -2.0V for pulses of less than 20 ns.

(1)

which may overshoot to 7.0V for pulses of less

Maximum output pin voltage is V

+0.75VDC,

CC

than 20 ns.

12

ATF1502AS(L)

0995J–PLD–09/02

ATF1502AS(L)

DC and AC Operating Conditions

Commercial Industrial

Operating Temperature (Ambient) 0°C-70°C-40°C-85°C

V

(5V) Power Supply 5V ±5% 5V ± 10%

CC

DC Characteristics

Symbol Parameter Condition Min Typ Max Units

I

I

I

I

I

I

V

V

V

IL

IH

OZ

CC1

CC2

CC3

IL

IH

OL

Input or I/O Low

VIN=V

CC

-2 -10 µA

Leakage Current

Input or I/O High

210

Leakage Current

Tri-state Output

VO=VCCor GND -40 40 µA

Off-state Current

Power Supply Current, Standby VCC=Max

V

=0,V

IN

Std Mode Com. 60 mA

CC

Ind. 75 mA

“L” Mode Com. 10 µA

Ind. 10 µA

Power Supply Current,
Power-down Mode

(2)

Reduced-power Mode
Supply Current, Standby

VCC=Max
V

=0,V

IN

VCC=Max
V

=0,V

IN

“PD” Mode 1 5 mA

CC

Std Mode Com. 35 mA

CC

Ind. 40 mA

Input Low Voltage -0.3 0.8 V

Input High Voltage 2.0 V

Output Low Voltage (TTL) VIN=VIHor V

VCC=MIN,IOL=12mA

Output Low Voltage (CMOS) V

IN=VIH

or V

VCC=MIN,IOL=0.1mA

IL

IL

Com. 3.0 0.45 V

Ind. 0.45

Com. 0.2 V

Ind. 0.2 V

CCIO

+0.3 V

V

OH

Output High Voltage (TTL) VIN=VIHor V

IL

2.4 V

VCC=MIN,IOH=-4.0mA

Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.

2. I

0995J–PLD–09/02

refers to the current in the reduced-power mode when macrocell reduced-power is turned on.

CC3

13

Pin Capacitance

Typ Max Units Conditions

(1)

C

IN

C

I/O

Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.

The OGI pin (high-voltage pin during programming) has a maximum capacitance of 12 pF.

810pF V

810pF V

=0V;f=1.0MHz

IN

=0V;f=1.0MHz

OUT

Timing Model

Input Test Waveforms and Measurement Levels

tR,tF=1.5nstypical

Output AC Test Loads

14

ATF1502AS(L)

0995J–PLD–09/02

ATF1502AS(L)

AC Characteristics

Symbol Parameter

t

PD1

t

PD2

t

SU

t

H

t

FSU

t

FH

t

COP

t

CH

t

CL

t

ASU

t

AH

t

ACOP

t

ACH

t

ACL

t

CNT

f

CNT

t

ACNT

f

ACNT

f

MAX

t

IN

t

IO

t

FIN

t

SEXP

t

PEXP

t

LAD

t

LAC

t

IOE

t

OD1

t

ZX1

t

ZX2

Input or Feedback to Non-registered Output 7.5 10 3 15 25 ns

I/O Input or Feedback to Non-registered
Feedback

Global Clock Setup Time 6 7 11 20 ns

Global Clock Hold Time 0 0 0 0 ns

Global Clock Setup Time of Fast Input 3 3 3 5 ns

Global Clock Hold Time of Fast Input 0.5 0.5 1 2 MHz

Global Clock to Output Delay 4.5 5 8 13 ns

Global Clock High Time 3 4 5 7 ns

Global Clock Low Time 3 4 5 7 ns

Array Clock Setup Time 3 3 4 5 ns

Array Clock Hold Time 2 3 4 6 ns

Array Clock Output Delay 7.5 10 15 25 ns

Array Clock High Time 3 4 6 10 ns

Array Clock Low Time 3 4 6 10 ns

Minimum Clock Global Period 8 10 13 22 ns

Maximum Internal Global Clock Frequency 125 100 76.9 50 MHz

Minimum Array Clock Period 8 10 13 22 ns

Maximum Internal Array Clock Frequency 125 100 76.9 50 MHz

Maximum Clock Frequency 166.7 125 100 60 MHz

Input Pad and Buffer Delay 0.5 0.5 2 2 ns

I/O Input Pad and Buffer Delay 0.5 0.5 2 2 ns

Fast Input Delay 1 1 2 2 ns

Foldback Term Delay 4 5 8 12 ns

Cascade Logic Delay 0.8 0.8 1 2 ns

Logic Array Delay 3 5 6 8 ns

Logic Control Delay 3 5 6 8 ns

Internal Output Enable Delay 2 2 3 4 ns

Output Buffer and Pad Delay
(Slow slew rate = OFF;
V

=5V;CL=35pF)

CC

Output Buffer Enable Delay
(Slow slew rate = OFF;
V

=5.0V;CL=35pF)

CCIO

Output Buffer Enable Delay
(Slow slew rate = OFF;
V

=3.3V;CL=35pF)

CCIO

(1)

-7 -10 -15 -25

UnitsMin Max Min Max Min Max Min Max

7931225ns

21.5 4 6ns

4.0 5.0 7 10 ns

4.5 5.5 7 10 ns

0995J–PLD–09/02

15

AC Characteristics (Continued)

Symbol Parameter

(1)

-7 -10 -15 -25

UnitsMin Max Min Max Min Max Min Max

t

ZX3

Output Buffer Enable Delay
(Slow slew rate = ON;
V

= 5.0V/3.3V; CL=35pF)

CCIO

t

XZ

t

SU

t

H

t

FSU

t

FH

t

RD

t

COMB

t

IC

t

EN

t

GLOB

t

PRE

t

CLR

t

UIM

t

RPA

Output Buffer Disable Delay (CL= 5 pF) 4 5 6 8 ns

Register Setup Time 3 3 4 6 ns

Register Hold Time 2 3 4 6 ns

Register Setup Time of Fast Input 3 3 2 3 ns

Register Hold Time of Fast Input 0.5 0.5 2 5 ns

Register Delay 1 2 1 2 ns

Combinatorial Delay 1 2 1 2 ns

Array Clock Delay 3 5 6 8 ns

Register Enable Time 3 5 6 8 ns

Global Control Delay 1 1 1 1 ns

Register Preset Time 2 3 4 6 ns

Register Clear Time 2 3 4 6 ns

Switch Matrix Delay 1 1 2 2 ns

Reduced-power Adder

(2)

Notes: 1. See ordering information for valid part numbers.

2. The t

parameter must be added to the t

RPA

LAD,tLAC,tTIC,tACL

power mode.

9 9 10 12 ns

10 11 13 15 ns

,andt

parameters for macrocells running in the reduced-

SEXP

16

ATF1502AS(L)

0995J–PLD–09/02

ATF1502AS(L)

SUPPLY CURRENT VS. SUPPLY VOLTAGE

AS VERSION (TA= 25°C, F = 0)

70

60

50

40

(mA)

CC

30

I

20

10

0

4.5 4.75 5 5.25 5.5

STANDARD POWER

REDUCED POWER

V

CC

(V)

SUPPLY CURRENT VS. SUPPLY VOLTAGE

PIN-CONTROLLED POWER-DOWN MODE (T

14

12

10

8

(mA)

CC

6

I

4

2

0

4.5 4.75 5 5.25 5.5

TBD

(V)

V

CC

=25°C,F=0)

A

SUPPLY CURRENT VS. SUPPLY VOLTAGE

120.0

100.0

80.0

(µA)

60.0

CC

I

40.0

20.0

0.0

(T = 25°C, NON-TURBO, BIT6 = 0, BIT 30 = 0)

4.00 4.50 4.75 5.00 5.25 5.5 0 6.00

VCC (V)

SUPPLY CURRENT VS. F REQUENCY

60.0

ASL (LOW-POWER) VERSION (T

= 25°C)

A

SUPPLY CURRENT VS. FR EQUENCY

60.0

50.0

40.0

(mA)

30.0

CC

I

20.0

10.0

0.0

0.00 20.00 40.00 60.00 80.00 100.00

AS VERSION (T

STAND ARD POWER

FREQUENCY (MHz)

= 25°C)

A

REDUCED POWER

OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE

(V

=2.4V,TA= 25°C)

0.0

-10.0

-20.0

(mA)

-30.0

OH

I

-40.0

-50.0

-60.0

4.50 4.75 5.00 5.25 5.5 0

OH

SUPPLY VOLTAGE (V)

50.0

40.0

(mA)

30.0

CC

I

20.0

10.0

0.0

0.00 10.00 20.00 30.00 4 0.00 50.00

STANDARD POWER

REDUCED POWER

FRE QUE NCY (MHz )

OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE

=5V,TA= 25°C)

(V

0.0

-10.0

-20.0

-30.0

-40.0

-50.0

IOH (mA)

-60.0

-70.0

-80.0

-90.0

-100.0

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00

CC

OUTPUT VOLTAGE (V)

0995J–PLD–09/02

17

INPUT CLAMP CURRENT VS. INPUT VOLTAGE

=5V,TA= 25°C)

(V

0

-10

-20

-30

-40

INPUT CURRENT (mA)

-50

-60

-1.00 -0.80 -0.60 -0.40 -0.20 0.00

CC

INPU T VOLTAGE ( V)

INPUT CURRENT VS. INPUT VOLTAGE

(V

=5V,TA=25°C)

40

30

20

10

0

-10

INPUT CURRENT (mA)

-20

-30

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

CC

INPUT VOLTAGE (V)

OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE

43

42

41

40

39

38

IOL (mA)

37

36

35

34

4.50 4.75 5.00 5.25 5.50

(VOL = 0.5V, T

SUP PLY VOLT AGE (V)

= 25°C)

A

NORMALIZED TPD

1.20

VS. SUPPLY VOLTAGE (T

1.10

1.00

NORMALIZED TPD

0.90

0.80

4.54.85.05.35.5

SUPPLY VOLTAGE (V)

= 25°C)

A

OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE

(V

=5V,TA= 25°C)

140.0

120.0

100.0

80.0

60.0

IOL (mA)

40.0

20.0

0.0

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00

CC

OUTPUT VOLTAGE (V)

NORMALIZED TPD

1.2

VS. TEMPERATURE (V

1.1

1.0

NORMALIZED TPD

0.9

0.8

-40.0 0.0 25.0 75.0

TEMPERATURE(C)

CC

=5.0V)

18

ATF1502AS(L)

0995J–PLD–09/02

ATF1502AS(L)

NORMALIZED TCO

1.2

VS. SUPPLY VOLTAGE (T

1.1

1.0

NORMALIZED TPD

0.9

0.8

4.5 4.8 5 .0 5.3 5.5

SUPPLY VOLTAGE (V)

=25°C)

A

NORMALIZED TSU VS. SUPPLY VOLTAGE (TA=25°C)

1.2

1.1

1.0

NORMALIZED TSU

0.9

0.8

4.5 4.8 5.0 5.3 5.5

SUPPLY V OLTAGE (V)

NORMALIZED TCO

1.2

VS. TEMPERATURE (V

1.1

1.0

NORMALIZED TCO

0.9

0.8

-40.0 0.0 25.0 75.0

TEMPERATURE(C)

CC

=5.0V)

NORMALIZED TSU

1.2

VS. TEMPERATURE (V

1.1

1.0

NORMALIZE D TSU

0.9

0.8

-40.0 0.0 25.0 75.0

TEMPERATURE (C)

CC

=5.0V)

0995J–PLD–09/02

19

ATF1502AS Dedicated Pinouts

44-lead

Dedicated Pin

INPUT/OE2/GCLK2 40 2

INPUT/GCLR 39 1

INPUT/OE1 38 44

INPUT/GCLK1 37 43

I/O / GCLK3 35 41

I/O / PD (1,2) 5, 19 11, 25

I/O / TDI (JTAG) 1 7

I/O / TMS (JTAG) 7 13

I/O / TCK (JTAG) 26 32

I/O/TDO(JTAG) 32 38

GND 4, 16, 24, 36 10, 22, 30, 42

VCC 9, 17, 29, 41 3, 15, 23, 35

# of Signal Pins 36 36

# User I/O Pins 32 32

TQFP

44-lead

J-lead

OE (1, 2) Global OE pins

GCLR Global Clear pin

GCLK (1, 2, 3) Global Clock pins

PD (1, 2) Power-down pins

TDI, TMS, TCK, TDO JTAG pins used for boundary-scan testing or in-system programming

GND Ground pins

VCC VCC pins for the device (+5V)

20

ATF1502AS(L)

0995J–PLD–09/02

ATF1502AS I/O Pinouts

MC PLC 44-lead PLCC 44-lead TQFP

1A442

2A543

3A/PD1 644

4/TDI A71

5A82

6A93

7A115

8A126

9/TMS A137

10 A 14 8

11 A 16 10

12 A 17 11

13 A 18 12

ATF1502AS(L)

14 A 19 13

15 A 20 14

16 A 21 15

17 B 41 35

18 B 40 34

19 B 39 33

20/TDO B3832

21 B 37 31

22 B 36 30

23 B 34 28

24 B 33 27

25/TCK B3226

26 B 31 25

27 B 29 23

28 B 28 22

29 B 27 21

30 B 26 20

31 B 25 19

0995J–PLD–09/02

32 B 24 18

21

Ordering Information

t

PD

(ns)

7.5 4.5 166.7 ATF1502AS-7 AC44

10 5 125 ATF1502AS-10 AC44

15 8 100 ATF1502AS-15 AC44

25 13 60 ATF1502ASL-25 AC44

t

CO1

(ns)

f

MAX

(MHz) Ordering Code Package Operation Range

ATF1502AS-7 JC44

ATF1502AS-10 JC444

ATF1502AS-10 AI44
ATF1502AS-10 JI44

ATF1502AS-15 JC44

ATF1502AS-15 AI44
ATF1502AS-15 JI44

ATF1502ASL-25 JC44

ATF1502ASL-25 AI44
ATF1502ASL-25 JI44

44A
44J

44A
44J

44A
44J

44A
44J

44A
44J

44A
44J

44A
44J

Commercial

(0°Cto70°C)

Commercial

(0°Cto70°C)

Industrial

(-40°Cto+85°C)

Commercial

(0°Cto70°C)

Industrial

(-40°Cto+85°C)

Commercial

(0°Cto70°C)

Industrial

(-40°Cto+85°C)

Using “C” Product for Industrial

To use commercial product for industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.

Package Type

44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)

44J 44-lead, Plastic J-leaded Chip Carrier OTP (PLCC)

22

ATF1502AS(L)

0995J–PLD–09/02

Packaging Information

44A – TQFP

PIN 1

ATF1502AS(L)

B

PIN 1 IDENTIFIER

e

E1 E

D1

D

C

0˚~7˚

A1

L

Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.

3. Lead coplanarity is 0.10 mm maximum.

A2 A

SYMBOL

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 11.75 12.00 12.25

D1 9.90 10.00 10.10 Note 2

E 11.75 12.00 12.25

E1 9.90 10.00 10.10 Note 2

B 0.30 – 0.45

C 0.09 – 0.20

L 0.45 – 0.75

e 0.80 TYP

NOM

MAX

NOTE

R

0995J–PLD–09/02

2325 Orchard Parkway
San Jose, CA 95131

TITLE

44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

10/5/2001

DRAWING NO.

44A

REV.

B

23

44J–PLCC

1.14(0.045) X 45˚

B

e

0.51(0.020)MAX

45˚ MAX (3X)

Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC.

2. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.

3. Lead coplanarity is 0.004" (0.102 mm) maximum.

PIN NO. 1

IDENTIFIER

D1

D

1.14(0.045) X 45˚

E1 E

0.318(0.0125)

0.191(0.0075)

NOM

D2/E2

MAX

B1

A2

A1

A

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

A 4.191 – 4.572

A1 2.286 – 3.048

A2 0.508 ––

D 17.399 – 17.653

D1 16.510 – 16.662 Note 2

E 17.399 – 17.653

E1 16.510 – 16.662 Note 2

D2/E2 14.986 – 16.002

B 0.660 – 0.813

B1 0.330 – 0.533

e 1.270 TYP

MIN

NOTE

24

2325 Orchard Parkway

TITLE

R

San Jose, CA 95131

ATF1502AS(L)

44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)

DRAWING NO.

44J

0995J–PLD–09/02

10/04/01

REV.

B

Atmel Headquarters Atmel Operations

Corporate Headquarters

2325 Orchard Parkway
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© Atmel Corporation 2002.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.

AT ME L®is the registered trademark of Atmel.

Other terms and product names may be the t rademarks of others.

Printed on recycled paper.

0995J–PLD–09/02 xM