Rainbow Electronics ATF1502ASL User Manual

Features

• High-density, High-performance, Electrically-erasable Complex Programmable

Logic Device

– 32 Macrocells – 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell –44Pins – 7.5 ns Maximum Pin-to-pin Delay – Registered Operation up to 125 MHz – Enhanced Routing Resources

• In-System Programmability (ISP) via JTAG

• Flexible Logic Macrocell

– D/T Latch Configurable Flip-flops – Global and Individual Register Control Signals – Global and Individual Output Enable – Programmable Output Slew Rate – Programmable Output Open Collector Option – Maximum Logic Utilization by Burying a Register with a COM Output

• Advanced Power Management Features

• Automatic10µAStandbyfor“L”Version

• Pin-controlled 1 mA Standby Mode

• Programmable Pin-keeper Inputs and I/Os

• Reduced-power Feature per Macrocell

• Available in Commercial and Industrial Temperature Ranges

• Available in 44-lead PLCC and TQFP

• Advanced EEPROM Technology

– 100% Tested – Completely Reprogrammable – 10,000 Program/Erase Cycles – 20-year Data Retention – 2000V ESD Protection – 200 mA Latch-up Immunity

• JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

• PCI-compliant

• Security Fuse Feature

Highperformance EEPROM CPLD

ATF1502AS ATF1502ASL

Enhanced Features

• Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

• Output Enable Product Terms

• D Latch Mode

• Combinatorial Output with Registered Feedback within Any Macrocell

• Three Global Clock Pins

• ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O

(“L” versions)

• Fast Registered Input from Product Term

• Programmable “Pin-keeper” Option

• V

Power-up Reset Option

• Pull-up Option on JTAG Pins TMS and TDI

• Advanced Power Management Features

– Input Transition Detection – Power-down (“L” versions) – Individual Macrocell Power Option – Disable ITD on Global Clocks, Inputs and I/O

Rev. 0995J–PLD–09/0 2

I/O/TDI

GND

PD1/I/O

TMS/I/O

VCC

TDI/I/O

PD1/I/O

I/O/TMS

I/O I/O

I/O

I/O I/O

GND

I/O

VCC

I/O I/O

44-lead TQFP

Top Vi e w

I/O

VCC

GCLK2/OE2/I

GCLR/I

I/OE1

4443424140393837363534

1 2 3 4 5 6 7 8 9 10 11

1213141516171819202122

I/O

VCC

GND

44-lead PLCC

Top Vi e w

I/O

VCC

GCLK2/OE2/I

GCLR/I

OE1/I

65432

7 8 9 10 11 12 13 14 15 16 17

1819202122232425262728

4443424140

GCLK1/I

GND

I/O

PD2/I/O

GCLK1/I

GND

GCLK3/I/O

I/O

33 32 31 30 29 28 27 26 25 24 23

I/O

GCLK3/I/O

I/O

39 38 37 36 35 34 33 32 31 30 29

I/O I/O/TDO I/O I/O VCC I/O I/O I/O/TCK I/O GND I/O

I/O

GND

VCC

I/O

PD2/I/O

Description The ATF1502AS is a high-performance, high-density complex programmable logic device

(CPLD) that utilizes Atmel’s proven electrically-erasable technology. With 32 logic macrocells and up to 36 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1502AS’s enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications.

The ATF1502AS has up to 32 bi-directional I/O pins and four dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal, register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell.

ATF1502AS(L)

0995J–PLD–09/02

Block Diagram

ATF1502AS(L)

Each of the 32 macrocells generates a buried feedback that goes to the global bus. Each input and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus. Each macrocell also generates a foldback logic term that goes to a regional bus. Cascade logic between macrocells in the ATF1502AS allows fast, efficient generation of complex logic functions. The ATF1502AS contains four such logic chains, each capable of creating sum term logic with a fan-in of up to 40 product terms.

The ATF1502AS macrocell, shown in Figure 1, is flexible enough to support highly complex logic functions operating at high speed. The macrocell consists of five sections: product terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select and enable, and logic array inputs.

Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse, when programmed, protects the contents of the ATF1502AS. Two bytes (16 bits) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the security fuse.

The ATF1502AS device is an in-system programmable (ISP) device. It uses the industry standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundaryscan Description Language (BSDL). ISP allows the device to be programmed without removing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software.

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Figure 1. ATF1502AS Macrocell

Product Terms and Select Mux

OR/XOR/ CASCADE Logic

Each ATF1502AS macrocell has five product terms. Each product term receives as its inputs all signals from both the global bus and regional bus.

The product term select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic gates and control signals. The PTMUX programming is determined by the design compiler, which selects the optimum macrocell configuration.

The ATF1502AS’s logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5-input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with little additional delay.

The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions. One input to the XOR comes from the OR sum term. The other XOR input can be a product term or a fixed high or low level. For combinatorial outputs, the fixed level input allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of product terms. The XOR gate is also used to emulate T- and JK-type flip-flops.

Flip-flop The ATF1502AS’s flip-flop has very flexible data and control functions. The data input can

come from either the XOR gate, from a separate product term or directly from the I/O pin. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell. (This feature is automatically implemented by the fitter software). In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flowthrough latch. In this mode, data passes through when the clock is high and is latched when the clock is low.

ATF1502AS(L)

0995J–PLD–09/02

ATF1502AS(L)

The clock itself can be either one of the Global CLK signals (GCK[0 : 2]) or an individual product term. The flip-flop changes state on the clock’s rising edge. When the GCK signal is used as the clock, one of the macrocell product terms can be selected as a clock enable. When the clock enable function is active and the enable signal (product term) is low, all clock edges are ignored. The flip-flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a product term, or always off. AR can also be a logic OR of GCLEAR with a product term. The asynchronous preset (AP) can be a product term or always off.

Extra Feedback The ATF1502AS(L) macrocell output can be selected as registered or combinatorial. The

extra buried feedback signal can be either combinatorial or a registered signal regardless of whether the output is combinatorial or registered. (This enhancement function is automatically implemented by the fitter software.) Feedback of a buried combinatorial output allows the creation of a second latch within a macrocell.

I/O Control The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be indi-

vidually configured as an input, output or for bi-directional operation. The output enable for each macrocell can be selected from the true or compliment of the two output enable pins, a subset of the I/O pins, or a subset of the I/O macrocells. This selection is automatically done by the fitter software when the I/O is configured as an input, all macrocell resources are still available, including the buried feedback, expander and cascade logic.

Global Bus/Switch Matrix

The global bus contains all input and I/O pin signals as well as the buried feedback signal from all 32 macrocells. The switch matrix in each logic block receives as its inputs all signals from the global bus. Under software control, up to 40 of these signals can be selected as inputs to the logic block.

Foldback Bus Each macrocell also generates a foldback product term. This signal goes to the regional bus

and is available to four macrocells. The foldback is an inverse polarity of one of the macrocell’s product terms. The four foldback terms in each region allow generation of high fan-in sum terms (up to nine product terms) with little additional delay.

Programmable Pin-keeper Option for Inputs and I/Os

The ATF1502AS offers the option of programming all input and I/O pins so that pin-keeper circuits can be utilized. When any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level. This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise. The keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption.

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Input Diagram

I/O Diagram

Speed/Power Management

ATF1502AS(L)

The ATF1502AS has several built-in speed and power management features. The ATF1502AS contains circuitry that automatically puts the device into a low-power standby mode when no logic transitions are occurring. This not only reduces power consumption during inactive periods, but also provides proportional power savings for most applications running at system speeds below 50 MHz. This feature may be selected as a design option.

To further reduce power, each ATF1502AS macrocell has a reduced-power bit feature. This feature allows individual macrocells to be configured for maximum power savings. This feature may be selected as a design option.

The ATF1502AS also has an optional power-down mode. In this mode, current drops to below 10 mA. When the power-down option is selected, either PD1 or PD2 pins (or both) can be used to power down the part. The power-down option is selected in the design source file. When enabled, the device goes into power-down when either PD1 or PD2 is high. In the power-down mode, all internal logic signals are latched and held, as are any enabled outputs.

0995J–PLD–09/02

ATF1502AS(L)

All pin transitions are ignored until the PD pin is brought low. When the power-down feature is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s macrocell may still be used to generate buried foldback and cascade logic signals.

All power-down AC characteristic parameters are computed from external input or I/O pins, with reduced-power bit turned on. For macrocells in reduced-power mode (reduced-power bit turned on), the reduced-power adder, t include the data paths t

The ATF1502AS macrocell also has an option whereby the power can be reduced on a permacrocell basis. By enabling this power-down option, macrocells that are not used in an application can be turned down, thereby reducing the overall power consumption of the device.

Each output also has individual slew rate control. This may be used to reduce system noise by slowing down outputs that do not need to operate at maximum speed. Outputs default to slow switching, and may be specified as fast switching in the design file.

LAD,tLAC,tIC,tACL,tACH

, must be added to the AC parameters, which

RPA

and t

SEXP

Design Software

ATF1502AS designs are supported by several third-party tools. Automated fitters allow logic synthesis using a variety of high-level description languages and formats.

Support

Power-up Reset The ATF1502AS is designed with a power-up reset, a feature critical for state machine initial-

ization. At a point delayed slightly from V the state of each output will depend on the polarity of its buffer. However, due to the asynchronous nature of reset and uncertainty of how V conditions are required:

1. The V

2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and,

3. The clock must remain stable during T

The ATF1502AS has two options for the hysteresis about the reset level, V Large. During the fitting process users may configure the device with the Power-up Reset hysteresis set to Large or Small. Atmel POF2JED users may select the Large option by including the flag “-power_reset” on the command line after “filename.POF”. To allow the registers to be properly reinitialized with the Large hysteresis option selected, the following condition is added:

4. If V

When the Large hysteresis option is active, I well.

rise must be monotonic,

falls below 2.0V, it must shut off completely before the device is turned on again.

crossing V

actually rises in the system, the following

is reduced by several hundred microamps as

, all registers will be initialized, and

RST

, Small and

Security Fuse Usage

A single fuse is provided to prevent unauthorized copying of the ATF1502AS fuse patterns. Once programmed, fuse verify is inhibited. However, the 16-bit User Signature remains accessible.

Programming ATF1502AS devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG pro-

tocol. This capability eliminates package handling normally required for programming and facilitates rapid design iterations and field changes.

0995J–PLD–09/02

Atmel provides ISP hardware and software to allow programming of the ATF1502AS via the PC. ISP is performed by using either a download cable, a comparable board tester or a simple microprocessor interface.

When using the ISP hardware or software to program the ATF1502AS devices, four I/O pins must be reserved for the JTAG interface. However, the logic features that the macrocells have associated with these I/O pins are still available to the design for burned logic functions.

To facilitate ISP programming by the Automated Test Equipment (ATE) vendors, Serial Vector Format (SVF) files can be created by Atmel-provided software utilities.

ATF1502AS devices can also be programmed using standard third-party programmers. With a third-party programmer, the JTAG ISP port can be disabled, thereby allowing four additional I/Opinstobeusedforlogic.

Contact your local Atmel representatives or Atmel PLD applications for details.

ISP Programming Protection

JTAG-BST/ISP Overview

The ATF1502AS has a special feature that locks the device and prevents the inputs and I/O from driving if the programming process is interrupted for any reason. The inputs and I/O default to high-Z state during such a condition. In addition, the pin-keeper option preserves the previous state of the input and I/O PMS during programming.

All ATF1502AS devices are initially shipped in the erased state, thereby making them ready to use for ISP.

Note: For more information refer to the “Designing for In-System Programmability with Atmel CPLDs”

application note.

The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the ATF1502AS. The boundary-scan technique involves the inclusion of a shift-register stage (contained in a boundary-scan cell) adjacent to each component so that signals at component boundaries can be controlled and observed using scan testing methods. Each input pin and I/O pin has its own boundary-scan cell (BSC) to support boundary-scan testing. The ATF1502AS does not include a Test Reset (TRST) input pin because the TAP controller is automatically reset at power-up. The five JTAG modes supported include: SAMPLE/PRELOAD, EXTEST, BYPASS, IDCODE and HIGHZ. The ATF1502AS’s ISP can be fully described using JTAG’s BSDL as described in IEEE Standard 1149.1b. This allows ATF1502AS programming to be described and implemented using any one of the third-party development tools supporting this standard.

The ATF1502AS has the option of using four JTAG-standard I/O pins for boundary-scan testing (BST) and in-system programming (ISP) purposes. The ATF1502AS is programmable through the four JTAG pins using the IEEE standard JTAG programming protocol established by IEEE Standard 1149.1 using 5V TTL-level programming signals from the ISP interface for in-system programming. The JTAG feature is a programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are available as I/O pins.

ATF1502AS(L)

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