Rainbow Electronics ATF1500AL User Manual
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39
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I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
65432
1
4443424140
1819202122232425262728
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O/PD
VCC
OE2/I
GCLR/I
OE1/I
CLK/I
GND
I/O
I/O
Features
• High-density, High-performance Electrically-erasable Complex
Programmable Logic Device
– 44-pin, 32 I/O CPLD
– 7.5 ns Maximum Pin-to-pin Delay
– Registered Operation Up To 125 MHz
– Fully Connected Input and Feedback Logic Array
– Backward Compatibility with ATF1500/L Software and Hardware
• Flexible Logic Macrocell
– D/T/Latch Configurable Flip Flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
• Advanced Power Management Features
– Automatic 3 mA Stand-By (ATF1500AL)
– Pin-controlled 10 mA Standby Mode
– Programmable Pin-Keeper Inputs and I/Os
• Available in Commercial and Industrial Temperature Ranges
• Available in 44-pin PLCC and TQFP Packages
• Advanced Flash Technology
– 100% Tested
– Completely Reprogrammable
– 100 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
• Supported By Popular 3rd Party Tools
• Security Fuse Feature
• Pin-compatible with the Most Commonly Used Devices
Highperformance
EPLD
ATF1500A
ATF1500AL
Description
The ATF1500A is a hig h-performance, hi gh-density complex PLD. Built on an
advanced Flash technol ogy, it has maxi mum pin to pin delay s of 7.5 ns and supports
sequential logic operati on at spee ds u p to 1 25 MHz . With 32 logic macro cell s and u p
to 36 inputs, it easily integrates logic from several TTL, SS I, MSI and classic PLDs.
The ATF1500A’s global input and feedback architecture simplifies logic placement
and eliminates pinout changes due to design changes.
Pin Configurations
Pin
Name Function
CLK Clock
I Logic Inputs
I/O
GCLR
OE1,
OE2
VCC +5V Supply
PD
Bidirectional
Buffers
Register Reset
(active low)
Output Enable
(active low)
Power Down
(active high)
PLCC
Top View
GND
VCC
I/O
I/O
4443424140393837363534
1
I/O
2
I/O
3
I/O
4
5
I/O
6
I/O
7
I/O
8
I/O
9
10
I/O
11
I/O
1213141516171819202122
I/O
I/O
(continued)
TQFP
Top View
I/O/PD
VCC
OE2/I
GCLR/I
OE1/I
I/O
I/O
I/O
VCC
GND
CLK/I
I/O
GND
I/O
I/O
I/O
33
I/O
32
I/O
31
I/O
30
I/O
29
VCC
28
I/O
27
I/O
26
I/O
25
I/O
24
GND
23
I/O
I/O
I/O
Rev. 0759E–06/99
1
Functional Logic Diagram
(1)
Note: 1. Arrows connecting macrocells indicate direction and groupings of CASIN/CASOUT data flow.
The ATF1500A has 32 bi-directional I/O pins and 4 dedicated input pins. Eac h dedicate d input pin c an also serve
as a global control signal: register clock, register reset or
output enable. Each of these control signals can be
selected for use individually within each macrocell.
2
ATF1500A(L)
Each of the 32 logic macrocells generates a buried feedback, which goes to th e global bu s. Each inp ut and I/O pin
also feeds into the global bus. Because of this global bussing, each of these signals is always available to all 32
macrocells in the device.
ATF1500A(L)
Each macrocell also generates a foldback logic term, which
goes to a regional bu s. Al l s ign al s wi thin a reg ion al bus are
connected to all 16 macrocells within the region.
Cascade logic between macrocells in the ATF1500A allows
fast, efficient generation of complex logic functions. Th e
ATF1500A co ntains 4 s uch lo gic ch ains, each capabl e of
creating sum term logic with a fa n in of up to 40 product
terms.
Bus Friendly Pin-Keeper Input and I/O’s
All Input and I/O pins on the ATF1500A have programma-
ble “pin keeper” circuits. If activated, when any pin is driven
high or low and then subsequently left floating, it will stay at
that previous high or low level.
This circuitry prevents unus ed Input and I/O lines from
floating to intermedi ate volta ge levels , which caus e unnecessary power consumption and system noise. The keeper
circuits eliminate the need for external pull-up resistors and
eliminate their DC power consumption.
Pin-keeper cir cuits can be disab led. Progr amming i s controlled in the logic design file. Once the pin-keeper circuits
are disabled, normal termination pr ocedures are r equired
for unused inputs and I/Os.
Speed/Power Management
The ATF1500A has seve ral built-i n spe ed and power m anagement features. The ATF1500A co ntains circuitry that
automatically puts the device into a low power stand-by
mode when no logic transitions are oc cu rrin g. Thi s not only
reduces power consumptio n during inactiv e periods, but
also provides a proportional power savings for most applications running at system speeds below 10 MHz.
All ATF1500As also have an optional pin-controlled power
down mode. In this mode, current drops to below 10 mA.
When the power down option is selected, the PD pin is
used to power down the part. The power down o ption is
selected in the desi gn source file. Whe n enabled, the
device goes into power down when the PD pin is high. In
the power down mode, all inter nal logi c si gnals ar e latche d
and held, as ar e any en abl ed out put s. Al l pin t rans itio ns ar e
ignored until the PD is brought low. When the power down
feature is enabled, the PD cannot be used as a logic input
or output. However, the PD pin's macrocell may still be
used to generate buried foldback and cascade logic s ignals.
Each output also has in divi dual sl ew rate contr ol. This may
be used to reduce system noise by slowing down o utputs
that do not need to operate at maximum speed. Outputs
default to slow switching, and may be specified as fas t
switching in the design file.
Design Software Support
ATF1500A designs are supported by several 3rd party
tools. Automated fitters allow logic synthesis using a variety
of high level description languages and formats.
Input Diagram
V
CC
INPUT
ESD
PROTECTION
CIRCUIT
100K
PROGRAMMABLE
OPTION
I/O Diagram
V
CC
OE
DATA
V
CC
100K
PROGRAMMABLE
OPTION
I/O
3
ATF1500A(L) Macrocell
ATF1500A Macrocell
The ATF1500A macr ocell is flexible enou gh to support
highly complex logic functions operating at high speed. The
macrocell consists of five sections: product terms and product term select multiplexer; OR/XOR/CASCADE logic; a flip
flop; output select and enable; and logic array inputs.
Product Terms and Select Mux
Each ATF1500A macrocell has five pr oduct terms. Each
product term recei ve s a s its inp u ts al l s ig nal s f ro m bo th th e
global bus and regional bus.
The product term select multip lexer ( PTMUX ) alloc ates th e
five product terms as needed to the macrocell logic gates
and control signals. The PTMUX programming is determined by the design c ompiler, which se lects the opt imum
macrocell configuration.
OR/XOR/CASCADE Logic
The ATF1500A macrocell’s OR/XOR/CASCADE logic
structure is design ed to effi c ien tly su pport al l ty pes of log ic .
Within a single mac rocell, all the product term s can be
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ATF1500A(L)
routed to the OR g ate, cr eating a fi ve input AND/OR sum
term. With the addition of the CASIN from neighboring
macrocells, this can be expanded to as many as 40 product
terms with a very small addition al del ay.
The macrocell’s XOR gate allows efficient implementation
of compare and arithmetic fun ctions. O ne input to the XOR
comes from the OR sum term. The other XOR input can be
a product term or a fixed high or low level. For combinatorial outputs, the fixed level input allows output polarity
selection. F or re gist ere d func tio ns, th e fix ed leve ls al low De
Morgan minimization of the product terms. The XOR gate is
also used to emulate T-type flip flops.
Flip Flop
The ATF1500A’s flip flop has very fle xible dat a and contro l
functions. The data input can come from either the XOR
gate or from a separate product term. Selecting the separate product term allows creation of a buried registered
feedback within a combinatorial output macrocell.
ATF1500A(L)
In addition to D, T, JK and SR operation, the flip flop can
also be configured as a flow-through latch. In this mode,
data passes through when the clock is high and is latched
when the clock is low.
The clock itself can be e ither the global CLK pi n or an ind ividual product term. The flip flop changes state on the
clock’s rising edge. When the CLK pin is used as the clock,
one of the macrocell product terms can be selected as a
clock enable. When the cloc k enable func tion is active an d
the enable signal (produc t term) is low , all clo ck edges are
ignored.
The flip flop’s asynchronous reset signal (AR) can be either
the pin global clear (GCLR), a product term, or always off.
AR can also be a logic OR of GCLR with a product term.
The asynchronous preset (AP) can be a product term or
always off.
Output Select and Enable
The ATF1500A macro cell ou tput can be s elect ed as regi stered or combinatorial. When the outpu t is registered, the
same registered signal is fed back inte rnally to the g lobal
bus. When the output is combi nato rial , the buri ed fee dba ck
can be either the same combinatorial signal or it can be the
register output if the separate product term is chosen as
the flip flop input.
The output enable multiplexer (MOE) controls the output
enable signals . Any buffer ca n be perman ently enab led for
simple output operation. Buffers ca n also be permanently
disabled to allow use of the pin as an i nput. In this confi guration all the ma croce ll res our ces are still ava ilab le, i ncl uding the buried feedback, expander and CASCADE logic.
The output enable for each m acroce ll ca n als o be se lecte d
as either of the two OE pins or as an individual product
term.
Global/Regional Busses
The global bus contains all Input and I/O pin signals as well
as the buried feed back signal from a ll 32 macrocells.
Together with the complement of each signal, this provides
a 68 bit bus as input to every product term. Having the
entire global bus available to each macrocell eliminates
any potential routing proble ms. With this arc hitecture
designs can be modified without requiring pinout changes.
Each macrocell a lso generate s a foldbac k product ter m.
This signal goes to the regi onal bu s, and is av ailab le to 16
macrocells. The foldback is an inverse polarity of one of the
macrocell’s product terms. The 16 foldba ck terms in each
region allow generation of high fan-in sum terms (up to 21
product terms) with a small additional delay.
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Absolute Maximum Ratings*
Temperature Under Bias.................................. -40°C to +85°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V
(1)
(1)
(1)
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent da mage to the device . This is a st ress rating only and
functional operatio n of the dev ice at th ese or an y
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for exten ded periods may af fect device
reliability .
Note: 1. Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is V
+ 0.75V DC,
CC
which may overshoot to 5.25V for pulses of less
than 20 ns.
DC and AC Operating Conditions
Commercial Industrial
Operating Temperature (ambient) 0°C - 70°C-40°C - 85°C
V
Power Supply 5V ± 5% 5V ± 10%
CC
DC Characteristics
Symbol Parameter Condition Min Typ Max Units
I
IL
I
IH
Input or I/O
Low Leakage Current
Input or I/O
High Leakage Current
≤ VIL (Max) -10 µA
0 ≤ V
IN
V
, Min ≤ VIN ≤ V
IH
CC
10 µA
Com. 70 mA
ATF1500A
I
CC1
(1)
Power Supply Current,
Standby
VCC = Max,
V
= 0, V
IN
CC
Ind. 100 mA
Com. 3 mA
ATF1500AL
Ind. 5 mA
I
I
V
V
V
V
CC2
OS
IL
IH
OL
OH
Power Supply Current,
Pin-Controlled Power
Down Mode
Output Short Circuit
Current
Input Low Voltage
Input High Voltage 2.0 VCC + 1 V
Output Low Voltage VCC = Min IOL = 12 mA 0.45 V
Output High Voltage VCC = Min
V
= Max,
CC
V
= 0, V
IN
V
OUT
VCC, Min < VCC
< VCC, Max
CC
= 0.5V -130 mA
-0.5 0.8 V
I
= -4 mA 2.4 V
OH
I
= -0.2 mA VCC - 0.2 V
OH
210mA
Note: 1. All ICC parameters measured with outputs open, and a 16-bit loadable, up/down counter programmed into each region.
6
ATF1500A(L)
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