Rainbow Electronics ATA6837 User Manual

Features

• Six Half-bridge Outputs Formed by Six High-side and Six Low-side Drivers

• Capable of Switching all Kinds of Loads (Such as DC Motors, Bulbs, Resistors,

Capacitors and Inductors)

• R

• Up to 650-mA Output Current

• Very Low Quiescent Current I

• Outputs Short-circuit Protected

• Overtemperature Prewarning and Protection

• Undervoltage Protection

• Various Diagnosis Functions Such as Shorted Output, Open Load, Overtemperature

• Serial Data Interface

• Operation Voltage up to 40V

• Daisy Chaining Possible

• Serial Interface 5V and 3.3V Compatible, up to 2 MHz Clock Frequency

• QFN24 Package

Typically 1.0Ω at 25°C, Maximum 2.2Ω at 200°C

DSon

< 20 µA in Standby Mode

S

and Power Supply Fail

High
Temperature
Hex Half-bridge
Driver with
Serial Input

1. Description

The ATA6837 is designed for high-temperature applications. In mechatronic solutions,
for example, turbo charger or exhaust gas recirculation systems, many flaps have to
be controlled by DC motor driver ICs which are located very close to the hot engine or
actuator and where ambient temperatures up to 150°C are usual. Due to the advan­tages of SOI technology, junction temperatures up to 200°C are allowed. This enables
new cost-effective board design possibilities to achieve complex mechatronic
solutions.

The ATA6837 is a fully protected hex half-bridge driver, used to control up to 6 differ­ent loads by a microcontroller in automotive and industrial applications.

Each of the six high-side and six low-side drivers is capable of driving currents up to
650 mA. The drivers are internally connected to form 6 half-bridges and can be con­trolled separately from a standard serial data interface. Therefore, all kinds of loads,
such as bulbs, resistors, capacitors and inductors, can be combined. The IC espe­cially supports the application of H-bridges to drive DC motors.

Protection is guaranteed in terms of short-circuit conditions, overtemperature and
undervoltage. Various diagnosis functions and a very low quiescent current in standby
mode make a wide range of applications possible.

Automotive qualification referring to conducted interferences, EMC protection and
ESD protection gives added value and enhanced quality for the exacting requirements
of automotive applications.

Control

ATA6837

Preliminary

4953C–AUTO–09/07

Figure 1-1. Block Diagram QFN24

O

S

L

S

C

D

I

T

Input register
Ouput register

P

I

S

S

N

C

F

H

D

Fault

Detect

Fault

Detect

11

OUT1

CLK

CS

INH

DO

DI

19

18

17

Fault

Detect

12

13

Fault

Detect

H

L

H

L

H

H

L

H

L

S

S

6

6

H

S

S

S

5

5

4

L

L
S
4

S

S
3

S

S

2

2

3

S

S

S

R

1

1

R

Serial interface

H

H

L

S

S

6

6

823

OUT2

H
S
5

Fault

Detect

Fault

Detect

L

S

5

H
S
4

5

OUT3

L

L
S
4

Fault

Detect

Fault

Detect

H

L
S
2

Fault

Detect

Fault

Detect

H

S

S

2

1

S

S

3

3

2

OUT4 OUT5 OUT6

Fault

Detect

Fault

Detect

T

L

P

S
1

20

Control

logic

Thermal

protection

3, 4

VS

Charge

pump

UV

protection

14

VCC

Power on

reset

24

GND

16

GND

15

GND

7

GND

2

ATA6837 [Preliminary]

4953C–AUTO–09/07

2. Pin Configuration

Figure 2-1. Pinning QFN 24, 5 × 5, 0.65 mm pitch

OUT4 SENSE

OUT4

VS
VS

OUT3

OUT3 SENSE

NC

OUT5

OUT5 SENSE

24 23 22 21 1920

1
2
3
4
5
6

78910 1211

OUT6 SENSE

OUT6

DI

CLK

18
17

CS

16

GND SENSE
NC

15
14

VCC

13

DO

ATA6837 [Preliminary]

NC

OUT2

OUT2 SENSE

INH

OUT1

OUT1 SENSE

Note: YWW Date code (Y = Year above 2000, WW = week number)

ATAxyz Product name
ZZZZZ Wafer lot number
AL Assembly sub-lot number

Table 2-1. Pin Description QFN24

Pin Symbol Function

1 OUT4 SENSE Only for testability in final test

Half-bridge output 4; formed by internally connected power MOS high-side switch 4 and low-side switch 4

2OUT4

3 VS Power supply output stages HS4, HS5 and HS6
4 VS Power supply output stages HS1, HS2 and HS3
5 OUT3 Output 3; see pin 1
6 OUT3 SENSE Only for testability in final test
7 NC Internal bond to GND
8 OUT2 Output 2; see pin 1

9 OUT2 SENSE Only for testability in final test
10 OUT1 SENSE Only for testability in final test
11 OUT1 Output 1; see pin 1
12 INH Inhibit input; 5V/3.3V logic input with internal pull down; low = standby, high = normal operation

13 DO

14 VCC Logic supply voltage (5V/3.3V)
15 NC Internal bond to GND
16 GND SENSE Ground; reference potential; internal connection to the lead frame; cooling tab

with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and
open load

Serial data output; 5V/3.3V CMOS logic level tri-state output for output (status) register data; sends 16-bit
status information to the microcontroller (LSB is transferred first). Output will remain tri-stated unless
device is selected by CS = low, therefore, several ICs can operate on one data output line only

4953C–AUTO–09/07

3

Table 2-1. Pin Description QFN24 (Continued)

Pin Symbol Function

17 CS

18 CLK

19 DI

20 OUT6 Output 6; see pin 1
21 OUT6 SENSE Only for testability in final test
22 OUT5 SENSE Only for testability in final test
23 OUT5 Output 5; see pin 1
24 NC Internal bond to GND

Chip select input; 5V/3.3V CMOS logic level input with internal pull up;
low = serial communication is enabled, high = disabled

Serial clock input; 5V/3.3V CMOS logic level input with internal pull down;
controls serial data input interface and internal shift register (f

Serial data input; 5V/3.3V CMOS logic level input with internal pull down; receives serial data from the
control device; DI expects a 16-bit control word with LSB being transferred first

= 2 MHz)

max

4

ATA6837 [Preliminary]

4953C–AUTO–09/07

3. Functional Description

3.1 Serial Interface

Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized
to CLK and is accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be trans­ferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS
is high, pin DO is in a tri-state condition. This output is enabled on the falling edge of CS. Output
data will change their state with the rising edge of CLK and stay stable until the next rising edge
of CLK appears. LSB (bit 0, TP) is transferred first.

Figure 3-1. Data Transfer Input Data Protocol

CS

ATA6837 [Preliminary]

CLK

DO

DI

SRR LS1 HS1 LS2 HS2 LS3

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

TP SLS1 SHS1 SLS2 SHS2 SLS3 SHS3 SLS4

HS3

LS4

HS4 LS5 HS5 LS6 HS6

SHS4 SLS5 SHS5 SLS6 SHS6 SCD INH PSF

OLD

SCT SI

Table 3-1. Input Data Protocol

Bit Input Register Function

0SRR

1 LS1 Controls output LS1 (high = switch output LS1 on)
2 HS1 Controls output HS1 (high = switch output HS1 on)
3 LS2 See LS1
4 HS2 See HS1
5 LS3 See LS1
6 HS3 See HS1
7 LS4 See LS1
8 HS4 See HS1

9 LS5 See LS1
10 HS5 See HS1
11 LS6 See LS1
12 HS6 See HS1
13 OLD Open load detection (low = on)

14 SCT

15 SI

Status register reset (high = reset; the bits PSF, SCD and
overtemperature shutdown in the output data register are set to low)

Programmable time delay for short circuit
(shutdown delay high/low = 12 ms/1.5 ms)

Software inhibit; low = standby, high = normal operation
(data transfer is not affected by standby function because the digital
part is still powered)

4953C–AUTO–09/07

5

Table 3-2. Output Data Protocol

Output (Status)

Bit

0TP

1 Status LS1

2 Status HS1

3 Status LS2 Description see LS1

4 Status HS2 Description see HS1

5 Status LS3 Description see LS1

6 Status HS3 Description see HS1

7 Status LS4 Description see LS1

8 Status HS4 Description see HS1

9 Status LS5 Description see LS1
10 Status HS5 Description see HS1
11 Status LS6 Description see LS1
12 Status HS6 Description see HS1

13 SCD

14 INH

15 PSF Power supply fail: undervoltage at pin VS detected

Note: Bit 0 to 15 = high: overtemperature shutdown

Register Function

Temperature prewarning: high = warning
(overtemperature shutdown see remark below)

Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is
switched off)

Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is
switched off)

Short circuit detected: set high, when at least one output is switched off
by a short circuit condition

Inhibit: this bit is controlled by software (bit SI in input register) and
hardware inhibit (pin INH). High = standby, low = normal operation

Table 3-3. Status of the Input Register After Power on Reset

Bit 15

6

Bit 14

(SI)

(SCT)

HHHLLLLLLLLLLLLL

Bit 13
(OLD)

Bit 12
(HS6)

Bit 11

(LS6)

Bit 10

(HS5)

Bit 9

(LS5)

Bit 8

(HS4)

Bit 7

(LS4)

Bit 6

(HS3)

Bit 5

(LS3)

Bit 4

(HS2)

Bit 3

(LS2)

Bit 2

(HS1)

Bit 1

(LS1)

Bit 0

(SRR)

ATA6837 [Preliminary]

4953C–AUTO–09/07