Rainbow Electronics ATA6834 User Manual

Features

• ATA6833 Temperature Range T

• ATA6834 Extended Temperature Range T

• Direct Driving of 6 External NMOS Transistors with a Maximum Switching Frequency of

50 kHz

• Integrated Charge Pump to Provide Gate Voltages for High-side Drivers and to Supply

the Gate of the External Battery Reverse Protection NMOS

• Built-in 5V/3.3V Voltage Regulator with Current Limitation

• Reset Signal for the Microcontroller

• Sleep Mode with Supply Current of typically < 45 µA

• Wake-up via LIN Bus or High Voltage Input

• Programmable Window Watchdog

• Battery Overvoltage Protection and Battery Undervoltage Management

• Overtemperature Warning and Protection (Shutdown)

• 200 mA Peak Current for Each Output Driver

• LIN Transceiver Conformal to LIN 2.1 and SAEJ2602-2 with Outstanding EMC and ESD

Performance

• QFN48 Package 7 mm × 7 mm

= 125°C, TJ = 150°C

A

= 150°C, TJ = 200°C

A

BLDC Motor
Driver and LIN
System Basis
Chip

ATA6833

1. Description

The ATA6833 and ATA6834 are system basis chips for three-phase brushless DC
motor controllers designed in Atmel
SMART-I.S.
FETs, the system basis chip forms a BLDC motor control unit for automotive
applications. In addition, the circuits provide a 3.3V/5V linear regulator and a window
watchdog.

The circuit includes various control and protection functions like overvoltage and over­temperature protection, short circuit detection, and undervoltage management.
Thanks to these function blocks, the driver fulfils a maximum of safety requirements
and offers a high integration level to save cost and space in various applications. The
target applications are most suitable for the automotive market due to the robust tech­nology and the high qualification level. ATA6834, in particular, is designed for
applications in a high-temperature environment.

™

1. In combination with a microcontroller and six discrete power MOS-

®

’s state-of-the-art 0.8 µm SOI technology

ATA6834

Preliminary

9122B–AUTO–10/08

Figure 1-1. Block Diagram

Supervisor:

Short Circuit

Overtemperature

Undervoltage

CP

VBATSW VINTVBAT

VBAT

PBAT

VG

LIN EN1

CPLO2CPLO1

CPOUTCPHI2CPHI1

CC

Timer

WD

Timer

VBG

LIN

Hall A
Hall B
Hall C

ATA6833/34

Logic Control

Oscillator

VINT 5V

Regulator

13V

Regulator

Microcontroller

High-side

Driver 1

High-side

Driver 2

High-side

Driver 3

3.3/5V VCC
Regulator

Low-side

Driver 3

Low-side

Driver 2

Low-side

Driver 1

L2

L1

L3

VMODE

H2

H3

DG3

/RESET

DG2

DG1

WD

IH1-3

IL1-3

TX

RX

VCC

H1

S2

S3

S1

RWD WDDGNDEN2 PGND

M

Hall A

Hall C

Hall B

CC

2

ATA6833/ATA6834 [Preliminary]

9122B–AUTO–10/08

2. Pin Configuration

Figure 2-1. Pinning QFN48

VMODE

VINT

RWD

CC

/RESET

WD

WDD

EN1

NC
NC

GND

NC

ATA6833/ATA6834 [Preliminary]

VG

L1

L2

L3

VBAT

EN2

VBATSW

48 47 46 45 44 43 42 41 40 39 38 37

1
2

3

4
5
6

ATA6833/ATA6834

7

8

9
10
11
12

13 14 15 16 17 18 19 20 21 22 23 24

NC

LIN

TXD

PGND

NC

VCC

Atmel YWW

ZZZZZ-AL

IL2

IL3

IH3

IH2

IL1

IH1

RXD

NC

PBAT

36
35
34
33
32
31
30

29
28
27
26
25

DG1

CPLO1
CPHI1
CPLO2
CPHI2
CPOUT
S1
H1
S2
H2

S3

H3
DG3

DG2

Note: YWW Date code (Y = Year - above 2000, WW = week number)

ATA683x Product name
ZZZZZ Wafer lot number
AL Assembly sub-lot number

Table 2-1. Pin Description

Pin Symbol I/O Function

1 VMODE I Selector for V
2 VINT I/O Blocking capacitor
3 RWD I Resistor defining the watchdog interval
4 CC I/O RC combination to adjust cross conduction time
5 /RESET O Reset signal for microcontroller
6 WD I Watchdog trigger signal
7 WDD I Enable and disable the watchdog
8 EN1 I Microcontroller output to switch system in Sleep Mode

9 N.C. Connect to GND
10 N.C. Connect to GND
11 GND I Ground
12 NC Connect to GND
13 LIN I/O LIN-bus terminal
14 NC Connect to GND
15 TXD I Transmit signal to LIN bus from microcontroller
16 IL3 I Control Input for output L3
17 IH3 I Control Input for output H3

and interface logic voltage level

CC

9122B–AUTO–10/08

3

Table 2-1. Pin Description

Pin Symbol I/O Function

18 IL2 I Control Input for output L2
19 IH2 I Control Input for output H2
20 IL1 I Control Input for output L1
21 IH1 I Control Input for output H1
22 RXD O Receive signal from LIN bus for microcontroller
23 DG1 O Diagnostic output 1
24 DG2 O Diagnostic output 2
25 DG3 O Diagnostic output 3
26 H3 O Gate voltage high-side 3
27 S3 I/O Voltage at half bridge 3
28 H2 O Gate voltage high-side 2
29 S2 I/O Voltage at half bridge 2
30 H1 O Gate voltage high-side 1
31 S1 I/O Voltage at half bridge 1
32 CPOUT I/O Charge pump output capacitor
33 CPHI2 I Charge pump capacitor 2
34 CPLO2 O Charge pump capacitor 2
35 CPHI1 I Charge pump capacitor 1
36 CPLO1 O Charge pump capacitor 1
37 NC Connect to GND
38 PBAT I Power supply (after reverse protection) for charge pump and gate drivers
39 VG I/O Blocking capacitor
40 L1 O Gate voltage H-bridge, low-side 1
41 L2 O Gate voltage H-bridge, low-side 2
42 L3 O Gate voltage H-bridge, low-side 3
43 PGND I Power ground for H-bridge and charge pump
44 VCC O 5V/100 mA supply for microcontroller
45 NC Connect to GND
46 VBAT I Supply voltage for IC core (after reverse protection)
47 EN2 I High voltage enable input
48 VBATSW O 100Ω PMOS switch from V

BAT

4

ATA6833/ATA6834 [Preliminary]

9122B–AUTO–10/08

ATA6833/ATA6834 [Preliminary]

3. Functional Description

3.1 Power Supply Unit with Supervisor Functions

3.1.1 Power Supply

The IC has to be supplied by a reverse-protected battery voltage. To prevent damage to the IC,
proper external protection circuitry has to be added. It is recommended to use at least one
capacitor combination of storage and RF capacitors behind the reverse protection circuitry,
which is connected close to the VBAT and GND pins of the IC.

A fully integrated low-power and low-drop regulator (VINT regulator), stabilized by an external
blocking capacitor, provides the necessary low-voltage supply needed for the wake-up process.
A trimmed low-power band gap is used as reference for the VINT regulator as well as for the
VCC regulator. All internal blocks are supplied by VINT regulator. VINT regulator must not be
used for any external supply purposes.

Nothing inside the IC except the logic interface to the external microcontroller is supplied by the
5V/3.3V VCC regulator.

Both voltage regulators are checked by a “power-good comparator”, which keeps the whole chip
in reset as long as the internal supply voltage (VINT regulator output) is too low and generates a
reset for the external microcontroller if the output voltage of the VCC regulator is not sufficient.

3.1.2 VBatt Switch

This high-voltage switch provides the battery voltage at pin VBATSW for various purposes. It is
switched ON after power on reset when the IC transits to Active Mode and it will only turn OFF
when the IC changes to Sleep Mode. Watchdog resets do not have an effect on the switch. The
switch can be used for measuring purposes as well as to switch on external voltage regulators.

3.1.3 Voltage Supervisor

This function is implemented to protect the IC and the external power MOS transistors from
damage due to overvoltage on PBAT input. In the event of overvoltage (V
(V

), the external NMOS motor driver transistors will be switched off. The failure state will be

THUV

flagged on DG2 pin. It is recommended to block PBAT with an external RF capacitor to suppress
high frequency disturbances.

3.1.4 Temperature Supervisor

An integrated temperature sensor prevents the IC from overheating. If the temperature is above
the overtemperature pre-warning threshold T
HIGH to signal this event to the external microcontroller. The microcontroller should take actions
to reduce the power dissipation in the IC. If the temperature rises above the overtemperature
shutdown threshold T
transceiver will be switched OFF immediately and the /RESET signal will go LOW. Both thresh­olds have a built-in hysteresis to avoid oscillations. The IC will return to normal operation (Active
Mode) when it has cooled down below the shutdown threshold. When the junction temperature
drops below the pre-warning threshold, bit DG3 will be switched LOW.

J switch off

) or undervoltage

THOV

, the diagnostic pin DG3 will be switched to

JPW set

, the VCC regulator and all output drivers together with the LIN

9122B–AUTO–10/08

5

3.2 Active Mode and Sleep Mode

Sleep Mode

LIN

VCC

EN1

Active ModeActive Mode

T

bus

= 90 µs Regulator Wake-up Time = 4 × T

OSC

T

gotosleep

= 10 µs

T

debounce

The IC has two modes: Sleep Mode and Active Mode. Switching between the modes is
described below. By default the IC starts in Active Mode (which means normal operation) after
power-on. A Go to Sleep procedure switches the IC from Active Mode to Sleep Mode (standby).
A Go to Active procedure brings the IC back from Sleep Mode to Active Mode. When in Sleep
Mode the internal 5V supply (VINT regulator), the EN2 pin input structure, and a certain part of
the LIN receiver remain active to ensure a proper startup of the system. The VCC regulator is
turned off.

The Go to Sleep and Go to Active procedures are implemented as follows:

Go to Sleep:

Pin EN1 is a low-voltage input supplied by the VCC regulator. It is ESD protected by diodes
against VCC and GND. Thus the input voltage at pin EN1 must not go below GND or exceed the
output voltage of the VCC regulator. A transition from HIGH to LOW followed by a permanent
LOW signal for a minimum time period t
Sleep Mode as the EN1 is edge triggered. V
to keep EN1 LOW during normal operation.

Go to Active Using Pin EN2:

Pin EN2 is a high-voltage input for external wake-up signals. Its input structure consists of a
comparator with a built-in hysteresis. It is ESD-protected by diodes against GND and V
and for this reason the applied input voltage must not go below GND or exceed V
EN2 up to V

Go to Active Using the LIN Interface:

switches the IC to Active Mode. EN2 is debounced and edge triggered.

BAT

gotosleep

(typical 10 µs) at pin EN1 switches the IC to

is switched off in Sleep Mode. It is recommended

CC

BAT

, B,

BAT

. Pulling

Using the LIN interface provides a second possibility to wake-up the IC (see Figure 3-1). A fall­ing edge at pin LIN followed by a dominant bus level maintained for a minimum time period
(T

) and ending with a rising edge leads to a remote wake-up request. The device switches

bus

from Sleep Mode to Active Mode. The VCC regulator is activated and the internal LIN slave ter­mination resistor is switched on.

Figure 3-1. Wake-up Using the LIN Interface

6

ATA6833/ATA6834 [Preliminary]

9122B–AUTO–10/08

ATA6833/ATA6834 [Preliminary]

0

5

10

15

20

25

30

35

40

0255075100125150

Load Current (mA)

ESR (Ω)

ESR versus Load Current at Pin VCC

ESR

min

(C

VCC

= 2.2 µF)

ESR

max

(C

VCC

= 2.2 µF)

0

5

10

15

20

25

0255075100125150

ESR (Ω)

Load Current (mA)

ESR versus Load Current at Pin VCC

ESR

max

(C

VCC

= 10 µF)

ESR

min

(C

VCC

= 10 µF)

3.3 5V/3.3V VCC Regulator

The 5V/3.3V regulator is fully integrated. It requires an external electrolytic capacitor in the range
of 2.2 µF up to 10 µF and with an ESR in the range from 2Ω to 15Ω for stability (see Figure 3-2).
The output voltage can be configured as either 5V or 3.3V by connecting pin VMODE to either
pin VINT or GND. Since the regulator is not designed to be switched between both output volt­ages during operation, it is advisable to hard-wire VMODE pin. The logic levels of the
microcontroller interface are adapted to the VCC regulator output voltage. The maximum output
current (I
80 mA. The VCC regulator has a built-in short circuit protection. A comparator checks the output
voltage of the VCC regulator and keeps the external microcontroller in reset as long as the volt­age is below the lower operation minimum (shown in Figure 3-33).

Figure 3-2. ESR versus Load Current for External Capacitors with Different Values

) of the regulator is 100 mA. For TJ> 150°C the I

OS1

of ATA6834 is reduced to

OS1

Figure 3-3. /RESET as Function of the VCC Output Voltage

100% VCC

9122B–AUTO–10/08

VCC

88% VCC

80% VCC

/RESET

0V

7

3.4 Reset and Watchdog Management

Watchdog

trigger edge

Reset and lead
time, no trigger

Watchdog cycle,

no trigger

Watchdog cycle, trigger

during t

2

window

Reset and lead time,

trigger during lead time

t

resshort

t

1

t

2

t

1

t

d

t

res

t

d

t

1

t

res

t

2

Watchdog trigger

in t

2

window

88% VCC

VCC

WD

/RESET

The watchdog timing is based on the trimmed internal watchdog oscillator. Its period time T
is determined by the external resistor RWD. A HIGH signal on WDD pin enables the watchdog
function; a LOW signal disables it. Since WDD pin is equipped with an internal pull-up resistor
the watchdog is enabled by default. In order to keep the current consumption as low as possible
the watchdog is switched off during Sleep Mode.

The timing diagram in Figure 3-4 shows the watchdog and external reset timing.

Figure 3-4. Timing Diagram of the Watchdog in Conjunction with the /RESET Signal

OSC

8

After power-up of the VCC regulator (VCC output exceeds 88% of its nominal value) /RESET
output stays LOW for the timeout period t

res

switches to HIGH. During the following time t
expected otherwise another external reset will be triggered.

When the watchdog has been correctly triggered for the first time, normal watch-dog operation
begins. A normal watchdog cycle consists of two time sections t
for the time t
edges on WD pin during t

at /RESET if no valid trigger has been applied at pin WD during t2. Rising

resshort

also cause a short pulse on /RESET. Start for such a cycle is always

1

the time of the last rising edge either on WD pin or on /RESET pin.

If the watchdog is disabled (WDD = LOW), only the initial reset for the time t
will be generated.

Additional resets will be generated if the VCC output voltage drops below 80% of its nominal
value.

The following example demonstrates how to calculate the timing scheme for valid watchdog trig­ger pulses, which the external microcontroller has to provide in order to prevent undesired
resets.

ATA6833/ATA6834 [Preliminary]

(typical 10 ms). Subsequently /RESET output

(typical 500 ms) a rising edge at the input WD is

d

and t2 followed by a short pulse

1

after power-up

res

9122B–AUTO–10/08