Rainbow Electronics ATA6832 User Manual

Features

• Supply Voltage up to 40V

• R

• Up to 1.0A Output Current

• Three Half-bridge Outputs Formed by Three High-side and Three Low-side Drivers

• Capable of Switching Loads such as DC Motors, Bulbs, Resistors, Capacitors, and

• PWM Capability up to 25 kHz for Each Output Controlled by External PWM Signal

• No Shoot-through Current

• Outputs Short-circuit Protected

• Selective Overtemperature Protection for Each Switch and Overtemperature

• Undervoltage Protection

• Various Diagnostic Functions such as Shorted Output, Open Load, Overtemperature

• Serial Data Interface, Daisy Chain Capable, up to 2 MHz Clock Frequency

• QFN18 Package

Typically 0.8Ω at 25°C, Maximum 1.8Ω at 200°C

DSon

Inductors

Prewarning

and Power-supply Fail Detection

High Temperature Triple Half-bridge Driver with SPI

1. Description

The ATA6832 is a fully protected driver IC specially designed for high temperature applications. In mechatronic solutions, for example turbo charger or exhaust gas recirculation systems, many flaps have to be controlled by DC motor driver ICs which are located very close to the hot engine or actuator where ambient temperatures up to 150°C are usual. Due to the advantages of SOI technology junction temperatures up to 200°C are allowed. This enables new cost effective board design possibilities to achieve complex mechatronic solutions.

The ATA6832 is a triple half-bridge driver to control up to 3 different loads by a microcontroller in automotive and industrial applications. Each of the 3 high-side and 3 low-side drivers is capable of driving currents up to 1.0A. Due to the enhanced PWM signal (up to 25 kHz) it is possible to generate a smooth control of, for example, a DC motor without any noise. The drivers are internally connected to form 3 half-bridges and can be controlled separately from a standard serial data interface, enabling all kinds of loads, such as bulbs, resistors, capacitors and inductors, to be combined. The IC design especially supports the application of H-bridges to drive DC motors.

Protection is guaranteed with respect to short-circuit conditions, overtemperature and undervoltage. Various diagnostic functions and a very low quiescent current in standby mode enable a wide range of applications. Automotive qualification (protection against conducted interferences, EMC protection and 2-kV ESD protection) gives added value and enhanced quality for exacting requirements of automotive applications.

and PWM

ATA6832

4951A–AUTO–08/06

Figure 1-1. Block Diagram

S

I

Input register Ouput register

DI

4

CLK

5

CS

3

DO

7

PWM

6

P S F

detector

Faul t

H

L

H

L

H

O

L

S

D

C

I

O

N

V

H

L

P H 3

n.u.n.

2

P L 3

u.

OUT3

P H 2

n.u.n.

Faul t

detector

Faul t

detector

P

L

H

2

1

n. u.

u.

12

L

P L 1

n. u.

S

3

Serial interface

H

L

S

3

Faul t

detector

Faul t

detector

OUT2

S

2

H

L

S

2

S

R

1

R

Charge

pump

H

L S 1

OUT1

T P

Control

logic

Thermal

protection

UV

protection

Power on

reset

S 1

15

10

VS1

11

VS2

9

VCC

8

GND

14

GND

17

GND

18

GND

2

ATA6832

4951A–AUTO–08/06

2. Pin Configuration

Figure 2-1. Pinning QFN24

PGND3

PGND1

OUT1S

OUT1

PGND2

OUT2S

CS

DI

18 17 16 15 1314

1 2 3 4 5 6

12 11 10

9 8 7

OUT3S OUT3F

CLK

PWM

Table 2-1. Pin Description

Pin Symbol Function

1 OUT3S Sense pin, used only for final testing

Half-bridge output 3; formed by internally connecting power MOS high-side switch 3 and low-side switch 3

2 OUT3F

3CS

4DI

5CLK

6 PWM PWM input; 5V CMOS logic level input with internal pull-down

7DO

8 GND Ground

9 VCC Logic supply voltage (5V) 10 VS1 Power supply for output stages OUT1 and OUT2; internal supply 11 VS2 Power supply for output stages OUT2 and OUT3; internal supply

12 OUT2F

13 OUT2S Sense pin, used only for final testing 14 PGND2 Power ground OUT2

15 OUT1

16 OUT1S Sense pin, used only for final testing 17 PGND1 Power ground OUT1 18 PGND3 Power ground OUT3

with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and open load

Chip select input; 5V CMOS logic level input with internal pull-up; low = serial communication is enabled, high = disabled

Serial data input; 5V CMOS logic level input with internal pull-down; receives serial data from the control device; DI expects a 16-bit control word with LSB transferred first

Serial clock input; 5V CMOS logic level input with internal pull-down; controls serial data input interface and internal shift register (f

Serial data output; 5V CMOS logic-level tri-state output for output (status) register data; sends 16-bit status information to the microcontroller (LSB transferred first); output will remain tri-stated unless device is selected by CS = low; this allows several ICs to operate on only one data-output line

Half-bridge output 2; formed by internally connected power MOS high-side switch 2 and low-side switch 2 with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and open load

Half-bridge output 1; formed by internally connected power MOS high-side switch 1 and low-side switch 1 with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and open load

OUT2F VS2 VS1 VCC GND DO

= 2 MHz)

max

ATA6832

4951A–AUTO–08/06

3

3. Functional Description

3.1 Serial Interface

Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and is accepted on the falling edge of the CLK signal. The LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is transferred first.

Figure 3-1. Data Transfer

CS

CLK

DO

DI

SRR LS1 HS1 LS2 HS2 LS3

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

TP S1L S1H S2L S2H S3L S3H n. u.

HS3

nPL!

PH1 PL2 PH2 PL3 PH3

n. u. n. u. n. u. n. u. n. u. OVl INH PSF

OLD

OCS SI

Table 3-1. Input Data Protocol

Bit Input Register Function

0SRR

1 LS1 Controls output LS1 (high = switch output LS1 on) 2 HS1 Controls output HS1 (high = switch output HS1 on) 3 LS2 See LS1 4 HS2 See HS1 5 LS3 See LS1 6 HS3 See HS1 7 PL1 Output LS1 additionally controlled by PWM Input 8 PH1 Output HS1 additionally controlled by PWM Input

9 PL2 See PL1 10 PH2 See PH1 11 PL3 See PL1 12 PH3 See PH1 13 OLD Open load detection (low = on) 14 OCS Overcurrent shutdown (high = overcurrent shutdown is active)

15 SI

Status register reset (high = reset; the bits PSF and OVL in the output data register are set to low)

Software inhibit; low = standby, high = normal operation (data transfer is not affected by the standby function because the digital part is still powered)

4

ATA6832

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Table 3-2. Output Data Protocol

Output (Status)

Bit

0 TP Temperature prewarning: high = warning

1 Status LS1

2 Status HS1

3 Status LS2 Description see LS1

4 Status HS2 Description see HS1

5 Status LS3 Description see LS1

6 Status HS3 Description see HS1

7 n. u. Not used

8 n. u. Not used

9 n. u. Not used 10 n. u. Not used 11 n. u. Not used 12 n. u. Not used

13 OVL

14 INH

15 PSF Power-supply fail: undervoltage at pin VS detected

Register Function

Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off); not affected by SRR

Over-load detected: set high, when at least one output is switched off by a short-circuit condition or an overtemperature event. Bits 1 to 6 can be used to detect the affected switch

Inhibit: this bit is controlled by software (bit SI in input register) High = standby, low = normal operation

ATA6832

4951A–AUTO–08/06

5

After power-on reset, the input register has the following status:

Bit 15SIBit 14

OCS

HHHLLLLLLLLLLLLL

Bit 13

OLD

Bit 12

PH3

Bit 11

PL3

Bit 10

PH2

Bit 9

PL2

Bit 8 PH1

Bit 7

PL1

Bit 6

HS3

Bit 5

LS3

Bit 4

HS2

Bit 3

LS2

Bit 2

HS1

Bit 1

LS1

Bit 0 SRR

The following patterns are used to enable internal test modes of the IC. Do not use these patterns during normal operation.

Bit 15 Bit 14 Bit 13

(OCS)

HHHHHLLLLLLLLLLL HHHLLHHLLLLLLLLL HHHLLLLHHLLLLLLL

Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6

(HS3)

Bit 5

(LS3)

Bit 4

(HS2)

Bit 3

(LS2)

Bit 2

(HS1)

Bit 1

(LS1)

Bit 0

(SRR)

3.2 Power-supply Fail

If undervoltage is detected at pin VS, the power-supply fail bit (PSF) in the output register is set and all outputs are disabled. To detect an undervoltage, its duration has to last longer than the undervoltage detection delay time t voltage returns to the normal operational value. The PSF bit stays high until it is reset by the SRR bit in the input register.

. The outputs are enabled immediately when the supply

dUV

3.3 Open-load Detection

If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and a pull-down current for each low-side switch is turned on (open-load detection current I the current through the external load does not reach the open-load detection current, the corresponding bit of the output in the output register is set to high.

Switching on an output stage with the OLD bit set to low disables the open-load function for this output.

OUT1-3

). If

6

ATA6832

4951A–AUTO–08/06

3.4 Overtemperature Protection

If the junction temperature of one or more output stages exceeds the thermal prewarning threshold, T temperature falls below the thermal prewarning threshold, T bit can be read without transferring a complete 16-bit data word. The status of TP is available at pin DO with the falling edge of CS. After the microcontroller has read this information, CS is set high and the data transfer is interrupted without affecting the status of input and output registers.

, the temperature prewarning bit (TP) in the output register is set. When the

jPW set

jPW reset

ATA6832

, the bit TP is reset. The TP

If the junction temperature of an output stage exceeds the thermal shutdown threshold, T the affected output is disabled and the corresponding bit in the output register is set to low. Additionally, the overload detection bit (OVL) in the output register is set. The output can be enabled again when the temperature falls below the thermal shutdown threshold, T bit in the input register is set to high. The hysteresis of thermal prewarning and shutdown threshold avoids oscillations.

3.5 Short-circuit Protection

The output currents are limited by a current regulator. Overcurrent detection is activated by writing a high to the overcurrent shutdown bit (OCS) bit in the input register. When the current in an output stage exceeds the overcurrent limitation and shut-down threshold, it is switched off, following a delay time (t bit in the output register is set to low. For OCS = low, the overcurrent shutdown is inactive and the OVL bit is not set by an overcurrent. By writing a high to the SRR bit in the input register the OVL bit is reset and the disabled outputs are enabled.

3.6 Inhibit

The SI bit in the input register has to be set to zero to inhibit the ATA6832.

In this state, all output stages are then turned off but the serial interface remains active. The output stages can be reactivated by setting bit SI to “1”.

3.7 PWM Mode

The common input for all six outputs is pin PWM (Figure 3-2). The selection of the outputs, which are controlled by PWM, is done by input data register PLx or PHx. In addition to the PWM input register, the corresponding input registers HSx and LSs have to be set.

jswitch off

jswitch on

). The over-load detection bit (OVL) is set and the corresponding status

dSd

, and the SRR

,

4951A–AUTO–08/06

Switching the high side outputs is possible up to 25 kHz, low side switches up to 8 kHz.

Figure 3-2. Output Control by PWM

Bit LSx/HSx

Bit PLx/PHx

Pin PWM

Pin OUTx

7

4. Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Parameters Pin Symbol Value Unit

Supply voltage 10, 11 V Supply voltage

t < 0.5s; I

> –2A

S

Logic supply voltage 9

Logic input voltage 3, 4, 5, 6

Logic output voltage 7

Input current 3, 4, 5, 6

10, 11

V

VCS, VDI, V

V

ICS, IDI, I

I

PWM

Output current 7 I

Output current 2, 12, 15 I

Output voltage 2, 12, 15 I Reverse conducting current

= 150 µs)

(t

pulse

2, 12, 15

Out1

I

Out1

, I

Out2

, I

Out2

, I

Out2

Junction temperature range T Storage temperature range

T

Ambient temperature range

VS

VCC

PWM

DO

j

STG

T

a

CLK

CLK,

, I

Out3

,

Internally limited, see output

–0.3 to +40 V

–1 V

–0.3 to +7 V

–0.3 to V

+ 0.3 V

VCC

+ 0.3 V

VCC

–10 to +10 mA

specification

–0.3 to +40 V

17 A

–40 to +150 °C –55 to +150 °C –40 to +150 °C

5. Thermal Resistance

Parameters Test Conditions Symbol Value Unit

Thermal resistance from junction to case

Thermal resistance from junction to ambient

Depends on the PC board R

R

thJC

thJA

15 k/W

40 K/W

6. Operating Range

Parameters Symbol Value Unit

(1)

V

Supply voltage V Logic supply voltage V Logic input voltage VCS, VDI, V Serial interface clock frequency f PWM input frequency f

PWM

Junction temperature range T Note: 1. Threshold for undervoltage description

VS

VCC

CLK, VPWM

CLK

j

to 40 V

UV

4.75 to 5.25 V

–0.3 to V

VCC

2 MHz

max. 25 kHz

–40 to +150 °C

V

8

ATA6832

4951A–AUTO–08/06

ATA6832

7. Noise and Surge Immunity

Parameters Test Conditions Value

Conducted interferences ISO 7637-1 Level 4 Interference suppression VDE 0879 Part 2 Level 5 ESD (Human Body Model) ESD S 5.1 2 kV CDM (Charge Device Model) ESD STM5.3.1 500V Note: 1. Test pulse 5: V

smax

= 40V

8. Electrical Characteristics

7.5V < VS < 40V; 4.75V < VCC < 5.25V; INH = High; –40°C ≤Tj≤ 200°C; Ta ≤ 150°C; unless otherwise specified, all values refer to GND pins.

No. Parameters Test Conditions

1 Current Consumption

1.1 Quiescent current VS V

1.2 Quiescent current VCC

< 20V, SI = low 10, 11 I

VS

4.75V < V SI = low

< 5.25V,

VCC

9I

VVS < 20V normal

1.3 Supply current VS

operating, all outputs off, input register bit 13

10, 11 I

(OLD) = high

1.4 Supply current VCC

1.5 Discharge current VS V

1.6 Discharge current VS V

4.75V < V normal operating

= 32.5V, INH = low 10, 11 I

VS

= 40V, INH = low 10, 11 I

VS

< 5.25V,

VCC

9I

2 Undervoltage Detection, Power-on Reset

Power-on reset

2.1 threshold

Power-on reset delay

2.2 time

Undervoltage-detection

2.3 threshold

Undervoltage-detection

2.4 hysteresis

Undervoltage-detection

2.5 delay time

After switching on V

=5V 10, 11 V

V

CC

= 5V 10, 11 ∆V

V

CC

9V

3 Thermal Prewarning and Shutdown

3.1 Thermal prewarning set T Thermal prewarning

3.2 reset

Thermal prewarning

3.3 hysteresis

3.4 Thermal shutdown off T

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of

final level. Device not in standby for t > 1 ms.

2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level.

3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode.

Symbol Min. Typ. Max. Unit Type*

VS

VCC

VS

VCC

VS

VCC

t

dPor

Uv

t

dUV

jPW set

T

jPW reset

∆T

jPW

j switch off

0.5 5.5 mA A

2.0 10 mA A

3.1 3.9 4.5 V A

30 95 190 µs A

5.5 7.1 V A

Uv

10 40 µs A

170 195 220 °C B

155 180 205 °C B

200 225 250 °C B

160 µAA

60 160 µA A

46mAA

350 650 µA A

0.6 V A

15 K B

(1)

4951A–AUTO–08/06

9

8. Electrical Characteristics (Continued)

7.5V < VS < 40V; 4.75V < VCC < 5.25V; INH = High; –40°C ≤Tj≤ 200°C; Ta ≤ 150°C; unless otherwise specified, all values refer to GND pins.

No. Parameters Test Conditions

3.5 Thermal shutdown on T Thermal shutdown

3.6 hysteresis

Ratio thermal shutdown

3.7

off/thermal prewarning set

Ratio thermal shutdown

3.8

on/thermal prewarning reset

4 Output Specification (OUT1 to OUT3)

4.1 On resistance

4.2 I

High-side output

4.3 leakage current

Low-side output

4.4 leakage current

High-side switch

4.5

reverse diode forward voltage

Low-side switch reverse

4.6 diode forward voltage

High-side overcurrent

4.7

limitation and shutdown threshold

Low-side overcurrent

4.8

limitation and shutdown threshold

High-side overcurrent

4.9

limitation and shutdown threshold

Low-side overcurrent

4.10

limitation and shutdown threshold

Overcurrent shutdown

4.11 delay time

High-side open load

4.12 detection current

Low-side open load

4.13 detection current

= –0.9 A

I

Out 1-3

= –0.9 A

Out 1-3

V

Out 1-3 H

= 0V

,

output stages off

Out 1-3 L

= V

VS,

V output stages off

I

= 1.5A

Out

Out 1-3 L

= –1.5A

I

7.5V < VVS < 20V

7.5V < V

20V < V

VS

< 40V

VS

< 40V

VS

< 20V

Input register bit 13 (OLD) = low, output off

2, 12,

15

2, 12,

15

2, 12,

15

2, 12,

15

2, 12,

15

2, 12,

15

2, 12,

15

2, 12,

15

2, 12,

15

2, 12,

15

2, 12,

15

2, 12,

15 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of

final level. Device not in standby for t > 1 ms.

2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level.

3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode.

Symbol Min. Typ. Max. Unit Type*

j switch on

∆T

T

j switch off/

T

j switch on/

T

jPW reset

R

DSon1-3H

R

DSon1-3L

I

V

Out1-3

V

I

j switch off

jPW set

Out1-3H

Out1-3L

– V

Out1-3L

Out1-3

t

dSd

Out1-3H

Out1-3L

185 210 235 °C B

15 K B

1.05 1.2 B

1.5 Ω A

–60 µA A

300 µA A

VS

2VA

1.0 1.3 1.7 A A

–1.7 –1.3 –1.0 A A

1.0 1.3 2.0 A A

–2.0 –1.3 –1.0 A A

10 40 µs A

–2.5 –0.2 mA A

0.2 2.5 mA A

10

ATA6832

4951A–AUTO–08/06

ATA6832

8. Electrical Characteristics (Continued)

7.5V < VS < 40V; 4.75V < VCC < 5.25V; INH = High; –40°C ≤Tj≤ 200°C; Ta ≤ 150°C; unless otherwise specified, all values refer to GND pins.

No. Parameters Test Conditions

Open load detection

4.14 current ratio

High-side output switch

4.15 on delay

Low-side output switch

4.16 on delay

High-side output switch

4.17 off delay

Low-side output switch

4.18 off delay

(1),(2)

VVS = 13V R

=30Ω

Load

VVS = 13V

=30Ω

R

Load

VVS =13V R

= 30Ω

Load

VVS =13V R

= 30Ω

Load

Dead time between corresponding

4.19 high-side and low-side

V R

VS Load

=13V

= 30Ω

switches

4.20

4.21

∆t

dPWM

low-side switch ∆t

dPWM

high-side switch

(3)

VVS = 13V

= 30Ω

R

Load

VVS = 13V

= 30Ω

R

Load

5 Logic Inputs DI, CLK, CS, PWM

Input voltage low-level

5.1 threshold

Input voltage high-level

5.2 threshold

Hysteresis of input

5.3 voltage

Pull-down current

5.4 pins DI, CLK, PWM

Pull-up current

5.5 pin CS

, V

V

DI

CLK, VPWM

V

= 0V 3 I

CS

= V

CC

3, 4, 5,

6

3, 4, 5,

6

3, 4, 5,

6

4, 5, 6 I

6 Serial Interface – Logic Output DO

6.1 Output-voltage low level I Output-voltage high

6.2 level

Leakage current

6.3 (tri-state)

= 2 mA 7 V

DOL

= –2 mA 7 V

I

DOL

= V

V

CS

0V < V

DO

CC

< V

VCC

7IDO –15 +15 µA A

7 Inhibit Input – Timing

Delay time from

7.1

standby to normal operation

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of

final level. Device not in standby for t > 1 ms.

2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level.

3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode.

Symbol Min. Typ. Max. Unit Type*

IOL

t

don

∆t

t

don

∆t

t

don

outLX

outHX

t

don

t

don

t

doff

t

doff

– t

dPWM

– t

dPWM

– t

V

IL

V

IH

∆V

PD

PU

DOL

DOH

t

dINH

/

1.2 3

20 µs A

3 µsA

doff

=

doff

=

doff

I

1 µsA

20 µs A

37 µsA

0.3 ×

V

VCC

0.7 ×

V

VCC

VA

50 700 mV A

570 µAA

–70 –5 µA A

0.4 V A

V

–

VCC

0.7V

VA

100 µs A

4951A–AUTO–08/06

11

9. Serial Interface Timing

No. Parameters Test Conditions Pin Timing Chart No.

8 Serial Interface Timing

DO enable after CS

8.1 falling edge

DO disable after CS

8.2 rising edge

= 100 pF 7 1 t

C

DO

= 100 pF 7 2 t

C

DO

8.3 DO fall time CDO = 100 pF 7 - t

8.4 DO rise time C

8.5 DO valid time C

= 100 pF 7 - t

DO

= 100 pF 7 10 t

DO

8.6 CS setup time 3 4 t

8.7 CS setup time 3 8 t

8.8 CS high time 3 9 t

8.9 CLK high time 5 5 t

8.10 CLK low time 5 6 t

8.11 CLK period time 5 - t

8.12 CLK setup time 5 7 t

8.13 CLK setup time 5 3 t

8.14 DI setup time 4 11 t

8.15 DI hold time 4 12 t

*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

(1)

Symbol Min. Typ. Max. Unit Type*

ENDO

DISDO

DOf

DOr

DOVal

CSSethl

CSSetlh

CSh

CLKh

CLKl

CLKp

CLKSethl

CLKSetlh

DIset

DIHold

225 ns D 225 ns D 500 ns D 225 ns D 225 ns D 500 ns D 225 ns D 225 ns D

40 ns D 40 ns D

200 ns D

100 ns D 100 ns D 200 ns D

12

ATA6832

4951A–AUTO–08/06

Figure 9-1. Serial Interface Timing with Chart Number

ATA6832

CS

CLK

1

CS

DO

4

5

3

6 8

2

9

7

DI

11

CLK

10 12

DO

Inputs DI, CLK, CS: High level = 0.7 × VCC, low level = 0.3 × V Output DO: High level = 0.8 × V

, low level = 0.2 × V

CC

4951A–AUTO–08/06

13

10. Application Circuit

Figure 10-1. Application Circuit

V

CC

U5021M

Watchdog

Reset

Micro-

controller

V

Trigger

CC

CLK

CS

DO

PWM

V

O

S

L

S

C

D

I

Input register Ouput register

I

O

DI

4

5

3

7

6

P S F

Faul t

detector

Faul t

detector

N

V

H

L

P H 3

n.u.n.

2

P L 3

u.

OUT3

P

H

2

n.u.n.

Faul t

detector

Faul t

detector

P

L

H

L

2

1

n.

u.

12

H

L

S

3

Serial interface

H

L

S

3

Faul t

detector

Faul t

detector

OUT2

H

L

H

L

S

2

H

L

S

2

S

R

1

R

Charge

pump

T

H

L

P

S

1

UV

protection

Control

logic

Thermal

protection

15

OUT1

Power on

reset

10

VS1

11

VS2

9

VCC

8

GND

14

GND

17

GND

18

GND

BYV28

+

S

V

Batt

13V

V

CC

V

CC

5V

+

10.1 Application Notes

• Connect the blocking capacitors at VCC and VS as close as possible to the power supply and

• Recommended value for capacitors at V

• To reduce thermal resistance, place cooling areas on the PCB as close as possible to the

14

ATA6832

MM

GND pins.

:

S

– Electrolytic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. The

value for the electrolytic capacitor depends on external loads, conducted interferences, and the reverse conducting current I

:

CC

Out1,2,3

.

– Electrolytic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF.

GND pins and to the die pad.

4951A–AUTO–08/06

11. Ordering Information

Extended Type Number Package Remarks

ATA6832-PFQW QFN18 Taped and reeled, Pb-free

12. Package Information

ATA6832

Package: VQFN_4 x 4_18L Exposed pad 2.5 x 3.125 Dimensions in mm

Not indicated tolerances ±0.05

Top

18

1

Pin 1 identification

6

Drawing-No.: 6.543-5133.01-4 Issue: preliminary copy; 06.10.06

Bottom

2.5

Z

13 18

12

3.125±0.15

4

0.2

±0.1

0.9

Z 10:1

0.23±0.07

7

2.6

technical drawings according to DIN specifications

0.45±0.1

0.5 nom.

1

2.5

6

±0.15

4951A–AUTO–08/06

15

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4951A–AUTO–08/06