Rainbow Electronics ATA6831 User Manual
Features
• Supply Voltage up to 40V
• R
• Up to 1.0A Output Current
• Three Half-bridge Outputs Formed by Three High-side and Three Low-side Drivers
• Capable of Switching Loads such as DC Motors, Bulbs, Resistors, Capacitors, and
• PWM Capability up to 25 kHz for Each High-side Output Controlled by External PWM
• No Shoot-through Current
• Very Low Quiescent Current I
• Outputs Short-circuit Protected
• Selective Overtemperature Protection for Each Switch and Overtemperature
• Undervoltage Protection
• Various Diagnostic Functions such as Shorted Output, Open Load, Overtemperature
• Serial Data Interface, Daisy Chain Capable, up to 2 MHz Clock Frequency
• QFN18 Package
Typically 0.8Ω at 25°C, Maximum 1.5Ω at 150°C
DSon
Inductors
Signal
< 5 µA in Standby Mode over Total Temperature Range
S
Prewarning
and Power-supply Fail Detection
1. Description
The ATA6831 provides fully protected driver interfaces designed in SOI technology.
They are used to allow a microcontroller to control up to 3 different loads in automotive and industrial applications.
Triple
Half-bridge
Driver with SPI
and PWM
ATA6831
Each of the 3 high-side and 3 low-side drivers is capable of driving currents up to
1.0A. Due to the enhanced PWM signal (up to 25 kHz) it is possible to generate a
smooth control of, for example, a DC motor without any noise. The drivers are internally connected to form 3 half-bridges and can be controlled separately from a
standard serial data interface, enabling all kinds of loads, such as bulbs, resistors,
capacitors and inductors, to be combined. The IC design especially supports the
application of H-bridges to drive DC motors.
Protection is guaranteed with respect to short-circuit conditions, overtemperature and
undervoltage. Various diagnostic functions and a very low quiescent current in
standby mode enable a wide range of applications. Automotive qualification (protection against conducted interferences, EMC protection and 2-kV ESD protection) gives
added value and enhanced quality for exacting requirements of automotive
applications.
4908D–AUTO–09/06
Figure 1-1. Block Diagram
S
I
Input register
Ouput register
DI
4
CLK
5
CS
3
DO
7
PWM
6
P
S
F
detector
detector
Faul t
Faul t
H
L
H
L
H
O
O
L
S
D
C
I
O
N
V
H
L
P
H
3
n.u.n.
1/2
P
L
3
u.
OUT3
P
H
2
n.u.n.
Faul t
detector
Faul t
detector
P
P
L
H
2
1
n.
u.
u.
12/13
L
P
L
1
n.
u.
S
S
3
3
Serial interface
H
L
S
S
3
3
Faul t
detector
Faul t
detector
OUT2
S
S
2
2
H
L
S
S
2
2
15/16
S
S
S
R
1
1
R
Charge
pump
H
L
S
1
OUT1
T
P
Control
logic
Thermal
protection
UV
protection
Power on
reset
S
1
10
VS1
11
VS2
9
VCC
8
GND
14
GND
17
GND
18
GND
2
ATA6831
4908D–AUTO–09/06
2. Pin Configuration
Figure 2-1. Pinning QFN18
PGND3
PGND1
OUT1S
OUT1F
PGND2
OUT2S
CS
DI
18 17 16 15 1314
1
2
3
4
5
6
12
11
10
9
8
7
OUT3S
OUT3F
CLK
PWM
Table 2-1. Pin Description
Pin Symbol Function
1 OUT3S Sense pin, used only for final testing
Half-bridge output 3; formed by internally connecting power MOS high-side switch 3 and low-side switch 3
2 OUT3F
3CS
4DI
5CLK
6 PWM PWM input; 5V CMOS logic level input with internal pull-down
7DO
8 GND Ground
9 VCC Logic supply voltage (5V)
10 VS1 Power supply for output stages OUT1 and OUT2; internal supply
11 VS2 Power supply for output stages OUT2 and OUT3; internal supply
12 OUT2F
13 OUT2S Sense pin, used only for final testing
14 PGND2 Power ground OUT2
15 OUT1F
16 OUT1S Sense pin, used only for final testing
17 PGND1 Power ground OUT1
18 PGND3 Power ground OUT3
with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and
open load
Chip select input; 5V CMOS logic level input with internal pull-up;
low = serial communication is enabled, high = disabled
Serial data input; 5V CMOS logic level input with internal pull-down; receives serial data from the control
device; DI expects a 16-bit control word with LSB transferred first
Serial clock input; 5V CMOS logic level input with internal pull-down;
controls serial data input interface and internal shift register (f
Serial data output; 5V CMOS logic-level tri-state output for output (status) register data; sends 16-bit status
information to the microcontroller (LSB transferred first); output will remain tri-stated unless device is
selected by CS = low; this allows several ICs to operate on only one data-output line
Half-bridge output 2; formed by internally connected power MOS high-side switch 2 and low-side switch 2
with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and
open load
Half-bridge output 1; formed by internally connected power MOS high-side switch 1 and low-side switch 1
with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and
open load
OUT2F
VS2
VS1
VCC
GND
DO
= 2 MHz)
max
ATA6831
4908D–AUTO–09/06
3
3. Functional Description
3.1 Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized
to CLK and is accepted on the falling edge of the CLK signal. The LSB (bit 0, SRR) has to be
transferred first. Execution of new input data is enabled on the rising edge of the CS signal.
When CS is high, pin DO is in tri-state condition. This output is enabled on the falling edge of
CS. Output data will change their state with the rising edge of CLK and stay stable until the next
rising edge of CLK appears. LSB (bit 0, TP) is transferred first.
Figure 3-1. Data Transfer
CS
CLK
DO
DI
SRR LS1 HS1 LS2 HS2 LS3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TP S1L S1H S2L S2H S3L S3H n. u.
HS3
nPL!
PH1 PL2 PH2 PL3 PH3
n. u. n. u. n. u. n. u. n. u. OVl INH PSF
OLD
OCS SI
Table 3-1. Input Data Protocol
Bit Input Register Function
0SRR
1 LS1 Controls output LS1 (high = switch output LS1 on)
2 HS1 Controls output HS1 (high = switch output HS1 on)
3 LS2 See LS1
4 HS2 See HS1
5 LS3 See LS1
6 HS3 See HS1
7 PL1 Output LS1 additionally controlled by PWM Input
8 PH1 Output HS1 additionally controlled by PWM Input
9 PL2 See PL1
10 PH2 See PH1
11 PL3 See PL1
12 PH3 See PH1
13 OLD Open load detection (low = on)
14 OCS Overcurrent shutdown (high = overcurrent shutdown is active)
15 SI
Status register reset (high = reset; the bits PSF and OVL in the output
data register are set to low)
Software inhibit; low = standby, high = normal operation
(data transfer is not affected by the standby function because the digital
part is still powered)
4
ATA6831
4908D–AUTO–09/06
Table 3-2. Output Data Protocol
Output (Status)
Bit
0 TP Temperature prewarning: high = warning
1 Status LS1
2 Status HS1
3 Status LS2 Description see LS1
4 Status HS2 Description see HS1
5 Status LS3 Description see LS1
6 Status HS3 Description see HS1
7 n. u. Not used
8 n. u. Not used
9 n. u. Not used
10 n. u. Not used
11 n. u. Not used
12 n. u. Not used
13 OVL
14 INH
15 PSF Power-supply fail: undervoltage at pin VS detected
Register Function
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is
switched off); not affected by SRR
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is
switched off); not affected by SRR
Over-load detected: set high, when at least one output is switched off
by a short-circuit condition or an overtemperature event. Bits 1 to 6 can
be used to detect the affected switch
Inhibit: this bit is controlled by software (bit SI in input register)
High = standby, low = normal operation
ATA6831
4908D–AUTO–09/06
5
After power-on reset, the input register has the following status:
Bit 15SIBit 14
OCS
HHHLLLLLLLLLLLLL
Bit 13
OLD
Bit 12
PH3
Bit 11
PL3
Bit 10
PH2
Bit 9
PL2
Bit 8
PH1
Bit 7
PL1
Bit 6
HS3
Bit 5
LS3
Bit 4
HS2
Bit 3
LS2
Bit 2
HS1
Bit 1
LS1
Bit 0
SRR
The following patterns are used to enable internal test modes of the IC. Do not use these patterns during normal operation.
Bit 15 Bit 14 Bit 13
(OCS)
HHHHHLLLLLLLLLLL
HHHLLHHLLLLLLLLL
HHHLLLLHHLLLLLLL
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6
(HS3)
Bit 5
(LS3)
Bit 4
(HS2)
Bit 3
(LS2)
Bit 2
(HS1)
Bit 1
(LS1)
Bit 0
(SRR)
3.2 Power-supply Fail
If undervoltage is detected at pin VS, the power-supply fail bit (PSF) in the output register is set
and all outputs are disabled. To detect an undervoltage, its duration has to last longer than the
undervoltage detection delay time t
voltage returns to the normal operational value. The PSF bit stays high until it is reset by the
SRR bit in the input register.
. The outputs are enabled immediately when the supply
dUV
3.3 Open-load Detection
If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and
a pull-down current for each low-side switch is turned on (open-load detection current I
the current through the external load does not reach the open-load detection current, the corresponding bit of the output in the output register is set to high.
Switching on an output stage with the OLD bit set to low disables the open-load function for this
output.
OUT1-3
). If
6
ATA6831
4908D–AUTO–09/06
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