Rainbow Electronics ATA6827 User Manual

Features

• Supply Voltage up to 40V

• R

• Up to 1.0A Output Current

• Three Half-bridge Outputs Formed by Three High-side and Three Low-side Drivers

• Capable to Switch all Kinds of Loads Such as DC Motors, Bulbs, Resistors, Capacitors

• No Shoot-through Current

• Outputs Short-circuit Protected

• Overtemperature Protection for Each Switch and Overtemperature Prewarning

• Undervoltage Protection

• Various Diagnostic Functions Such as Shorted Output, Open-load, Overtemperature

• Serial Data Interface, Daisy Chain Capable, up to 2 MHz Clock Frequency

• QFN18 Package

Typically 0.8Ω at 25°C, Maximum 1.8Ω at 200°C

DSon

and Inductors

and Power-supply Fail Detection

High
Temperature
Triple
Half-bridge

1. Description

The ATA6827 is a fully protected driver IC specially designed for high temperature
applications. In mechatronic solutions, for example turbo charger or exhaust gas recir­culation systems, many flaps have to be controlled by DC motor driver ICs which are
located very close to the hot engine or actuator where ambient temperatures up to
150°C are usual. Due to the advantages of SOI technology junction temperatures up
to 200°C are allowed. This enables new cost effective board design possibilities to
achieve complex mechatronic solutions.

The ATA6827 is a fully protected Triple Half-Bridge to control up to 3 different loads by
a microcontroller in automotive and industrial applications. Each of the 3 high-side and
3 low-side drivers is capable to drive currents up to 1.0A. The drivers are internally
connected to form 3 half-bridges and can be controlled separately from a standard
serial data interface. Therefore, all kinds of loads such as bulbs, resistors, capacitors
and inductors can be combined. The IC design especially supports the application of
H-bridges to drive DC motors.

Protection is guaranteed regarding short-circuit conditions, overtemperature and und­ervoltage. Various diagnostic functions and a very low quiescent current in standby
mode opens a wide range of applications. Automotive qualification gives added value
and enhanced quality for exacting requirements of automotive applications.

Driver with
Serial Input
Control

ATA6827

Preliminary

4912C–AUTO–10/06

Figure 1-1. Block Diagram

n.u.n.

Input register
Ouput register

DI

4

CLK

5

CS

3

INH

8

DO

7

P
S
F

detector

detector

Faul t

Faul t

H

L

H

L

H

O
S
C

u.

O

S

P

C

L

D

1/2

n.u.n.

n.u.n.

n.u.n.u.n.u.n.

u.

n.u.n.

u.

Faul t

detector

Faul t

detector

OUT3

n.
u.

u.

12/13

L

S

S
3

u.

H

n.

S

u.

3

OUT2

S

S

2

2

3

Serial interface

L

H

L

S

S

S

3

2

2

Faul t

detector

Faul t

detector

15/16

S

S

S

R

1

1

R

Charge

pump

L
S
1

OUT1

T
P

Control

logic

Thermal

protection

UV

protection

Power on

reset

H
S
1

10

VS

11

VS

9

VCC

14

GND

17

GND

18

GND

6

GND

2

ATA6827 [Preliminary]

4912C–AUTO–10/06

ATA6827 [Preliminary]

2. Pin Configuration

Figure 2-1. Pinning QFN18

PGND3

PGND1

OUT1S

OUT1F

PGND2

OUT2S

CS

DI

18 17 16 15 1314

1
2
3
4
5
6

OUT3S

OUT3

CLK

GND

Table 2-1. Pin Description

Pin Symbol Function

1 OUT3S Sense OUT3, internal connected to pin 2 via lead
2 OUT3 Half-bridge output 3

3 CS

4 DI

5 CLK

6 GND Ground; reference potential

7 DO

8 INH Inhibit input; 5-V logic input with internal pull down; low = standby, high = normal operation

9 VCC Logic supply voltage (5 V)
10 VS Power supply for output stages OUT1, OUT2 and OUT3, internal supply
11 VS Power supply for output stages OUT1, OUT2 and OUT3, internal supply
12 OUT2 Half-bridge output 2

13

OUT2S

14 PGND2 Power Ground OUT2
15 OUT1F Half-bridge output 1
16 OUT1S Sense OUT1, internal connected to pin 15 via lead

17

18

PGND1
PGND3

PGND1
PGND3

Chip select input; 5-V CMOS logic level input with internal pull up;
low = serial communication is enabled, high = disabled

Serial data input; 5-V CMOS logic level input with internal pull down; receives serial data from the control
device; DI expects a 16-bit control word with LSB being transferred first

Serial clock input; 5-V CMOS logic level input with internal pull down;
controls serial data input interface and internal shift register (f

Serial data output; 5-V CMOS logic level tri-state output for output (status) register data; sends 16-bit
status information to the microcontroller (LSB is transferred first); output will remain tri-stated unless
device is selected by CS = low, therefore, several ICs can operate on one data output line only.

Sense OUT2, internal connected to pin 12 via bond; OUT2 controlled loads have to be connected to pin
12 OUT2F

Power Ground OUT1 and OUT3

Power Ground OUT1 and OUT3

12
11
10

OUT2
VS
VS
VCC

9

INH

8

DO

7

= 2 MHz)

max

4912C–AUTO–10/06

3

3. Functional Description

3.1 Serial Interface

Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized
to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be trans­ferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS
is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output
data will change their state with the rising edge of CLK and stay stable until the next rising edge
of CLK appears. LSB (bit 0, TP) is transferred first.

Figure 3-1. Data Transfer

CS

CLK

DO

DI

SRR LS1 HS1 LS2 HS2 LS3

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

TP S1L S1H S2L S2H S3L S3H n. u.

HS3

n. u.

n. u. n. u. n. u. n. u. n. u.

n. u. n. u. n. u. n. u. n. u. SCD OPL PSF

OCS

n. u. n. u.

Table 3-1. Input Data Protocol

Bit Input Register Function

0SRR

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15

LS1 Controls output LS1 (high = switch output LS1 on)

HS1 Controls output HS1 (high = switch output HS1 on)

LS2 See LS1

HS2 See HS1

LS3 See LS1
HS3 See HS1
n. u. Not used
n. u. Not used
n. u. Not used
n. u. Not used
n. u. Not used
n. u. Not used

OCS Overcurrent shutdown (high = overcurrent shutdown is active)

n. u. Not used
n. u. Not used

Status register reset (high = reset; the bits PSF, OPL and SCD in the
output data register are set to low)

4

ATA6827 [Preliminary]

4912C–AUTO–10/06

ATA6827 [Preliminary]

Table 3-2. Output Data Protocol

Output (Status)

Bit

0 TP Temperature prewarning: high = warning
1
2
3
4
5
6
7
8

9
10
11
12

13

14

15

Register Function

Status LS1 High = output is on, low = output is off; not affected by SRR

Status HS1 High = output is on, low = output is off; not affected by SRR

Status LS2 Description see LS1

Status HS2 Description see HS1

Status LS3 Description see LS1

Status HS3 Description see HS1

n. u. Not used
n. u. Not used
n. u. Not used
n. u. Not used
n. u. Not used
n. u. Not used

Short circuit detected: set high when at least one high-side or low-side

SCD

OPL

PSF Power-supply fail: undervoltage at pin VS detected

switch is switched off by a short-circuit condition. Bits 1 to 6 can be used
to detect the shorted switch.

Open load detected: set high, when at least one active high-side or
low-side switch sinks/sources a current below the open load threshold
current.

After power-on reset, the input register has the following status:

Bit 15 Bit 14 Bit 13

(OCS)

xxHxxxxxxLLLLLLL

Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6

(HS3)

Bit 5

(LS3)

Bit 4

(HS2)

Bit 3

(LS2)

Bit 2

(HS1)

Bit 1

(LS1)

Bit 0

(SRR)

The following patterns are used to enable internal test modes of the IC. It is not recommended to use these patterns during
normal operation.

Bit 15 Bit 14 Bit 13

(OCS)

HHHHHLLLLLLLLLLL
HHHLLHHLLLLLLLLL
HHHLLLLHHLLLLLLL

Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6

(HS3)

Bit 5

(LS3)

Bit 4

(HS2)

Bit 3

(LS2)

Bit 2

(HS1)

Bit 1

(LS1)

Bit 0

(SRR)

4912C–AUTO–10/06

5