Rainbow Electronics ATA6824 User Manual

Features

• PWM and Direction-controlled Driving of Four Externally-powered NMOS Transistors

• High Temperature Capability up to 200° C Junction

• A Programmable Dead Time Is Included to Avoid Peak Currents Within the H-bridge

• Integrated Charge Pump to Provide Gate Voltages for High-side Drivers and to Supply

the Gate of the External Battery Reverse Protection NMOS

• 5V/3.3V Regulator and Current Limitation Function

• Reset Derived From 5V/3.3V Regulator Output Voltage

• A Programmable Window Watchdog

• Battery Overvoltage Protection and Battery Undervoltage Management

• Overtemperature Warning and Protection (Shutdown)

• High Voltage Serial Interface for Communication

• QFN32 Package

High
Temperature
H-bridge Motor

1. Description

The ATA6824 is designed for high temperature mechatronic applications, for example
turbo chargers, where the electronic is mounted very close to the hot engine. In such
harsch environments the ICs have to withstand temperatures up to 150°C ambient
which results in junction temperatures up to 200° C. The IC is used to drive a continu­ous current motor in a full H-bridge configuration. An external microcontroller controls
the driving function of the IC by providing a PWM signal and a direction signal and
allows the use of the IC in a motor-control application. The PWM control is performed
by the low-side switch; the high-side switch is permanently on in the driving phase.
The VMODE configuration pin can be set to 5V or 3.3V mode (for regulator and inter­face high level). The window watchdog has a programmable time, programmable by
choosing a certain value of the external watchdog resistor RWD, internally trimmed to
an accuracy of 10%. To communicate with a host controller there is a HV Serial Inter­face integrated.

Driver

ATA6824

Preliminary

4931C–AUTO–09/06

Figure 1-1. Block Diagram

M

CP

VRES H2

CPLO

Charge

Pump

CPIH

VG

PBAT

VBAT

CP

VINT

VBAT

VBATSW

12V

Regulator

Vint 5V

Regulator

VCC 5V

Regulator

VCC

R

GATE

HS Driver 2

OTP

12 bit

Oscillator

VBG

Bandgap

VMODE /RESET

R

GATE

H1

HS Driver 1

Logic Control

WD

NC

S1 S2 L2

DIR

R

GATE

LS Driver 1

PWM

R

GATE

LS Driver 2

OT

UV

Supervisor

OV

CC timer

WD timer

Serial

Interface

TXRX

PGNDL1

VBAT

GND

DG3

DG2

DG1

CC

NC

SIO

Microcontroller

Battery

2

ATA6824 [Preliminary]

4931C–AUTO–09/06

2. Pin Configuration

/

Figure 2-1. Pinning QFN32

VMODE

VINT
RWD

CC

RESET

WD

GND

SIO

NC

VBATSW

VBAT

VCC

PGNDL1L2

32 31 30 29 28 27 26 25

1
2
3

Atmel YWW

4
5
6
7
8

ATA6824

ZZZZZ-AL

9 10 11 12 13 14 15 16

PBAT

24
23
22
21
20
19
18
17

ATA6824 [Preliminary]

VG
CPLO
CPHI
VRES
H2
S2
H1
S1

Table 2-1. Pin Description

Pin Symbol I/O Function

1 VMODE I Selector for V
2 VINT I/O Blocking capacitor 220 nF/10V/X7R
3 RWD I Resistor defining the watchdog interval
4 CC I/O RC combination to adjust cross conduction time
5 /RESET O Reset signal for microcontroller
6 WD I Watchdog trigger signal
7 GND I Ground for chip core
8 SIO I/O High Voltage (HV) serial interface

9 TX I Transmit signal to serial interface from microcontroller
10 DIR I Defines the rotation direction for the motor
11 PWM I PWM input controls motor speed
12 NC – Not connected
13 RX O Receive signal from LIN bus for microcontroller
14 DG3 O Diagnostic output 3
15 DG2 O Diagnostic output 2
16 DG1 O Diagnostic output 1
17 S1 I/O Source voltage H-bridge, high-side 1
18 H1 O Gate voltage H-bridge, high-side 1
19 S2 I/O Source voltage H-bridge, high-side 2
20 H2 O Gate voltage H-bridge, high-side 2
21 VRES I/O Gate voltage for reverse protection NMOS, blocking capacitor 470 nF/25V/X7R

TX

DIR

NC

PWM

RX

DG3

DG2

DG1

Note: YWW Date code (Y = Year - above 2000, WW = week number)

ATA6824 Product name
ZZZZZ Wafer lot number
AL Assembly sub-lot number

and interface logic voltage level

CC

4931C–AUTO–09/06

3

Table 2-1. Pin Description (Continued)

Pin Symbol I/O Function

22 CPHI I
23 CPLO O
24 VG I/O Blocking capacitor 470 nF/25V/X7R
25 PBAT I Power supply (after reverse protection) for charge pump and H-bridge
26 L2 O Gate voltage H-bridge, low-side 2
27 L1 O Gate voltage H-bridge, low-side 1
28 PGND I Power ground for H-bridge and charge pump
29 VCC O 5V/100 mA supply for microcontroller, blocking capacitor 2.2 µF/10V/X7R
30 VBAT I Supply voltage for IC core (after reverse protection)
31 VBATSW O 100Ω PMOS switch from V
32 NC – Not connected

Charge pump capacitor 220 nF/25V/X7R

BAT

3. General Statement and Conventions

• Parameter values given without tolerances are indicative only and not to be tested in
production

• Parameters given with tolerances but without a parameter number in the first column of
parameter table are “guaranteed by design” (mainly covered by measurement of other
specified parameters). These parameters are not to be tested in production. The tolerances
are given if the knowledge of the parameter tolerances is important for the application

• The lowest power supply voltage is named GND

• All voltage specifications are referred to GND if not otherwise stated

• Sinking current means that the current is flowing into the pin (value is positive)

• Sourcing current means that the current is flowing out of the pin (value is negative)

3.1 Related Documents

• Qualification of integrated circuits according to Atmel® HNO procedure based on AEC-Q100

• AEC-Q100-004 and JESD78 (Latch-up)

• ESD STM 5.1-1998

• CEI 801-2 (only for information regarding ESD requirements of the PCB)

4

ATA6824 [Preliminary]

4931C–AUTO–09/06

4. Application

4.1 General Remark

This chapter describes the principal application for which the ATA6824 was designed. Because
Atmel cannot be considered to understand fully all aspects of the system, application and envi­ronment, no warranties of fitness for a particular purpose are given.

Table 4-1. Typical External Components

ATA6824 [Preliminary]

Component Function Value Tolerance

C
C
C
R
C
C
C
R
C

VINT

VCC

CC

CC

VG

CP

VRES

RWD

SIO

Blocking capacitor at VINT 220 nF, 10V, X7R 10%
Blocking capacitor at VCC 2.2 µF, 10V, X7R 10%
Cross conduction time definition capacitor Typical 330 pF, 100V, COG
Cross conduction time definition resistor Typical 10 kΩ
Blocking capacitor at VG 470 nF, 25V, X7R 10%
Charge pump capacitor 220 nF, 25V, X7R 10%
Reservoir capacitor 470 nF, 25V, X7R 10%
Watchdog time definition resistor Typical 51 kΩ 1%
Filter capacitor for serial interface Typical 220 pF, 100V 10%

5. Functional Description

5.1 Power Supply Unit with Supervisor Functions

5.1.1 Power Supply

The IC is supplied by a reverse-protected battery voltage. To prevent it from destruction, proper
external protection circuitry has to be added. It is recommended to use at least a capacitor com­bination of storage and HF caps behind the reverse protection circuitry and closed to the VBAT
pin of the IC (see Figure 1-1 on page 2).

A fully-internal low-power and low-drop regulator, stabilized by an external blocking capacitor
provides the necessary low-voltage supply needed for the wake-up process. The low-power
band gap reference is trimmed and is used for the bigger VCC regulator, too. All internal blocks
are supplied by the internal regulator.

Note: The internal supply voltage V

Nothing inside the IC except the logic interface to the microcontroller is supplied by the 5V/3.3V
VCC regulator.

A power-good comparator checks the output voltage of the V
chip in reset as long as the voltage is too low.

There is a high-voltage switch which brings out the battery voltage to the pin VBATSW for mea­surement purposes. This switch is switched ON for VCC = HIGH and stays ON in case of a
watchdog reset. The signal can be used to switch on external voltage regulators, etc.

must not be used for any other supply purpose!

INT

regulator and keeps the whole

INT

4931C–AUTO–09/06

5

5.1.2 Voltage Supervisor

This block is intended to protect the IC and the external power MOS transistors against overvolt­age on battery level and to manage undervoltage on it.

Function: in case of both overvoltage alarm (V
nal NMOS motor bridge transistors will be switched off. The failure state will be flagged via DG2.
No other actions will be carried out. The voltage supervision block is connected to VBAT and fil­tered by a first-order low pass with a corner frequency of typical 15 kHz.

5.1.3 Temperature Supervisor

There is a temperature sensor integrated on-chip to prevent the IC from overheating due to a
failure in the external circuitry and to protect the external NMOSFET transistors.

In case of detected overtemperature (180°C), the diagnostic pin DG3 will be switched to “H” to
signalize this event to the microcontroller. It should undertake actions to reduce the power dissi­pation in the IC. In case of detected overtemperature (200°C), the V
including the LIN transceiver will be switched OFF immediately and /RESET will go LOW.

Both temperature thresholds are correlated. The absolute tolerance is ±15°C and there is a
built-in hysteresis of about 10°K to avoid fast oscillations. After cooling down below the 170°C
threshold; the IC will go into Active mode.

The serial interface has a separate thermal shutdown with disabled the low-side driver at typi­cally 200°C.

5.2 5V/3.3V VCC Regulator

The 5V/3.3V regulator is fully integrated on-chip. It requires only a 2.2 µF ceramic capacitor for
stability and has 100 mA current capability. Using the VMODE pin, the output voltage can be
selected to either 5V or 3.3V. Switching of the output voltage during operation is not intended to
be supported. The VMODE pin must be hard-wired to either VINT for 5V or to GND for 3.3V. The
logic HIGH level of the microcontroller interface will be adapted to the VCC regulator voltage.

) and of undervoltage alarm (V

THOV

CC

) the exter-

THUV

regulator and all drivers

The output voltage accuracy is in general < ±3%; in the 5V mode with V
<5%.

To prevent destruction of the IC, the current delivered by the regulator is limited to maximum
160 mA to 320 mA. The delivered voltage will break down and a reset may occur.

Please note that this regulator is the main heat source on the chip. The maximum output current
at maximum battery voltage and high ambient temperature can only guaranteed if the IC is
mounted on an efficient heat sink.

A power-good comparator checks the output voltage of the VCC regulator and keeps the exter­nal microcontroller in reset as long as the voltage is too low.

5.3 Reset and Watchdog Management

The timing basis of the watchdog is provided by the trimmed internal oscillator. Its period T
adjustable via the external resistor R

The watchdog expects a triggering signal (a rising edge) from the microcontroller at the WD
input within a period time window of T
switched off during Sleep mode.

6

ATA6824 [Preliminary]

< 8V it is limited to

VBAT

.

WD

. In order to save current consumption, the watchdog is

WD

4931C–AUTO–09/06

OSC

is

Figure 5-1. Timing Diagram of the Watchdog Function

/

0

res

RESET

ATA6824 [Preliminary]

t

resshortt

t

d

WD

5.3.1 Timing Sequence

For example, with an external resistor R
of the watchdog.

T

The times t

After ramp-up of the battery voltage (power-on reset), the V
reset output, /RESET, stays low for the time t
initial lead time t
edge on WD to start its normal window watchdog sequence. If no rising edge is detected, the
watchdog will reset the microcontroller for t

Times t
receiving a reset from the watchdog, the triggering signal from the microcontroller must hit the
timeframe of t

t

1

= 12.32 µs, t1= 12.1 ms, t2= 9.61 ms, TWD= 16.88 ms ±10%

OSC

= 68 ms and td= 68 ms are fixed values with a tolerance of 10%.

res

d

(close window) and t2 (open window) form the window watchdog sequence. To avoid

1

= 9.61 ms. The trigger event will restart the watchdog sequence.

2

t

2

t

1

=33kΩ ±1% we get the following typical parameters

WD

(typically 68 ms), then switches to high. For an

res

(typically 68 ms for setups in the controller) the watchdog waits for a rising

and wait td for the rising edge on WD.

res

t

d

t

2

regulator is switched on. The

CC

4931C–AUTO–09/06

Figure 5-2. T

versus RWD

WD

60

50

40

30

TWD (ms)

20

10

max

min

0

10 20 30 40 50 60 70 80 90 10

RWD (kΩ)

typ

7

If triggering fails, /RESET will be pulled to ground for a shortened reset time of typically 2 ms.
The watchdog start sequence is similar to the power-on reset.

The internal oscillator is trimmed to a tolerance of < ±10%. This means that t
vary by ±10%. The following calculation shows the worst case calculation of the watchdog
period T

t

1min

t

2min

T

wdmax

T

wdmin

T

= 16.42 ms ±3.15 ms (±19.1%)

wd

which the microcontroller has to provide.

wd

= 0.90 × t1 = 10.87 ms, t
= 0.90 × t2 = 8.65ms, t

= t

+ t

1min

2min

= t

= 13.28 ms

1max

Figure 5-2 on page 7 shows the typical watchdog period T

external resistor R

A reset will be active for V

5.4 High Voltage Serial Interface

A bi-directional bus interface is implemented for data transfer between hostcontroller and the
local microcontroller (SIO).

The transceiver consists of a low side driver (1.2V at 40 mA) with slew rate control, wave shap­ing, current limitation, and a high-voltage comparator followed by a debouncing unit in the
receiver.

= 1.10 × t1 = 13.28 ms

1max

= 1.10 × t2 = 10.57 ms

2max

= 10.87 ms + 8.65 ms = 19.52 ms

.

OSC

CC

< V

tHRESx

; the level V

tHRESx

and t2 can also

1

depending on the value of the

WD

is realized with a hysteresis (HYS

RESth

).

5.4.1 Transmit Mode

During transmission, the data at the pin TX will be transferred to the bus driver to generate a bus
signal on pin SIO.

To minimize the electromagnetic emission of the bus line, the bus driver has an integrated slew
rate control and wave-shaping unit. Transmission will be interrupted in the following cases:

• Thermal shutdown active or overtemperature SIO active

8

ATA6824 [Preliminary]

4931C–AUTO–09/06

Figure 5-3. Definition of Bus Timing Parameters

ATA6824 [Preliminary]

TXD

(input to transmitting Node)

TH

Rec(max)

V

S

(Transceiver
supply
of transmitting
node)

TH

Dom(max)

TH

Rec(min)

TH

Dom(min)

RXD

(output of receiving Node 1)

t

Bit

SIO Bus Signal

t

rx_pdf(1)

t

Bus_dom(max)

t

Bus_dom(min)

t

Bit

t

Bus_rec(min)

t

Bit

Thresholds of
receiving node 1

Thresholds of
receiving node 2

t

Bus_rec(max)

t

rx_pdr(1)

RXD

(output of receiving Node 2)

The recessive BUS level is generated from the integrated 30 kΩ pull-up resistor in series with an
active diode. This diode prevents the reverse current of VBUS during differential voltage
between VSUP and BUS (V

BUS>VSUP

t

rx_pdr(2)

t

rx_pdf(2)

).

4931C–AUTO–09/06

9

5.5 Control Inputs DIR and PWM

5.5.1 Pin DIR

Logical input to control the direction of the external motor to be controlled by the IC. An internal
pull-down resistor is included.

5.5.2 Pin PWM

Logical input for PWM information delivered by external microcontroller. Duty cycle and fre­quency at this pin are passed through to the H-bridge. An internal pull-down resistor is included.

Table 5-1. Status of the IC Depending on Control Inputs and Detected Failures

Control Inputs Driver Stage for External Power MOS Comments

ON DIR PWM H1 L1 H2 L2

0 X X OFF OFF OFF OFF Standby mode
1 0 PWM ON OFF /PWM PWM Motor PWM forward
1 1 PWM /PWM PWM ON OFF Motor PWM reverse

The internal signal ON is high when

• At least one valid trigger has been accepted (SYNC = 1)

•V

is inside the specified range (UV = 0 and nOV = 1)

BAT

• The charge pump has reached its minimum voltage (CPOK = 1) and

• The device is not overheated (OT2 = 0)

In case of a short circuit, the appropriate transistor is switched off after a debounce time of about
10 µs. In order to avoid cross current through the bridge, a cross conduction timer is imple­mented. Its time constant is programmable by means of an RC combination.

10

Table 5-2. Status of the Diagnostic Outputs

Device Status Diagnostic Outputs Comments

CPOK OT1 OV UV SC DG1 DG2 DG3

0 X X X X – 1 – Charge pump failure
X 1 X X X – – 1 Overtemperature warning
X X 1 X X – 1 – Overvoltage
X X X 1 X – 1 – Undervoltage
X X X X 1 1 – – Short circuit

Note: X represents: don't care – no effect)

OT1: Overtemperature warning
OV: Overvoltage of VBAT
UV: Undervoltage of VBAT
SC: Short circuit
CPOK: Charge pump OK

ATA6824 [Preliminary]

4931C–AUTO–09/06

5.6 VG Regulator

The VG regulator is used to generate the gate voltage for the low-side driver. Its output voltage
will be used as one input for the charge pump, which generates the gate voltage for the
high-side driver. The purpose of the regulator is to limit the gate voltage for the external power
MOS transistors to 12V. It needs a ceramic capacitor of 470 nF for stability. The output voltage
is reduced if the supply voltage at VBAT falls below 12V.

5.7 Charge Pump

The integrated charge pump is needed to supply the gates of the external power MOS transis­tors. It needs a shuffle capacitor of 220 nF and a reservoir capacitor of 470 nF. Without load, the
output voltage on the reservoir capacitor is V
dedicated internal oscillator of 100 KHz. The charge pump is designed to reach a good EMC
level.

5.8 Thermal Shutdown

There is a thermal shutdown block implemented. With rising junction temperature, a first warning
level will be reached at 180°C. At this point the IC stays fully functional and a warning will be
sent to the microcontroller. At junction temperature 200°C the VCC regulator will be switched off
and a reset occurs.

ATA6824 [Preliminary]

plus VG. The charge pump is clocked with a

BAT

5.9 H-bridge Driver

The IC includes two push-pull drivers for control of two external power NMOS used as high-side
drivers and two push-pull drivers for control of two external power NMOS used as low-side driv­ers. The drivers are able to be used with standard and logic-level power NMOS.

The drivers for the high-side control use the charge pump voltage to supply the gates with a volt­age of VG above the battery voltage level. The low-side drivers are supplied by VG directly. It is
possible to control the external load (motor) in the forward and reverse direction (see Table 5-1

on page 10). The duty cycle of the PMW controls the speed. A duty cycle of 100% is possible in

both directions.

5.9.1 Cross Conduction Time

To prevent high peak currents in the H-bridge, a non-overlapping phase for switching the exter­nal power NMOS is realized. An external RC combination defines the cross conduction time in
the following way:

t

(µs) = 0.41 × RCC (kΩ) × CCC (nF) (tolerance: ±5% ±0.15 µs)

CC

The RC combination is charged to 5V and the switching level of the internal comparator is 67%
of the start level.

The resistor R
value has to be ≤ 5 nF. Use of COG capacitor material is recommended.

The time measurement is triggered by the PWM or DIR signal crossing the 50% level.

must be greater than 5 kΩ and should be as close as possible to 10 kΩ, the C

CC

CC

4931C–AUTO–09/06

11

Figure 5-4. Timing of the Drivers

PWM or
DIR

Lx

Hx

t

LxHLtLxf

t

HxLH

t

CC

50%

t

Hxr

80%

20%

80%

t

LxLH

t

CC

t

HxHLtHxf

t

t

Lxr

t

The delays t

5.10 Short Circuit Detection

To detect a short in H-bridge circuitry, internal comparators detect the voltage difference
between source and drain of the external power NMOS. If the transistors are switched ON and
the source-drain voltage difference is higher than the value V
>t

(typically 10 µs) the signal SC (short circuit) will be set and the drivers will be switched off

SC

immediately. The diagnostic pin DG1 will be set to “H”. With the next transition on pin PWM, the
bit will be cleared and the corresponding drivers, depending on the DIR pin, will be switched on
again.

There is a PBAT supervision block implemented to detect the possible voltage drop on PBAT
during a short circuit. If the voltage at PBAT falls under V
>t

the drivers will be switched off immediately and DG1 will be set to “H”. It will be cleared as

SC

above.

HxLH

and t

20%

include the cross conduction time tCC.

LxLH

(4V with tolerances) for a time

SC

(5.6V with tolerances) for a time

SCPB

t

12

ATA6824 [Preliminary]

4931C–AUTO–09/06

ATA6824 [Preliminary]

6. Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Pin Description Pin Name Min Max Unit

Ground GND 0 0 V
Power ground PGND –0.3 +0.3 V
Reverse protected battery voltage VBAT –0.3 +40 V
Reverse protected battery voltage PBAT –0.3 +40 V
Digital output /RESET –0.3 V
Digital output DG1, DG2, DG3 –0.3 V

4.9V output, external blocking capacitor VINT –0.3 +5.5 V
Cross conduction time capacitor/resistor

combination

CC –0.3 V

Digital input coming from microcontroller WD –0.3 V
Watchdog timing resistor RWD –0.3 V
Digital input direction control DIR –0.3 V
Digital input PWM control + Test mode PWM –0.3 V
5V regulator output VCC –0.3 +5.5 V
Digital input VMODE –0.3 V
12V output, external blocking capacitor VG –0.3 +16 V
Digital output RX –0.3 V
Digital input TX –0.3 V
LIN data pin SIO –27

(1)

Source external high-side NMOS S1, S2 –2 +30 V
Gates external low-side NMOS L1, L2 V
Gates of external high-side NMOS H1, H2 V

– 0.3 V

PGND

– 1 VS + 16 V

S

Charge pump CPLO –0.3 V
Charge pump CPHI –0.3 V
Charge pump output VRES –0.3 +30 V
Switched VBAT VBATSW –0.3 V
Power dissipation P
Storage temperature ϑ
Soldering temperature (10s) ϑ
Notes: 1. For V

VBAT

≤ 13.5V

tot

STORE

SOLDERING

–55 +200 °C

2. May be additionally limited by external thermal resistance

+ 0.3 V

VCC

+ 0.3 V

VCC

+ 0.3 V

VINT

+ 0.3 V

VINT

+ 0.3 V

VCC

+ 0.3 V

VCC

+ 0.3 V

VCC

+ 0.3 V

VINT

+ 0.3 V

VCC

+ 0.3 V

VCC

V

+ 2 V

VBAT

+ 0.3 V

VG

+ 0.3 V

PBAT

+ 0.3 V

VRES

+ 0.3 V

VBAT

(2)

1.4

240 °C

W

4931C–AUTO–09/06

13

7. Thermal Resistance

Parameters Symbol Value Unit

Thermal resistance junction to heat slug R
Thermal resistance junction to ambient when heat

slug is soldered to PCB

thjc

R

thja

<5 K/W

25 K/W

8. Operating Range

The operating conditions define the limits for functional operation and parametric characteristics of the device. Functionality outside these
limits is not implied unless otherwise stated explicitly.

Parameters Symbol Min Max Unit

Operating supply voltage
Operating supply voltage
Operating supply voltage
Operating supply voltage
Operating supply voltage

(1)

(2)

(3)

(4)

(5)

Junction temperature range under bias T
Normal functionality T
Normal functionality, overtemperature warning T
Drivers for H1, H2, L1, L2, and SIO are switched

OFF, VCC regulator is OFF
Note: 1. Full functionality

2. H-bridge drivers may be switched off (undervoltage detection)

3. H-bridge drivers are switched off, 5V/3.3V regulator with reduced parameters, RESET works correctly

4. H-bridge drivers are switched off, 5V regulator not working, RESET not correct

5. H-bridge drivers are switched off

V
V
V
V
V

VBAT1

VBAT2

VBAT3

VBAT4

VBAT5

j

a

a

T

a

718V
6< 7V
3< 6V
0< 3V

> 20 40 V

–40 +200 °C
–40 +150 °C
180 200 °C

200 220 °C

9. Noise and Surge Immunity

Parameters Test Conditions Value

Conducted interferences ISO 7637-1 Level 4
Interference suppression VDE 0879 Part 2 Level 5
ESD (Human Body Model) ESD S 5.1 2 kV
CDM (Charge Device Model) ESD STM5.3. 500V
Note: 1. Test pulse 5: V

14

ATA6824 [Preliminary]

vbmax

= 40V

4931C–AUTO–09/06

(1)

ATA6824 [Preliminary]

10. Electrical Characteristics

All parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ϑambient ≤ 150°C unless stated otherwise.

No. Parameters Test Conditions Pin Symbol Min Typ Max Unit Type*

1 Power Supply and Supervisor Functions

1.1 Current consumption V

BATVVBAT

= 13.5V

1.2 Internal power supply 2 V

1.3 Band gap voltage V
Overvoltage threshold

1.4
V

BAT

Overvoltage threshold

1.5
hysteresis V

Undervoltage threshold

1.6
V

BAT

Undervoltage threshold

1.7
hysteresis V

On resistance of V

1.8
switch

BAT

BAT

BAT

Measured during
qualification only

Measured during
qualification only

V

VBAT

= 13.5V 31 R

2 5V/3.3V Regulator

2.1 Regulated output voltage

9V < V

= 0 mA to 100 mA

I

load

9V < V

= 0 mA to 80 mA,

2.1a Regulated output voltage

I

load

Ta > 125°C

VCC

VCC

6V < V
I

= 0 mA to 100 mA

load

= 0 mA to 100 mA 29

load

= 0 mA to 100 mA 29

load

> 6V 29 I

VBAT

(2), (3)

2.2 Regulated output voltage

2.3 Line regulation I

2.4 Load regulation I

2.5 Output current limitation V
Serial inductance to C

2.6
including PCB

Serial resistance to C

2.7
including PCB

2.8 Blocking cap at VCC

2.9 HIGH threshold VMODE 1 VMODE H 4.0 V A

2.10 LOW threshold VMODE 1 VMODE L 0.7 V A
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. EN, DIR, PWM = high

2. The use of X7R material is recommended

3. For higher values, stability at zero load is not guaranteed

4. Tested during qualification only

5. Value depends on T

; function tested with digital test pattern

OSC

6. Tested during characterization only

7. Supplied by charge pump

8. See section “Cross Conduction Time”

9. Voltage between source-drain of external switching transistors in active case

10. The short-circuit message will never be generated for switch-on time < t

VBAT

VBAT

VBAT

(1)

< 40V,

< 40V,

≤ 9V

25, 30 I

30 V

30 V

30 V

30 V

29 V

29 V

29 V

regulation

regulation

VBAT1

INT

BG

THOV

TOVhys

THUV

TUVhys

ON_VBATSW

CC1

CC1

CC2

DC line

DC load

OS1

4.84.945.1 V A

1.235 V A

19.8 22.3 V A

11.5VA

6.5 7 V A

0.2 0.4 V A

4.85

(3.2)

4.85

(3.2)

4.75

(3.2)

<1 50 mV A

<10 50 mV A

100 300 mA C

7mAA

100 Ω A

5.15
(3.4)

5.15
(3.4)

5.25
(3.4)

VA

VA

VA

29 ESL 1 20 nH D

29 ESR 0 0.5 Ω D

29 C

VCC

1.5 3.0 µF D

sc

4931C–AUTO–09/06

15

10. Electrical Characteristics (Continued)

All parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ϑambient ≤ 150°C unless stated otherwise.

No. Parameters Test Conditions Pin Symbol Min Typ Max Unit Type*

3 Reset and Watchdog

threshold voltage

V

3.1

CC

level for /RESET
Tracking of reset

3.1a

thres-hold with regulated
output voltage

threshold voltage

V

3.2

3.3

3.4

3.5

3.6

3.7

CC

level for /RESET
Hysteresis of /RESET

level
Length of pulse at

/RESET pin
Length of short pulse at

/RESET pin
Wait for the first WD

trigger
Time for VCC < V

tHRESL

before activating /RESET
Resistor defining internal

3.8

bias currents for
watchdog oscillator

Watchdog oscillator

3.9
period

Watchdog oscillator

3.10

period with internal
resistor

Watchdog input

3.11
low-voltage threshold

Watchdog input

3.12
high-voltage threshold

Hysteresis of watchdog

3.13
input voltage threshold

3.14 Close window

3.15 Open window

Output low-voltage of

3.16
/RESET

* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. EN, DIR, PWM = high

2. The use of X7R material is recommended

3. For higher values, stability at zero load is not guaranteed

4. Tested during qualification only

5. Value depends on T

6. Tested during characterization only

7. Supplied by charge pump

8. See section “Cross Conduction Time”

9. Voltage between source-drain of external switching transistors in active case

10. The short-circuit message will never be generated for switch-on time < t

VMODE = “H”
(VMODE = “L”)

VMODE = “H”
(VMODE = “L”)

VMODE = “H”
(VMODE = “L”)

(4)

(5)

(5)

(5)

(4)

29 V

29 V

29 V

29 HYS

5t

5t

5t

29 t

3R

R

= 33 kΩ 3T

RWD

6V

6V

6V

(5)

(5)

At I

; function tested with digital test pattern

OSC

= 1 mA 5 V

OLRES

tHRESH

CC1-VtHRESH

tHRESL

RESth

res

resshort

d

delayRESL

RWD

OSC

T

OSC_start

ILWD

IHWD

hysWD

t1

t2

OLRES

4.9

(3.25)

100
(70)

4.3

(2.86)

VA

mV A

VA

0.2 V A

6800 T

200 T

6800 T

100

100

100

0.5 2 µs C

10 91 kΩ D

11.09 13.55 µs A

16 24 µs A

0.7 ×

V

VCC

0.3 ×

V

VCC

VA

VA

1VA

980 ×

T

OSC

780 ×

T

OSC

0.4 V A

sc

A

A

A

A

A

16

ATA6824 [Preliminary]

4931C–AUTO–09/06

ATA6824 [Preliminary]

10. Electrical Characteristics (Continued)

All parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ϑambient ≤ 150°C unless stated otherwise.

No. Parameters Test Conditions Pin Symbol Min Typ Max Unit Type*

Internal pull-up resistor at

3.17
pin /RESET

5R

PURES

4 High Voltage Serial Interface

4.1 Low-level output current

Normal mode;
V

=0V, VRX=0.4V

LIN

13 IL

RX

Normal mode;

4.2 High-level output current

V

LIN=VBAT

13 IH

RX

VRX=VCC–0.4V

Driver recessive output

4.3
voltage

Driver dominant voltage

4.4
V

BUSdom_DRV_LoSUP

Driver dominant voltage

4.5
V

BUSdom_DRV_HiSUP

Driver dominant voltage

4.6
V

BUSdom_DRV_LoSUP

Driver dominant voltage

4.7
V

BUSdom_DRV_HiSUP

4.8 Pull up resistor to VS

4.9 Current limitation V
Input leakage current at

the receiver including

4.10
pull-up resistor as

specified

V

TXD

V

VAT

R

load

V

VAT

R

load

V

VAT

R

load

V

VAT

R

load

= 0V; I

= 7.3V
= 500Ω

= 18V
= 500Ω

= 7.3V
= 1000Ω

= 18V
= 1000Ω

= 0 mA 8 V

LIN

The serial diode is
mandatory

= V

BUS

BAT_max

Input leakage current
driver off

= 0V

V

BUS

V

= 12V

BAT

BUSrec

8V

8V

8V

8V

8R

8I

8I

_LoSUP

_HiSUP

_LoSUP_1k

_HiSUP_1k_

LIN

BUS_LIM

BUS_PAS_dom

Driver off

Leakage current SIO

4.11
recessive

8V < V
8V < V
V

BUS

≥ V

BAT
BUS

< 18V

< 18V

BAT

8I

BUS_PAS_rec

Leakage current at
ground loss
Control unit disconnected

4.12

from ground
Loss of local ground must

GND
V

BAT

0V < V

Device

=12V

BUS

= VS

< 18V

8I

BUS_NO_gnd

not affect communication
in the residual network

* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. EN, DIR, PWM = high

2. The use of X7R material is recommended

3. For higher values, stability at zero load is not guaranteed

4. Tested during qualification only

5. Value depends on T

; function tested with digital test pattern

OSC

6. Tested during characterization only

7. Supplied by charge pump

8. See section “Cross Conduction Time”

9. Voltage between source-drain of external switching transistors in active case

10. The short-circuit message will never be generated for switch-on time < t

5 10 15 kΩ D

4mAD

4mAD

0.9 ×

VBAT

V

1.2 V

2V

0.6 V

0.8 V

20 30 60 kΩ D

50 200 mA

–1 mA

30 µA

–1 1 mA

sc

4931C–AUTO–09/06

17

10. Electrical Characteristics (Continued)

All parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ϑambient ≤ 150°C unless stated otherwise.

No. Parameters Test Conditions Pin Symbol Min Typ Max Unit Type*

Node has to sustain the
current that can flow

4.13

under this condition. Bus
must remain operational
under this condition

Center of receiver

4.14
threshold

4.15 Receiver dominant state V

4.16 Receiver recessive state V

4.17 Receiver input hysteresis V

5 Control Inputs DIR, PWM, WD, TX

Input low-voltage

5.1
threshold

Input high-voltage

5.2
threshold

5.3 Hysteresis

5.4 Pull-down resistor DIR, PWN, WD, TX R

5.5 Rise/fall time t

6Charge Pump

6.1 Charge pump voltage Load = 0A 21 VCP

6.2 Charge pump voltage

Period charge pump

6.3
oscillator

CP load current in VG

6.4
without CP load

CP load current in VG

6.5
with CP load

7H-bridge Driver

Low-side driver HIGH

7.1
output voltage

ON-resistance of sink

7.2
stage of pins L1, L2

ON-resistance of source

7.3
stage of pins L1, L2

* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. EN, DIR, PWM = high

2. The use of X7R material is recommended

3. For higher values, stability at zero load is not guaranteed

4. Tested during qualification only

5. Value depends on T

6. Tested during characterization only

7. Supplied by charge pump

8. See section “Cross Conduction Time”

9. Voltage between source-drain of external switching transistors in active case

10. The short-circuit message will never be generated for switch-on time < t

V

disconnected

BAT

V

SUP_Device

0V < V

V

BUS_CNT

(V

EN

EN

HYS

(6)

Load = 3 mA,
C

CP

= GND
< 18V

BUS

=

th_dom+Vth_rec

)/2

8I

8V

= 5V 8 V
= 5V 8 V

= V

= 100 nF

th_rec

– V

th_dom

8V

21 VCP

Load = 0A I

Load = 3 mA,

= 100 nF

C

CP

; function tested with digital test pattern

OSC

BUS

BUS_CNT

BUSdom

BUSrec

BUShys

V

IL

V

IH

0.475 VS 0.5 VS 0.525 VS V

0.6 VS V

0.1 VS 0.175 VS V

0.7 ×

V

VCC

100 µA

0.4 VS V

0.3 ×

V

VCC

VA

VA

HYS 0.7 A

PD

rf

T

100

VGCPz

I

VGCP

V

LxH

R

DSON_LxL,

x = 1, 2

R

DSON_LxH,

x = 1, 2

25 50 100 kΩ D

100 ns D

V

+ V

V

VBAT

VG

– 1

+ V

VBAT

VG

VA

VA

911µsA

100 µA D

3.3 mA A

V

VG

VD

20 Ω A

20 Ω A

sc

18

ATA6824 [Preliminary]

4931C–AUTO–09/06

ATA6824 [Preliminary]

10. Electrical Characteristics (Continued)

All parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ϑambient ≤ 150°C unless stated otherwise.

No. Parameters Test Conditions Pin Symbol Min Typ Max Unit Type*

Output peak current at

7.4

pins L1, L2, switched to

V

= 3V

Lx

LOW
Output peak current at

7.5

pins L1, L2, switched to

V

= 3V

Lx

HIGH
Pull-down resistance at

7.6
pins L1, L2

ON-resistance of sink

7.7
stage of pins H1, H2

ON-resistance of source

7.8
stage of pins H1, H2

Output peak current at

7.9
pins Hx, switched to LOW

Output peak current at

7.10

pins Hx, switched to
HIGH

Static high-side switch

7.11

output low-voltage pins
Hx

Static high-side switch

7.12

output high-voltage pins
H1, H2

V

= 0

Sx

= V

V

Sx

VBAT

V

= 13.5V

VBAT

V

= V

Sx

V

Hx

V

VBAT

= V

V

Sx

V

Hx

= 0V

V

Sx

= 1 mA

I

Hx

= –10 µA

I

Lx

VBAT

= V

VBAT

= 13.5V

VBAT

= V

VBAT

+ 3V

+ 3V

(PWM = static)

Sink resistance between

7.13

Hx and ground in Sleep
mode

Dynamic Parameters

Dynamic high-side switch

7.14

output high-voltage pins
H1, H2

Propagation delay time,

7.15

low-side driver from high
to low

= 5 nF

C

Hx

C

= 100 nF

CB

= 20 kHz

f

PWM

Figure 5-4 on page 12

= 13.5V

V

VBAT

Propagation delay time,

7.16

low-side driver from low to
high

* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. EN, DIR, PWM = high

2. The use of X7R material is recommended

3. For higher values, stability at zero load is not guaranteed

4. Tested during qualification only

5. Value depends on T

; function tested with digital test pattern

OSC

6. Tested during characterization only

7. Supplied by charge pump

8. See section “Cross Conduction Time”

9. Voltage between source-drain of external switching transistors in active case

10. The short-circuit message will never be generated for switch-on time < t

I

LxL,

x = 1, 2

I

LxH,

x = 1, 2

R

PDLx

x = 1, 2

R

DSON_HxL,

x = 1, 2

R

DSON_HxH,

x = 1, 2

I

HxL,

x = 1, 2

I

HxH,

x = 1, 2

V

HxL

x = 1, 2

V

HxHstat1

R

Hxsleep

V

HxHdyn1

t

LxHL

t

LxLH

100 mA D

–100 mA D

30 100 kΩ A

20 Ω A

20 Ω A

100 mA D

–100 mA D

,

V

(7)

VBAT

+

VVG – 1

0.3 V

V

+

VBAT

V

VG

V

310kΩ

V

V

VBAT
VG

+

– 1

V

VBAT

V

VG

+

V

0.5 µs

0.5 + t

sc

CC

µs

4931C–AUTO–09/06

19

10. Electrical Characteristics (Continued)

All parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ϑambient ≤ 150°C unless stated otherwise.

No. Parameters Test Conditions Pin Symbol Min Typ Max Unit Type*

= 13.5V

V

7.17 Fall time low-side driver

7.18 Rise time low-side driver t
Propagation delay time,

7.19

high-side driver from high
to low

Propagation delay time,

7.20

high-side driver from low
to high

7.21 Fall time high-side driver

7.22 Rise time high-side driver t

7.23 Cross conduction time

7.24 External resistor R

7.25 External capacitor C
RON of tCC switching

7.26
transistor

Switching level of t

7.27
comparator

Short circuit detection

7.28
voltage

Short circuit detection

7.29
time

CC

8 Diagnostic Outputs DG1, DG2, DG3

8.1 Low level output current V

8.2 High level output current V
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. EN, DIR, PWM = high

2. The use of X7R material is recommended

3. For higher values, stability at zero load is not guaranteed

4. Tested during qualification only

5. Value depends on T

6. Tested during characterization only

7. Supplied by charge pump

8. See section “Cross Conduction Time”

9. Voltage between source-drain of external switching transistors in active case

10. The short-circuit message will never be generated for switch-on time < t

VBAT

=5 nF

C

Gx

Figure 5-4 on page 12

= 13.5V

V

VBAT

V

= 13.5V,

VBAT

C

= 5 nF

Gx

(8)

(9)

(10)

(6)

= 0.4V

DG

= VCC – 0.4V

DG

; function tested with digital test pattern

OSC

(6)

0.5 µs

0.5 µs

0.5 µs

0.5 + t

CC

0.5 µs

0.5 µs
10 µs

5nF

100 Ω

0.68 ×

V

VCC

t

t

R

V

t

Lxf

Lxr

HxHL

HxLH

t

Hxf

Hxr

t

CC

CC

CC

ONCC

swtcc

V

SC

t

SC

5kΩ

0.653 ×

V

VCC

0.667 ×

V

VCC

3.544.5V

51015ms

IL 4 mA

IH 4 mA

sc

µs

V

20

ATA6824 [Preliminary]

4931C–AUTO–09/06

ATA6824 [Preliminary]

11. Ordering Information

Extended Type Number Package Remarks

ATA6824-PHQW QFN32 Pb-free

12. Package Information

4931C–AUTO–09/06

21

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4931C–AUTO–09/06